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[openwrt/staging/rmilecki.git] / target / linux / pistachio / patches-5.4 / 413-mtd-Introduce-SPI-NAND-framework.patch
1 From 082a89a78e29b15008284df90441747cb742f149 Mon Sep 17 00:00:00 2001
2 From: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
3 Date: Tue, 2 Dec 2014 09:58:52 -0300
4 Subject: mtd: Introduce SPI NAND framework
5
6 Add a new framework, to support SPI NAND devices. The framework registers
7 a NAND chip and handles the generic SPI NAND protocol, calling device-specific
8 hooks for each SPI NAND command.
9
10 The following is the stack design, from userspace to hardware. This commit
11 adds the "SPI NAND core" layer.
12
13 Userspace
14 ------------------
15 MTD
16 ------------------
17 NAND core
18 ------------------
19 SPI NAND core
20 ------------------
21 SPI NAND device
22 ------------------
23 SPI core
24 ------------------
25 SPI master
26 ------------------
27 Hardware
28
29 (based on http://lists.infradead.org/pipermail/linux-mtd/2014-December/056763.html)
30
31 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
32 Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
33 Signed-off-by: Ian Pozella <Ian.Pozella@imgtec.com>
34 ---
35 drivers/mtd/Kconfig | 2 +
36 drivers/mtd/Makefile | 1 +
37 drivers/mtd/spi-nand/Kconfig | 7 +
38 drivers/mtd/spi-nand/Makefile | 1 +
39 drivers/mtd/spi-nand/spi-nand-base.c | 566 +++++++++++++++++++++++++++++++++++
40 include/linux/mtd/spi-nand.h | 54 ++++
41 6 files changed, 631 insertions(+)
42 create mode 100644 drivers/mtd/spi-nand/Kconfig
43 create mode 100644 drivers/mtd/spi-nand/Makefile
44 create mode 100644 drivers/mtd/spi-nand/spi-nand-base.c
45 create mode 100644 include/linux/mtd/spi-nand.h
46
47 --- a/drivers/mtd/Kconfig
48 +++ b/drivers/mtd/Kconfig
49 @@ -373,6 +373,8 @@ source "drivers/mtd/onenand/Kconfig"
50
51 source "drivers/mtd/lpddr/Kconfig"
52
53 +source "drivers/mtd/spi-nand/Kconfig"
54 +
55 source "drivers/mtd/spi-nor/Kconfig"
56
57 source "drivers/mtd/ubi/Kconfig"
58 --- a/drivers/mtd/Makefile
59 +++ b/drivers/mtd/Makefile
60 @@ -37,6 +37,7 @@ inftl-objs := inftlcore.o inftlmount.o
61
62 obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/
63
64 +obj-$(CONFIG_MTD_SPI_NAND) += spi-nand/
65 obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/
66 obj-$(CONFIG_MTD_UBI) += ubi/
67
68 --- /dev/null
69 +++ b/drivers/mtd/spi-nand/Kconfig
70 @@ -0,0 +1,7 @@
71 +menuconfig MTD_SPI_NAND
72 + tristate "SPI NAND device support"
73 + depends on MTD
74 + select MTD_NAND
75 + help
76 + This is the framework for the SPI NAND.
77 +
78 --- /dev/null
79 +++ b/drivers/mtd/spi-nand/Makefile
80 @@ -0,0 +1 @@
81 +obj-$(CONFIG_MTD_SPI_NAND) += spi-nand-base.o
82 --- /dev/null
83 +++ b/drivers/mtd/spi-nand/spi-nand-base.c
84 @@ -0,0 +1,566 @@
85 +/*
86 + * Copyright (C) 2014 Imagination Technologies Ltd.
87 + *
88 + * This program is free software; you can redistribute it and/or modify
89 + * it under the terms of the GNU General Public License as published by
90 + * the Free Software Foundation; version 2 of the License.
91 + *
92 + * Notes:
93 + * 1. Erase and program operations need to call write_enable() first,
94 + * to clear the enable bit. This bit is cleared automatically after
95 + * the erase or program operation.
96 + *
97 + */
98 +
99 +#include <linux/device.h>
100 +#include <linux/err.h>
101 +#include <linux/errno.h>
102 +#include <linux/kernel.h>
103 +#include <linux/module.h>
104 +#include <linux/mtd/rawnand.h>
105 +#include <linux/mtd/mtd.h>
106 +#include <linux/mtd/partitions.h>
107 +#include <linux/mtd/spi-nand.h>
108 +#include <linux/of.h>
109 +#include <linux/slab.h>
110 +
111 +/* Registers common to all devices */
112 +#define SPI_NAND_LOCK_REG 0xa0
113 +#define SPI_NAND_PROT_UNLOCK_ALL 0x0
114 +
115 +#define SPI_NAND_FEATURE_REG 0xb0
116 +#define SPI_NAND_ECC_EN BIT(4)
117 +#define SPI_NAND_QUAD_EN BIT(0)
118 +
119 +#define SPI_NAND_STATUS_REG 0xc0
120 +#define SPI_NAND_STATUS_REG_ECC_MASK 0x3
121 +#define SPI_NAND_STATUS_REG_ECC_SHIFT 4
122 +#define SPI_NAND_STATUS_REG_PROG_FAIL BIT(3)
123 +#define SPI_NAND_STATUS_REG_ERASE_FAIL BIT(2)
124 +#define SPI_NAND_STATUS_REG_WREN BIT(1)
125 +#define SPI_NAND_STATUS_REG_BUSY BIT(0)
126 +
127 +#define SPI_NAND_CMD_BUF_LEN 8
128 +
129 +/* Rewind and fill the buffer with 0xff */
130 +static void spi_nand_clear_buffer(struct spi_nand *snand)
131 +{
132 + snand->buf_start = 0;
133 + memset(snand->data_buf, 0xff, snand->buf_size);
134 +}
135 +
136 +static int spi_nand_enable_ecc(struct spi_nand *snand)
137 +{
138 + int ret;
139 +
140 + ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
141 + if (ret)
142 + return ret;
143 +
144 + snand->buf[0] |= SPI_NAND_ECC_EN;
145 + ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
146 + if (ret)
147 + return ret;
148 + snand->ecc = true;
149 +
150 + return 0;
151 +}
152 +
153 +static int spi_nand_disable_ecc(struct spi_nand *snand)
154 +{
155 + int ret;
156 +
157 + ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
158 + if (ret)
159 + return ret;
160 +
161 + snand->buf[0] &= ~SPI_NAND_ECC_EN;
162 + ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
163 + if (ret)
164 + return ret;
165 + snand->ecc = false;
166 +
167 + return 0;
168 +}
169 +
170 +static int spi_nand_enable_quad(struct spi_nand *snand)
171 +{
172 + int ret;
173 +
174 + ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
175 + if (ret)
176 + return ret;
177 +
178 + snand->buf[0] |= SPI_NAND_QUAD_EN;
179 + ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
180 + if (ret)
181 + return ret;
182 +
183 + return 0;
184 +}
185 +/*
186 + * Wait until the status register busy bit is cleared.
187 + * Returns a negatie errno on error or time out, and a non-negative status
188 + * value if the device is ready.
189 + */
190 +static int spi_nand_wait_till_ready(struct spi_nand *snand)
191 +{
192 + unsigned long deadline = jiffies + msecs_to_jiffies(100);
193 + bool timeout = false;
194 + int ret;
195 +
196 + /*
197 + * Perhaps we should set a different timeout for each
198 + * operation (reset, read, write, erase).
199 + */
200 + while (!timeout) {
201 + if (time_after_eq(jiffies, deadline))
202 + timeout = true;
203 +
204 + ret = snand->read_reg(snand, SPI_NAND_STATUS_REG, snand->buf);
205 + if (ret < 0) {
206 + dev_err(snand->dev, "error reading status register\n");
207 + return ret;
208 + } else if (!(snand->buf[0] & SPI_NAND_STATUS_REG_BUSY)) {
209 + return snand->buf[0];
210 + }
211 +
212 + cond_resched();
213 + }
214 +
215 + dev_err(snand->dev, "operation timed out\n");
216 +
217 + return -ETIMEDOUT;
218 +}
219 +
220 +static int spi_nand_reset(struct spi_nand *snand)
221 +{
222 + int ret;
223 +
224 + ret = snand->reset(snand);
225 + if (ret < 0) {
226 + dev_err(snand->dev, "reset command failed\n");
227 + return ret;
228 + }
229 +
230 + /*
231 + * The NAND core won't wait after a device reset, so we need
232 + * to do that here.
233 + */
234 + ret = spi_nand_wait_till_ready(snand);
235 + if (ret < 0)
236 + return ret;
237 + return 0;
238 +}
239 +
240 +static int spi_nand_status(struct spi_nand *snand)
241 +{
242 + int ret, status;
243 +
244 + ret = snand->read_reg(snand, SPI_NAND_STATUS_REG, snand->buf);
245 + if (ret < 0) {
246 + dev_err(snand->dev, "error reading status register\n");
247 + return ret;
248 + }
249 + status = snand->buf[0];
250 +
251 + /* Convert this into standard NAND_STATUS values */
252 + if (status & SPI_NAND_STATUS_REG_BUSY)
253 + snand->buf[0] = 0;
254 + else
255 + snand->buf[0] = NAND_STATUS_READY;
256 +
257 + if (status & SPI_NAND_STATUS_REG_PROG_FAIL ||
258 + status & SPI_NAND_STATUS_REG_ERASE_FAIL)
259 + snand->buf[0] |= NAND_STATUS_FAIL;
260 +
261 + /*
262 + * Since we unlock the entire device at initialization, unconditionally
263 + * set the WP bit to indicate it's not protected.
264 + */
265 + snand->buf[0] |= NAND_STATUS_WP;
266 + return 0;
267 +}
268 +
269 +static int spi_nand_erase(struct spi_nand *snand, int page_addr)
270 +{
271 + int ret;
272 +
273 + ret = snand->write_enable(snand);
274 + if (ret < 0) {
275 + dev_err(snand->dev, "write enable command failed\n");
276 + return ret;
277 + }
278 +
279 + ret = snand->block_erase(snand, page_addr);
280 + if (ret < 0) {
281 + dev_err(snand->dev, "block erase command failed\n");
282 + return ret;
283 + }
284 +
285 + return 0;
286 +}
287 +
288 +static int spi_nand_write(struct spi_nand *snand)
289 +{
290 + int ret;
291 +
292 + /* Enable quad mode */
293 + ret = spi_nand_enable_quad(snand);
294 + if (ret) {
295 + dev_err(snand->dev, "error %d enabling quad mode\n", ret);
296 + return ret;
297 + }
298 + /* Store the page to cache */
299 + ret = snand->store_cache(snand, 0, snand->buf_size, snand->data_buf);
300 + if (ret < 0) {
301 + dev_err(snand->dev, "error %d storing page 0x%x to cache\n",
302 + ret, snand->page_addr);
303 + return ret;
304 + }
305 +
306 + ret = snand->write_enable(snand);
307 + if (ret < 0) {
308 + dev_err(snand->dev, "write enable command failed\n");
309 + return ret;
310 + }
311 +
312 + /* Get page from the device cache into our internal buffer */
313 + ret = snand->write_page(snand, snand->page_addr);
314 + if (ret < 0) {
315 + dev_err(snand->dev, "error %d reading page 0x%x from cache\n",
316 + ret, snand->page_addr);
317 + return ret;
318 + }
319 +
320 + return 0;
321 +}
322 +
323 +static int spi_nand_read_id(struct spi_nand *snand)
324 +{
325 + int ret;
326 +
327 + ret = snand->read_id(snand, snand->data_buf);
328 + if (ret < 0) {
329 + dev_err(snand->dev, "error %d reading ID\n", ret);
330 + return ret;
331 + }
332 + return 0;
333 +}
334 +
335 +static int spi_nand_read_page(struct spi_nand *snand, unsigned int page_addr,
336 + unsigned int page_offset, size_t length)
337 +{
338 + unsigned int corrected = 0, ecc_error = 0;
339 + int ret;
340 +
341 + /* Load a page into the cache register */
342 + ret = snand->load_page(snand, page_addr);
343 + if (ret < 0) {
344 + dev_err(snand->dev, "error %d loading page 0x%x to cache\n",
345 + ret, page_addr);
346 + return ret;
347 + }
348 +
349 + ret = spi_nand_wait_till_ready(snand);
350 + if (ret < 0)
351 + return ret;
352 +
353 + if (snand->ecc) {
354 + snand->get_ecc_status(ret, &corrected, &ecc_error);
355 + snand->bitflips = corrected;
356 +
357 + /*
358 + * If there's an ECC error, print a message and notify MTD
359 + * about it. Then complete the read, to load actual data on
360 + * the buffer (instead of the status result).
361 + */
362 + if (ecc_error) {
363 + dev_err(snand->dev,
364 + "internal ECC error reading page 0x%x\n",
365 + page_addr);
366 + snand->nand_chip.mtd.ecc_stats.failed++;
367 + } else {
368 + snand->nand_chip.mtd.ecc_stats.corrected += corrected;
369 + }
370 + }
371 +
372 + /* Enable quad mode */
373 + ret = spi_nand_enable_quad(snand);
374 + if (ret) {
375 + dev_err(snand->dev, "error %d enabling quad mode\n", ret);
376 + return ret;
377 + }
378 + /* Get page from the device cache into our internal buffer */
379 + ret = snand->read_cache(snand, page_offset, length, snand->data_buf);
380 + if (ret < 0) {
381 + dev_err(snand->dev, "error %d reading page 0x%x from cache\n",
382 + ret, page_addr);
383 + return ret;
384 + }
385 + return 0;
386 +}
387 +
388 +static u8 spi_nand_read_byte(struct mtd_info *mtd)
389 +{
390 + struct nand_chip *chip = mtd_to_nand(mtd);
391 + struct spi_nand *snand = nand_get_controller_data(chip);
392 + char val = 0xff;
393 +
394 + if (snand->buf_start < snand->buf_size)
395 + val = snand->data_buf[snand->buf_start++];
396 + return val;
397 +}
398 +
399 +static void spi_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
400 +{
401 + struct nand_chip *chip = mtd_to_nand(mtd);
402 + struct spi_nand *snand = nand_get_controller_data(chip);
403 + size_t n = min_t(size_t, len, snand->buf_size - snand->buf_start);
404 +
405 + memcpy(snand->data_buf + snand->buf_start, buf, n);
406 + snand->buf_start += n;
407 +}
408 +
409 +static void spi_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
410 +{
411 + struct nand_chip *chip = mtd_to_nand(mtd);
412 + struct spi_nand *snand = nand_get_controller_data(chip);
413 + size_t n = min_t(size_t, len, snand->buf_size - snand->buf_start);
414 +
415 + memcpy(buf, snand->data_buf + snand->buf_start, n);
416 + snand->buf_start += n;
417 +}
418 +
419 +static int spi_nand_write_page_hwecc(struct mtd_info *mtd,
420 + struct nand_chip *chip, const uint8_t *buf, int oob_required,
421 + int page)
422 +{
423 + chip->write_buf(mtd, buf, mtd->writesize);
424 + chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
425 +
426 + return 0;
427 +}
428 +
429 +static int spi_nand_read_page_hwecc(struct mtd_info *mtd,
430 + struct nand_chip *chip, uint8_t *buf, int oob_required,
431 + int page)
432 +{
433 + struct spi_nand *snand = nand_get_controller_data(chip);
434 +
435 + chip->read_buf(mtd, buf, mtd->writesize);
436 + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
437 +
438 + return snand->bitflips;
439 +}
440 +
441 +static int spi_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
442 +{
443 + struct spi_nand *snand = nand_get_controller_data(chip);
444 + int ret;
445 +
446 + ret = spi_nand_wait_till_ready(snand);
447 +
448 + if (ret < 0) {
449 + return NAND_STATUS_FAIL;
450 + } else if (ret & SPI_NAND_STATUS_REG_PROG_FAIL) {
451 + dev_err(snand->dev, "page program failed\n");
452 + return NAND_STATUS_FAIL;
453 + } else if (ret & SPI_NAND_STATUS_REG_ERASE_FAIL) {
454 + dev_err(snand->dev, "block erase failed\n");
455 + return NAND_STATUS_FAIL;
456 + }
457 +
458 + return NAND_STATUS_READY;
459 +}
460 +
461 +static void spi_nand_cmdfunc(struct mtd_info *mtd, unsigned int command,
462 + int column, int page_addr)
463 +{
464 + struct nand_chip *chip = mtd_to_nand(mtd);
465 + struct spi_nand *snand = nand_get_controller_data(chip);
466 +
467 + /*
468 + * In case there's any unsupported command, let's make sure
469 + * we don't keep garbage around in the buffer.
470 + */
471 + if (command != NAND_CMD_PAGEPROG) {
472 + spi_nand_clear_buffer(snand);
473 + snand->page_addr = 0;
474 + }
475 +
476 + switch (command) {
477 + case NAND_CMD_READ0:
478 + spi_nand_read_page(snand, page_addr, 0, mtd->writesize);
479 + break;
480 + case NAND_CMD_READOOB:
481 + spi_nand_disable_ecc(snand);
482 + spi_nand_read_page(snand, page_addr, mtd->writesize,
483 + mtd->oobsize);
484 + spi_nand_enable_ecc(snand);
485 + break;
486 + case NAND_CMD_READID:
487 + spi_nand_read_id(snand);
488 + break;
489 + case NAND_CMD_ERASE1:
490 + spi_nand_erase(snand, page_addr);
491 + break;
492 + case NAND_CMD_ERASE2:
493 + /* There's nothing to do here, as the erase is one-step */
494 + break;
495 + case NAND_CMD_SEQIN:
496 + snand->buf_start = column;
497 + snand->page_addr = page_addr;
498 + break;
499 + case NAND_CMD_PAGEPROG:
500 + spi_nand_write(snand);
501 + break;
502 + case NAND_CMD_STATUS:
503 + spi_nand_status(snand);
504 + break;
505 + case NAND_CMD_RESET:
506 + spi_nand_reset(snand);
507 + break;
508 + default:
509 + dev_err(&mtd->dev, "unknown command 0x%x\n", command);
510 + }
511 +}
512 +
513 +static void spi_nand_select_chip(struct mtd_info *mtd, int chip)
514 +{
515 + /* We need this to override the default */
516 +}
517 +
518 +int spi_nand_check(struct spi_nand *snand)
519 +{
520 + if (!snand->dev)
521 + return -ENODEV;
522 + if (!snand->read_cache)
523 + return -ENODEV;
524 + if (!snand->load_page)
525 + return -ENODEV;
526 + if (!snand->store_cache)
527 + return -ENODEV;
528 + if (!snand->write_page)
529 + return -ENODEV;
530 + if (!snand->write_reg)
531 + return -ENODEV;
532 + if (!snand->read_reg)
533 + return -ENODEV;
534 + if (!snand->block_erase)
535 + return -ENODEV;
536 + if (!snand->reset)
537 + return -ENODEV;
538 + if (!snand->write_enable)
539 + return -ENODEV;
540 + if (!snand->write_disable)
541 + return -ENODEV;
542 + if (!snand->get_ecc_status)
543 + return -ENODEV;
544 + return 0;
545 +}
546 +
547 +int spi_nand_register(struct spi_nand *snand, struct nand_flash_dev *flash_ids)
548 +{
549 + struct nand_chip *chip = &snand->nand_chip;
550 + struct mtd_info *mtd = nand_to_mtd(chip);
551 + struct device_node *np = snand->dev->of_node;
552 + const char __maybe_unused *of_mtd_name = NULL;
553 + int ret;
554 +
555 + /* Let's check all the hooks are in-place so we don't panic later */
556 + ret = spi_nand_check(snand);
557 + if (ret)
558 + return ret;
559 +
560 + nand_set_controller_data(chip, snand);
561 + nand_set_flash_node(chip, np);
562 + chip->read_buf = spi_nand_read_buf;
563 + chip->write_buf = spi_nand_write_buf;
564 + chip->read_byte = spi_nand_read_byte;
565 + chip->cmdfunc = spi_nand_cmdfunc;
566 + chip->waitfunc = spi_nand_waitfunc;
567 + chip->select_chip = spi_nand_select_chip;
568 + chip->options |= NAND_NO_SUBPAGE_WRITE;
569 + chip->bits_per_cell = 1;
570 +
571 + mtd_set_ooblayout(mtd, snand->ooblayout);
572 + chip->ecc.read_page = spi_nand_read_page_hwecc;
573 + chip->ecc.write_page = spi_nand_write_page_hwecc;
574 + chip->ecc.mode = NAND_ECC_HW;
575 +
576 + if (of_property_read_bool(np, "nand-on-flash-bbt"))
577 + chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
578 +
579 +#ifdef CONFIG_MTD_OF_PARTS
580 + of_property_read_string(np, "linux,mtd-name", &of_mtd_name);
581 +#endif
582 + if (of_mtd_name)
583 + mtd->name = of_mtd_name;
584 + else
585 + mtd->name = snand->name;
586 + mtd->owner = THIS_MODULE;
587 +
588 + /* Allocate buffer to be used to read/write the internal registers */
589 + snand->buf = kmalloc(SPI_NAND_CMD_BUF_LEN, GFP_KERNEL);
590 + if (!snand->buf)
591 + return -ENOMEM;
592 +
593 + /* This is enabled at device power up but we'd better make sure */
594 + ret = spi_nand_enable_ecc(snand);
595 + if (ret)
596 + return ret;
597 +
598 + /* Preallocate buffer for flash identification (NAND_CMD_READID) */
599 + snand->buf_size = SPI_NAND_CMD_BUF_LEN;
600 + snand->data_buf = kmalloc(snand->buf_size, GFP_KERNEL);
601 +
602 + ret = nand_scan_ident(mtd, 1, flash_ids);
603 + if (ret)
604 + return ret;
605 +
606 + /*
607 + * SPI NAND has on-die ECC, which means we can correct as much as
608 + * we are required to. This must be done after identification of
609 + * the device.
610 + */
611 + chip->ecc.strength = chip->ecc_strength_ds;
612 + chip->ecc.size = chip->ecc_step_ds;
613 +
614 + /*
615 + * Unlock all the device before calling nand_scan_tail. This is needed
616 + * in case the in-flash bad block table needs to be created.
617 + * We could override __nand_unlock(), but since it's not currently used
618 + * by the NAND core we call this explicitly.
619 + */
620 + snand->buf[0] = SPI_NAND_PROT_UNLOCK_ALL;
621 + ret = snand->write_reg(snand, SPI_NAND_LOCK_REG, snand->buf);
622 + if (ret)
623 + return ret;
624 +
625 + /* Free the buffer and allocate a good one, to fit a page plus OOB */
626 + kfree(snand->data_buf);
627 +
628 + snand->buf_size = mtd->writesize + mtd->oobsize;
629 + snand->data_buf = kmalloc(snand->buf_size, GFP_KERNEL);
630 + if (!snand->data_buf)
631 + return -ENOMEM;
632 +
633 + ret = nand_scan_tail(mtd);
634 + if (ret)
635 + return ret;
636 +
637 + return mtd_device_register(mtd, NULL, 0);
638 +}
639 +EXPORT_SYMBOL_GPL(spi_nand_register);
640 +
641 +void spi_nand_unregister(struct spi_nand *snand)
642 +{
643 + kfree(snand->buf);
644 + kfree(snand->data_buf);
645 +}
646 +EXPORT_SYMBOL_GPL(spi_nand_unregister);
647 +
648 +MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@imgtec.com>");
649 +MODULE_DESCRIPTION("Framework for SPI NAND");
650 +MODULE_LICENSE("GPL v2");
651 --- /dev/null
652 +++ b/include/linux/mtd/spi-nand.h
653 @@ -0,0 +1,54 @@
654 +/*
655 + * Copyright (C) 2014 Imagination Technologies Ltd.
656 + *
657 + * This program is free software; you can redistribute it and/or modify
658 + * it under the terms of the GNU General Public License as published by
659 + * the Free Software Foundation; version 2 of the License.
660 + */
661 +
662 +#ifndef __LINUX_MTD_SPI_NAND_H
663 +#define __LINUX_MTD_SPI_NAND_H
664 +
665 +#include <linux/mtd/mtd.h>
666 +#include <linux/mtd/rawnand.h>
667 +
668 +struct spi_nand {
669 + struct nand_chip nand_chip;
670 + struct device *dev;
671 + const char *name;
672 +
673 + u8 *buf, *data_buf;
674 + size_t buf_size;
675 + off_t buf_start;
676 + unsigned int page_addr;
677 + unsigned int bitflips;
678 + bool ecc;
679 + struct mtd_ooblayout_ops *ooblayout;
680 +
681 + int (*reset)(struct spi_nand *snand);
682 + int (*read_id)(struct spi_nand *snand, u8 *buf);
683 +
684 + int (*write_disable)(struct spi_nand *snand);
685 + int (*write_enable)(struct spi_nand *snand);
686 +
687 + int (*read_reg)(struct spi_nand *snand, u8 opcode, u8 *buf);
688 + int (*write_reg)(struct spi_nand *snand, u8 opcode, u8 *buf);
689 + void (*get_ecc_status)(unsigned int status,
690 + unsigned int *corrected,
691 + unsigned int *ecc_errors);
692 +
693 + int (*store_cache)(struct spi_nand *snand, unsigned int page_offset,
694 + size_t length, u8 *write_buf);
695 + int (*write_page)(struct spi_nand *snand, unsigned int page_addr);
696 + int (*load_page)(struct spi_nand *snand, unsigned int page_addr);
697 + int (*read_cache)(struct spi_nand *snand, unsigned int page_offset,
698 + size_t length, u8 *read_buf);
699 + int (*block_erase)(struct spi_nand *snand, unsigned int page_addr);
700 +
701 + void *priv;
702 +};
703 +
704 +int spi_nand_register(struct spi_nand *snand, struct nand_flash_dev *flash_ids);
705 +void spi_nand_unregister(struct spi_nand *snand);
706 +
707 +#endif
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