target/linux/pistachio/patches-5.4/102-spi-img-spfi-Implement-dual-and-quad-mode.patch

   1 From cd2a6af51553d38072cd31699b58d16ca6176ef5 Mon Sep 17 00:00:00 2001
   2 From: Ionela Voinescu <ionela.voinescu@imgtec.com>
   3 Date: Thu, 2 Feb 2017 16:46:14 +0000
   4 Subject: spi: img-spfi: Implement dual and quad mode
   5
   6 For dual and quad modes to work the SPFI controller needs
   7 to have information about command/address/dummy bytes in the
   8 transaction register. This information is not relevant for
   9 single mode, and therefore it can have any value in the
  10 allowed range. Therefore, for any read or write transfers of less
  11 than 8 bytes (cmd = 1 byte, addr up to 7 bytes), SPFI will be
  12 configured, but not enabled (unless it is the last transfer in
  13 the queue). The transfer will be enabled by the subsequent tranfer.
  14 A pending transfer is determined by the content of the transaction
  15 register: if command part is set and tsize is not.
  16
  17 This way we ensure that for dual and quad transactions
  18 the command request size will apear in the command/address part
  19 of the transaction register, while the data size will be in
  20 tsize, all data being sent/received in the same transaction (as
  21 set up in the transaction register).
  22
  23 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
  24 Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
  25 ---
  26  drivers/spi/spi-img-spfi.c | 96 ++++++++++++++++++++++++++++++++++++++++------
  27  1 file changed, 85 insertions(+), 11 deletions(-)
  28
  29 --- a/drivers/spi/spi-img-spfi.c
  30 +++ b/drivers/spi/spi-img-spfi.c
  31 @@ -40,7 +40,8 @@
  32  #define SPFI_CONTROL_SOFT_RESET                        BIT(11)
  33  #define SPFI_CONTROL_SEND_DMA                  BIT(10)
  34  #define SPFI_CONTROL_GET_DMA                   BIT(9)
  35 -#define SPFI_CONTROL_SE                        BIT(8)
  36 +#define SPFI_CONTROL_SE                                BIT(8)
  37 +#define SPFI_CONTROL_TX_RX                     BIT(1)
  38  #define SPFI_CONTROL_TMODE_SHIFT               5
  39  #define SPFI_CONTROL_TMODE_MASK                        0x7
  40  #define SPFI_CONTROL_TMODE_SINGLE              0
  41 @@ -51,6 +52,10 @@
  42  #define SPFI_TRANSACTION                       0x18
  43  #define SPFI_TRANSACTION_TSIZE_SHIFT           16
  44  #define SPFI_TRANSACTION_TSIZE_MASK            0xffff
  45 +#define SPFI_TRANSACTION_CMD_SHIFT             13
  46 +#define SPFI_TRANSACTION_CMD_MASK              0x7
  47 +#define SPFI_TRANSACTION_ADDR_SHIFT            10
  48 +#define SPFI_TRANSACTION_ADDR_MASK             0x7
  49
  50  #define SPFI_PORT_STATE                                0x1c
  51  #define SPFI_PORT_STATE_DEV_SEL_SHIFT          20
  52 @@ -87,6 +92,7 @@
  53   */
  54  #define SPFI_32BIT_FIFO_SIZE                   64
  55  #define SPFI_8BIT_FIFO_SIZE                    16
  56 +#define SPFI_DATA_REQUEST_MAX_SIZE             8
  57
  58  struct img_spfi {
  59         struct device *dev;
  60 @@ -103,6 +109,8 @@ struct img_spfi {
  61         struct dma_chan *tx_ch;
  62         bool tx_dma_busy;
  63         bool rx_dma_busy;
  64 +
  65 +       bool complete;
  66  };
  67
  68  struct img_spfi_device_data {
  69 @@ -123,9 +131,11 @@ static inline void spfi_start(struct img
  70  {
  71         u32 val;
  72
  73 -       val = spfi_readl(spfi, SPFI_CONTROL);
  74 -       val |= SPFI_CONTROL_SPFI_EN;
  75 -       spfi_writel(spfi, val, SPFI_CONTROL);
  76 +       if (spfi->complete) {
  77 +               val = spfi_readl(spfi, SPFI_CONTROL);
  78 +               val |= SPFI_CONTROL_SPFI_EN;
  79 +               spfi_writel(spfi, val, SPFI_CONTROL);
  80 +       }
  81  }
  82
  83  static inline void spfi_reset(struct img_spfi *spfi)
  84 @@ -138,12 +148,21 @@ static int spfi_wait_all_done(struct img
  85  {
  86         unsigned long timeout = jiffies + msecs_to_jiffies(50);
  87
  88 +       if (!(spfi->complete))
  89 +               return 0;
  90 +
  91         while (time_before(jiffies, timeout)) {
  92                 u32 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
  93
  94                 if (status & SPFI_INTERRUPT_ALLDONETRIG) {
  95                         spfi_writel(spfi, SPFI_INTERRUPT_ALLDONETRIG,
  96                                     SPFI_INTERRUPT_CLEAR);
  97 +                       /*
  98 +                        * Disable SPFI for it not to interfere with
  99 +                        * pending transactions
 100 +                        */
 101 +                       spfi_writel(spfi, spfi_readl(spfi, SPFI_CONTROL)
 102 +                       & ~SPFI_CONTROL_SPFI_EN, SPFI_CONTROL);
 103                         return 0;
 104                 }
 105                 cpu_relax();
 106 @@ -494,9 +513,32 @@ static void img_spfi_config(struct spi_m
 107                             struct spi_transfer *xfer)
 108  {
 109         struct img_spfi *spfi = spi_master_get_devdata(spi->master);
 110 -       u32 val, div;
 111 +       u32 val, div, transact;
 112 +       bool is_pending;
 113
 114         /*
 115 +        * For read or write transfers of less than 8 bytes (cmd = 1 byte,
 116 +        * addr up to 7 bytes), SPFI will be configured, but not enabled
 117 +        * (unless it is the last transfer in the queue).The transfer will
 118 +        * be enabled by the subsequent transfer.
 119 +        * A pending transfer is determined by the content of the
 120 +        * transaction register: if command part is set and tsize
 121 +        * is not
 122 +        */
 123 +       transact = spfi_readl(spfi, SPFI_TRANSACTION);
 124 +       is_pending = ((transact >> SPFI_TRANSACTION_CMD_SHIFT) &
 125 +                       SPFI_TRANSACTION_CMD_MASK) &&
 126 +                       (!((transact >> SPFI_TRANSACTION_TSIZE_SHIFT) &
 127 +                       SPFI_TRANSACTION_TSIZE_MASK));
 128 +
 129 +       /* If there are no pending transactions it's OK to soft reset */
 130 +       if (!is_pending) {
 131 +               /* Start the transaction from a known (reset) state */
 132 +               spfi_reset(spfi);
 133 +       }
 134 +
 135 +       /*
 136 +        * Before anything else, set up parameters.
 137          * output = spfi_clk * (BITCLK / 512), where BITCLK must be a
 138          * power of 2 up to 128
 139          */
 140 @@ -509,20 +551,52 @@ static void img_spfi_config(struct spi_m
 141         val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT;
 142         spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select));
 143
 144 -       spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT,
 145 -                   SPFI_TRANSACTION);
 146 +       if (!list_is_last(&xfer->transfer_list, &master->cur_msg->transfers) &&
 147 +               /*
 148 +                * For duplex mode (both the tx and rx buffers are !NULL) the
 149 +                * CMD, ADDR, and DUMMY byte parts of the transaction register
 150 +                * should always be 0 and therefore the pending transfer
 151 +                * technique cannot be used.
 152 +                */
 153 +               (xfer->tx_buf) && (!xfer->rx_buf) &&
 154 +               (xfer->len <= SPFI_DATA_REQUEST_MAX_SIZE) && !is_pending) {
 155 +               transact = (1 & SPFI_TRANSACTION_CMD_MASK) <<
 156 +                       SPFI_TRANSACTION_CMD_SHIFT;
 157 +               transact |= ((xfer->len - 1) & SPFI_TRANSACTION_ADDR_MASK) <<
 158 +                       SPFI_TRANSACTION_ADDR_SHIFT;
 159 +               spfi->complete = false;
 160 +       } else {
 161 +               spfi->complete = true;
 162 +               if (is_pending) {
 163 +                       /* Keep setup from pending transfer */
 164 +                       transact |= ((xfer->len & SPFI_TRANSACTION_TSIZE_MASK) <<
 165 +                               SPFI_TRANSACTION_TSIZE_SHIFT);
 166 +               } else {
 167 +                       transact = ((xfer->len & SPFI_TRANSACTION_TSIZE_MASK) <<
 168 +                               SPFI_TRANSACTION_TSIZE_SHIFT);
 169 +               }
 170 +       }
 171 +       spfi_writel(spfi, transact, SPFI_TRANSACTION);
 172
 173         val = spfi_readl(spfi, SPFI_CONTROL);
 174         val &= ~(SPFI_CONTROL_SEND_DMA | SPFI_CONTROL_GET_DMA);
 175 -       if (xfer->tx_buf)
 176 +       /*
 177 +        * We set up send DMA for pending transfers also, as
 178 +        * those are always send transfers
 179 +        */
 180 +       if ((xfer->tx_buf) || is_pending)
 181                 val |= SPFI_CONTROL_SEND_DMA;
 182 -       if (xfer->rx_buf)
 183 +       if (xfer->tx_buf)
 184 +               val |= SPFI_CONTROL_TX_RX;
 185 +       if (xfer->rx_buf) {
 186                 val |= SPFI_CONTROL_GET_DMA;
 187 +               val &= ~SPFI_CONTROL_TX_RX;
 188 +       }
 189         val &= ~(SPFI_CONTROL_TMODE_MASK << SPFI_CONTROL_TMODE_SHIFT);
 190 -       if (xfer->tx_nbits == SPI_NBITS_DUAL &&
 191 +       if (xfer->tx_nbits == SPI_NBITS_DUAL ||
 192             xfer->rx_nbits == SPI_NBITS_DUAL)
 193                 val |= SPFI_CONTROL_TMODE_DUAL << SPFI_CONTROL_TMODE_SHIFT;
 194 -       else if (xfer->tx_nbits == SPI_NBITS_QUAD &&
 195 +       else if (xfer->tx_nbits == SPI_NBITS_QUAD ||
 196                  xfer->rx_nbits == SPI_NBITS_QUAD)
 197                 val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT;
 198         val |= SPFI_CONTROL_SE;