d96b1d6c3054191b5262de8c2aae9ccce262d3c6
[openwrt/staging/rmilecki.git] / target / linux / mpc85xx / patches-5.10 / 104-powerpc-mpc85xx-change-P2020RDB-dts-file-for-OpenWRT.patch
1 From 93514afd769c305182beeed1f9c4c46235879ef8 Mon Sep 17 00:00:00 2001
2 From: Pawel Dembicki <paweldembicki@gmail.com>
3 Date: Sun, 30 Dec 2018 23:24:41 +0100
4 Subject: [PATCH] powerpc: mpc85xx: change P2020RDB dts file for OpenWRT
5
6 This patch apply chages for OpenWRT in P2020RDB
7 dts file.
8
9 Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
10 ---
11 arch/powerpc/boot/dts/fsl/p2020rdb.dts | 98 +++++++++++++++++---------
12 1 file changed, 63 insertions(+), 35 deletions(-)
13
14 --- a/arch/powerpc/boot/dts/fsl/p2020rdb.dts
15 +++ b/arch/powerpc/boot/dts/fsl/p2020rdb.dts
16 @@ -5,10 +5,15 @@
17 * Copyright 2009-2012 Freescale Semiconductor Inc.
18 */
19
20 +/dts-v1/;
21 +
22 /include/ "p2020si-pre.dtsi"
23
24 +#include <dt-bindings/gpio/gpio.h>
25 +#include <dt-bindings/input/input.h>
26 +
27 / {
28 - model = "fsl,P2020RDB";
29 + model = "Freescale P2020RDB";
30 compatible = "fsl,P2020RDB";
31
32 aliases {
33 @@ -34,48 +39,38 @@
34 0x2 0x0 0x0 0xffb00000 0x00020000>;
35
36 nor@0,0 {
37 - #address-cells = <1>;
38 - #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x1000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 - partition@0 {
45 - /* This location must not be altered */
46 - /* 256KB for Vitesse 7385 Switch firmware */
47 - reg = <0x0 0x00040000>;
48 - label = "NOR (RO) Vitesse-7385 Firmware";
49 - read-only;
50 - };
51 -
52 - partition@40000 {
53 - /* 256KB for DTB Image */
54 - reg = <0x00040000 0x00040000>;
55 - label = "NOR (RO) DTB Image";
56 - read-only;
57 - };
58 + partitions {
59 + compatible = "fixed-partitions";
60 + #address-cells = <1>;
61 + #size-cells = <1>;
62
63 - partition@80000 {
64 - /* 3.5 MB for Linux Kernel Image */
65 - reg = <0x00080000 0x00380000>;
66 - label = "NOR (RO) Linux Kernel Image";
67 - read-only;
68 - };
69 + partition@0 {
70 + /* This location must not be altered */
71 + /* 256KB for Vitesse 7385 Switch firmware */
72 + reg = <0x0 0x00040000>;
73 + label = "NOR (RO) Vitesse-7385 Firmware";
74 + read-only;
75 + };
76
77 - partition@400000 {
78 - /* 11MB for JFFS2 based Root file System */
79 - reg = <0x00400000 0x00b00000>;
80 - label = "NOR (RW) JFFS2 Root File System";
81 - };
82 + partition@40000 {
83 + compatible = "denx,fit";
84 + reg = <0x00040000 0x00ec0000>;
85 + label = "firmware";
86 + };
87
88 - partition@f00000 {
89 - /* This location must not be altered */
90 - /* 512KB for u-boot Bootloader Image */
91 - /* 512KB for u-boot Environment Variables */
92 - reg = <0x00f00000 0x00100000>;
93 - label = "NOR (RO) U-Boot Image";
94 - read-only;
95 + partition@f00000 {
96 + /* This location must not be altered */
97 + /* 512KB for u-boot Bootloader Image */
98 + /* 512KB for u-boot Environment Variables */
99 + reg = <0x00f00000 0x00100000>;
100 + label = "u-boot";
101 + read-only;
102 + };
103 };
104 };
105
106 @@ -85,6 +80,7 @@
107 compatible = "fsl,p2020-fcm-nand",
108 "fsl,elbc-fcm-nand";
109 reg = <0x1 0x0 0x40000>;
110 + nand-ecc-mode = "none";
111
112 partition@0 {
113 /* This location must not be altered */
114 @@ -140,13 +136,43 @@
115 soc: soc@ffe00000 {
116 ranges = <0x0 0x0 0xffe00000 0x100000>;
117
118 + gpio0: gpio-controller@fc00 {
119 + };
120 +
121 i2c@3000 {
122 + temperature-sensor@4c {
123 + compatible = "adi,adt7461";
124 + reg = <0x4c>;
125 + };
126 +
127 + eeprom@50 {
128 + compatible = "atmel,24c256";
129 + reg = <0x50>;
130 + };
131 +
132 rtc@68 {
133 compatible = "dallas,ds1339";
134 reg = <0x68>;
135 };
136 };
137
138 + i2c@3100 {
139 + pmic@11 {
140 + compatible = "zl2006";
141 + reg = <0x11>;
142 + };
143 +
144 + gpio@18 {
145 + compatible = "nxp,pca9557";
146 + reg = <0x18>;
147 + };
148 +
149 + eeprom@52 {
150 + compatible = "atmel,24c01";
151 + reg = <0x52>;
152 + };
153 + };
154 +
155 spi@7000 {
156 flash@0 {
157 #address-cells = <1>;
158 @@ -200,10 +225,12 @@
159 phy0: ethernet-phy@0 {
160 interrupts = <3 1 0 0>;
161 reg = <0x0>;
162 + reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
163 };
164 phy1: ethernet-phy@1 {
165 interrupts = <3 1 0 0>;
166 reg = <0x1>;
167 + reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
168 };
169 tbi-phy@2 {
170 device_type = "tbi-phy";