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mediatek: update v4.19 switch support to latest vendor version
[openwrt/staging/rmilecki.git] / target / linux / mediatek / patches-4.19 / 0003-mt7531-gsw-internal_phy_calibration.patch
1 --- a/drivers/net/phy/mtk/mt753x/Makefile
2 +++ b/drivers/net/phy/mtk/mt753x/Makefile
3 @@ -8,4 +8,4 @@
4
5 mt753x-y += mt753x_mdio.o mt7530.o mt7531.o \
6 mt753x_common.o mt753x_vlan.o \
7 - mt753x_nl.o
8 + mt753x_nl.o mt753x_phy.o
9 --- a/drivers/net/phy/mtk/mt753x/mt7531.c
10 +++ b/drivers/net/phy/mtk/mt753x/mt7531.c
11 @@ -454,6 +454,27 @@ static void mt7531_core_pll_setup(struct gsw_mt753x *gsw)
12
13 static int mt7531_internal_phy_calibration(struct gsw_mt753x *gsw)
14 {
15 + u32 i, val;
16 + int ret;
17 +
18 + dev_info(gsw->dev,">>>>>>>>>>>>>>>>>>>>>>>>>>>>> START CALIBRATION:\n");
19 +
20 + /* gphy value from sw path */
21 + val = gsw->mmd_read(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403);
22 + val |= GBE_EFUSE_SETTING;
23 + gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val);
24 +
25 + for (i = 0; i < 5; i++) {
26 + dev_info(gsw->dev, "-------- gephy-calbration (port:%d) --------\n",
27 + i);
28 + ret = mt753x_phy_calibration(gsw, i);
29 +
30 + /* set Auto-negotiation with giga extension. */
31 + gsw->mii_write(gsw, i, 0, 0x1340);
32 + if (ret)
33 + return ret;
34 + }
35 +
36 return 0;
37 }
38
39 --- a/drivers/net/phy/mtk/mt753x/mt753x.h
40 +++ b/drivers/net/phy/mtk/mt753x/mt753x.h
41 @@ -141,6 +141,8 @@ void mt753x_mmd_ind_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
42 void mt753x_irq_worker(struct work_struct *work);
43 void mt753x_irq_enable(struct gsw_mt753x *gsw);
44
45 +int mt753x_phy_calibration(struct gsw_mt753x *gsw, u8 phyaddr);
46 +
47 /* MDIO Indirect Access Registers */
48 #define MII_MMD_ACC_CTL_REG 0x0d
49 #define MMD_CMD_S 14
50 --- /dev/null
51 +++ b/drivers/net/phy/mtk/mt753x/mt753x_phy.c
52 @@ -0,0 +1,1061 @@
53 +// SPDX-License-Identifier: GPL-2.0+
54 +/*
55 + * Common part for MediaTek MT753x gigabit switch
56 + *
57 + * Copyright (C) 2018 MediaTek Inc. All Rights Reserved.
58 + *
59 + * Author: Weijie Gao <weijie.gao@mediatek.com>
60 + */
61 +
62 +#include <linux/kernel.h>
63 +#include <linux/delay.h>
64 +
65 +#include "mt753x.h"
66 +#include "mt753x_regs.h"
67 +#include "mt753x_phy.h"
68 +
69 +u32 tc_phy_read_dev_reg(struct gsw_mt753x *gsw, u32 port_num, u32 dev_addr, u32 reg_addr)
70 +{
71 + u32 phy_val;
72 + phy_val = gsw->mmd_read(gsw, port_num, dev_addr, reg_addr);
73 +
74 + //printk("switch phy cl45 r %d 0x%x 0x%x = %x\n",port_num, dev_addr, reg_addr, phy_val);
75 + //switch_phy_read_cl45(port_num, dev_addr, reg_addr, &phy_val);
76 + return phy_val;
77 +}
78 +
79 +void tc_phy_write_dev_reg(struct gsw_mt753x *gsw, u32 port_num, u32 dev_addr, u32 reg_addr, u32 write_data)
80 +{
81 + u32 phy_val;
82 + gsw->mmd_write(gsw, port_num, dev_addr, reg_addr, write_data);
83 + phy_val = gsw->mmd_read(gsw, port_num, dev_addr, reg_addr);
84 + //printk("switch phy cl45 w %d 0x%x 0x%x 0x%x --> read back 0x%x\n",port_num, dev_addr, reg_addr, write_data, phy_val);
85 + //switch_phy_write_cl45(port_num, dev_addr, reg_addr, write_data);
86 +}
87 +
88 +void switch_phy_write(struct gsw_mt753x *gsw, u32 port_num, u32 reg_addr, u32 write_data){
89 + gsw->mii_write(gsw, port_num, reg_addr, write_data);
90 +}
91 +
92 +u32 switch_phy_read(struct gsw_mt753x *gsw, u32 port_num, u32 reg_addr){
93 + return gsw->mii_read(gsw, port_num, reg_addr);
94 +}
95 +
96 +const u8 MT753x_ZCAL_TO_R50ohm_GE_TBL_100[64] = {
97 + 127, 127, 127, 127, 127, 127, 127, 127,
98 + 127, 127, 127, 127, 127, 123, 122, 117,
99 + 115, 112, 103, 100, 98, 87, 85, 83,
100 + 81, 72, 70, 68, 66, 64, 55, 53,
101 + 52, 50, 49, 48, 38, 36, 35, 34,
102 + 33, 32, 22, 21, 20, 19, 18, 17,
103 + 16, 7, 6, 5, 4, 3, 2, 1,
104 + 0, 0, 0, 0, 0, 0, 0, 0
105 +};
106 +
107 +const u8 MT753x_TX_OFFSET_TBL[64] = {
108 + 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18,
109 + 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
110 + 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9, 0x8,
111 + 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, 0x1, 0x0,
112 + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
113 + 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
114 + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
115 + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f
116 +};
117 +
118 +u8 ge_cal_flag;
119 +
120 +u8 all_ge_ana_cal_wait(struct gsw_mt753x *gsw, u32 delay, u32 phyaddr) // for EN7512
121 +{
122 + u8 all_ana_cal_status;
123 + u32 cnt, tmp_1e_17c;
124 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017c, 0x0001); // da_calin_flag pull high
125 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001);
126 + //printk("delay = %d\n", delay);
127 +
128 + cnt = 10000;
129 + do {
130 + udelay(delay);
131 + cnt--;
132 + all_ana_cal_status = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17b) & 0x1;
133 +
134 + } while ((all_ana_cal_status == 0) && (cnt != 0));
135 +
136 +
137 + if(all_ana_cal_status == 1) {
138 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0);
139 + return all_ana_cal_status;
140 + } else {
141 + tmp_1e_17c = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17c);
142 + if ((tmp_1e_17c & 0x1) != 1) {
143 + pr_info("FIRST MDC/MDIO write error\n");
144 + pr_info("FIRST 1e_17c = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17c));
145 +
146 + }
147 + printk("re-K again\n");
148 +
149 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0);
150 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001);
151 + cnt = 10000;
152 + do {
153 + udelay(delay);
154 + cnt--;
155 + tmp_1e_17c = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17c);
156 + if ((tmp_1e_17c & 0x1) != 1) {
157 + pr_info("SECOND MDC/MDIO write error\n");
158 + pr_info("SECOND 1e_17c = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17c));
159 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001);
160 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001);
161 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001);
162 + }
163 + } while ((cnt != 0) && (tmp_1e_17c == 0));
164 +
165 + cnt = 10000;
166 + do {
167 + udelay(delay);
168 + cnt--;
169 + all_ana_cal_status = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17b) & 0x1;
170 +
171 + } while ((all_ana_cal_status == 0) && (cnt != 0));
172 +
173 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0);
174 + }
175 +
176 + if(all_ana_cal_status == 0){
177 + pr_info("!!!!!!!!!!!! dev1Eh_reg17b ERROR\n");
178 + }
179 +
180 + return all_ana_cal_status;
181 +}
182 +
183 +
184 +
185 +
186 +int ge_cal_rext(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
187 +{
188 + u8 rg_zcal_ctrl, all_ana_cal_status;
189 + u16 ad_cal_comp_out_init;
190 + u16 dev1e_e0_ana_cal_r5;
191 + int calibration_polarity;
192 + u8 cnt = 0;
193 + u16 dev1e_17a_tmp, dev1e_e0_tmp;
194 +
195 + /* *** Iext/Rext Cal start ************ */
196 + all_ana_cal_status = ANACAL_INIT;
197 + /* analog calibration enable, Rext calibration enable */
198 + /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */
199 + /* 1e_dc[0]:rg_txvos_calen */
200 + /* 1e_e1[4]:rg_cal_refsel(0:1.2V) */
201 + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00db, 0x1110)
202 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1110);
203 + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00dc, 0x0000);
204 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0);
205 + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00e1, 0x0000);
206 + //tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e1, 0x10);
207 +
208 + rg_zcal_ctrl = 0x20;/* start with 0 dB */
209 + dev1e_e0_ana_cal_r5 = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0); // get default value
210 + /* 1e_e0[5:0]:rg_zcal_ctrl */
211 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0xe0, rg_zcal_ctrl);
212 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr);/* delay 20 usec */
213 +
214 + if (all_ana_cal_status == 0) {
215 + all_ana_cal_status = ANACAL_ERROR;
216 + printk(" GE Rext AnaCal ERROR init! \r\n");
217 + return -1;
218 + }
219 + /* 1e_17a[8]:ad_cal_comp_out */
220 + ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a) >> 8) & 0x1;
221 + if (ad_cal_comp_out_init == 1)
222 + calibration_polarity = -1;
223 + else /* ad_cal_comp_out_init == 0 */
224 + calibration_polarity = 1;
225 + cnt = 0;
226 + while (all_ana_cal_status < ANACAL_ERROR) {
227 + cnt++;
228 + rg_zcal_ctrl += calibration_polarity;
229 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0xe0, (rg_zcal_ctrl));
230 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); /* delay 20 usec */
231 + dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a);
232 + if (all_ana_cal_status == 0) {
233 + all_ana_cal_status = ANACAL_ERROR;
234 + printk(" GE Rext AnaCal ERROR 2! \r\n");
235 + return -1;
236 + } else if (((dev1e_17a_tmp >> 8) & 0x1) != ad_cal_comp_out_init) {
237 + all_ana_cal_status = ANACAL_FINISH;
238 + //printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
239 + } else {
240 + dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a);
241 + dev1e_e0_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0);
242 + if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) {
243 + all_ana_cal_status = ANACAL_SATURATION; /* need to FT(IC fail?) */
244 + printk(" GE Rext AnaCal Saturation! \r\n");
245 + rg_zcal_ctrl = 0x20; /* 0 dB */
246 + }
247 + }
248 + }
249 +
250 + if (all_ana_cal_status == ANACAL_ERROR) {
251 + rg_zcal_ctrl = 0x20; /* 0 dB */
252 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
253 + } else if(all_ana_cal_status == ANACAL_FINISH){
254 + //tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
255 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, ((rg_zcal_ctrl << 8) | rg_zcal_ctrl));
256 + printk("0x1e-e0 = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x00e0));
257 + /* **** 1f_115[2:0] = rg_zcal_ctrl[5:3] // Mog review */
258 + tc_phy_write_dev_reg(gsw, PHY0, 0x1f, 0x0115, ((rg_zcal_ctrl & 0x3f) >> 3));
259 + printk("0x1f-115 = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1f, 0x115));
260 + printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
261 + ge_cal_flag = 1;
262 + } else {
263 + printk("GE Rxet cal something wrong2\n");
264 + }
265 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000);
266 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000);
267 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000);
268 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000);
269 +}
270 +
271 +//-----------------------------------------------------------------
272 +int ge_cal_r50(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
273 +{
274 + u8 rg_zcal_ctrl, all_ana_cal_status, calibration_pair;
275 + u16 ad_cal_comp_out_init;
276 + u16 dev1e_e0_ana_cal_r5;
277 + int calibration_polarity;
278 + u8 cnt = 0;
279 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
280 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000); // 1e_dc[0]:rg_txvos_calen
281 +
282 + for(calibration_pair = ANACAL_PAIR_A; calibration_pair <= ANACAL_PAIR_D; calibration_pair ++) {
283 + rg_zcal_ctrl = 0x20; // start with 0 dB
284 + dev1e_e0_ana_cal_r5 = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x00e0) & (~0x003f));
285 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl)); // 1e_e0[5:0]:rg_zcal_ctrl
286 + if(calibration_pair == ANACAL_PAIR_A)
287 + {
288 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1101); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
289 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000);
290 + //printk("R50 pair A 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc));
291 +
292 + }
293 + else if(calibration_pair == ANACAL_PAIR_B)
294 + {
295 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
296 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x1000); // 1e_dc[12]:rg_zcalen_b
297 + //printk("R50 pair B 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db),tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc));
298 +
299 + }
300 + else if(calibration_pair == ANACAL_PAIR_C)
301 + {
302 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
303 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0100); // 1e_dc[8]:rg_zcalen_c
304 + //printk("R50 pair C 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc));
305 +
306 + }
307 + else // if(calibration_pair == ANACAL_PAIR_D)
308 + {
309 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
310 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0010); // 1e_dc[4]:rg_zcalen_d
311 + //printk("R50 pair D 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc));
312 +
313 + }
314 +
315 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
316 + if(all_ana_cal_status == 0)
317 + {
318 + all_ana_cal_status = ANACAL_ERROR;
319 + printk( "GE R50 AnaCal ERROR init! \r\n");
320 + return -1;
321 + }
322 +
323 + ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1; // 1e_17a[8]:ad_cal_comp_out
324 + if(ad_cal_comp_out_init == 1)
325 + calibration_polarity = -1;
326 + else
327 + calibration_polarity = 1;
328 +
329 + cnt = 0;
330 + while(all_ana_cal_status < ANACAL_ERROR)
331 + {
332 + cnt ++;
333 + rg_zcal_ctrl += calibration_polarity;
334 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
335 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
336 +
337 + if(all_ana_cal_status == 0)
338 + {
339 + all_ana_cal_status = ANACAL_ERROR;
340 + printk( " GE R50 AnaCal ERROR 2! \r\n");
341 + return -1;
342 + }
343 + else if(((tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8)&0x1) != ad_cal_comp_out_init)
344 + {
345 + all_ana_cal_status = ANACAL_FINISH;
346 + }
347 + else {
348 + if((rg_zcal_ctrl == 0x3F)||(rg_zcal_ctrl == 0x00))
349 + {
350 + all_ana_cal_status = ANACAL_SATURATION; // need to FT
351 + printk( " GE R50 AnaCal Saturation! \r\n");
352 + }
353 + }
354 + }
355 +
356 + if(all_ana_cal_status == ANACAL_ERROR) {
357 + rg_zcal_ctrl = 0x20; // 0 dB
358 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
359 + }
360 + else {
361 + rg_zcal_ctrl = MT753x_ZCAL_TO_R50ohm_GE_TBL_100[rg_zcal_ctrl - 9]; // wait Mog zcal/r50 mapping table
362 + printk( " GE R50 AnaCal Done! (%d) (0x%x)(0x%x) \r\n", cnt, rg_zcal_ctrl, (rg_zcal_ctrl|0x80));
363 + }
364 +
365 + if(calibration_pair == ANACAL_PAIR_A) {
366 + ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174) & (~0x7f00);
367 + //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174);
368 + //printk( " GE-a 1e_174(0x%x)(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), ad_cal_comp_out_init, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
369 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0174, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<8)&0xff00) | 0x8000))); // 1e_174[15:8]
370 + //printk( " GE-a 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
371 + }
372 + else if(calibration_pair == ANACAL_PAIR_B) {
373 + ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174) & (~0x007f);
374 + //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174);
375 + //printk( " GE-b 1e_174(0x%x)(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), ad_cal_comp_out_init, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
376 +
377 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0174, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<0)&0x00ff) | 0x0080))); // 1e_174[7:0]
378 + //printk( " GE-b 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
379 + }
380 + else if(calibration_pair == ANACAL_PAIR_C) {
381 + ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175) & (~0x7f00);
382 + //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175);
383 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0175, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<8)&0xff00) | 0x8000))); // 1e_175[15:8]
384 + //printk( " GE-c 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
385 + } else {// if(calibration_pair == ANACAL_PAIR_D)
386 + ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175) & (~0x007f);
387 + //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175);
388 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0175, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<0)&0x00ff) | 0x0080))); // 1e_175[7:0]
389 + //printk( " GE-d 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
390 + }
391 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00e0, ((rg_zcal_ctrl<<8)|rg_zcal_ctrl));
392 + }
393 +
394 + printk( " GE 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
395 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000);
396 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000);
397 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000);
398 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000);
399 +}
400 +
401 +int ge_cal_tx_offset(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
402 +{
403 + u8 all_ana_cal_status, calibration_pair;
404 + u16 ad_cal_comp_out_init;
405 + int calibration_polarity, tx_offset_temp;
406 + u8 tx_offset_reg_shift, tabl_idx, i;
407 + u8 cnt = 0;
408 + u16 tx_offset_reg, reg_temp, cal_temp;
409 + //switch_phy_write(phyaddr, R0, 0x2100);//harry tmp
410 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
411 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0001); // 1e_dc[0]:rg_txvos_calen
412 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0096, 0x8000); // 1e_96[15]:bypass_tx_offset_cal, Hw bypass, Fw cal
413 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0xf808); // 1e_3e
414 + for(i = 0; i <= 4; i++)
415 + tc_phy_write_dev_reg(gsw, i, 0x1e, 0x00dd, 0x0000);
416 + for(calibration_pair = ANACAL_PAIR_A; calibration_pair <= ANACAL_PAIR_D; calibration_pair ++)
417 + {
418 + tabl_idx = 31;
419 + tx_offset_temp = MT753x_TX_OFFSET_TBL[tabl_idx];
420 +
421 + if(calibration_pair == ANACAL_PAIR_A) {
422 + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x145, 0x5010);
423 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x1000); // 1e_dd[12]:rg_txg_calen_a
424 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, (0x8000|DAC_IN_0V)); // 1e_17d:dac_in0_a
425 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, (0x8000|DAC_IN_0V)); // 1e_181:dac_in1_a
426 + //printk("tx offset pairA 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181));
427 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0172) & (~0x3f00));
428 + tx_offset_reg_shift = 8; // 1e_172[13:8]
429 + tx_offset_reg = 0x0172;
430 +
431 + //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
432 + } else if(calibration_pair == ANACAL_PAIR_B) {
433 + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x145, 0x5018);
434 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0100); // 1e_dd[8]:rg_txg_calen_b
435 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, (0x8000|DAC_IN_0V)); // 1e_17e:dac_in0_b
436 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, (0x8000|DAC_IN_0V)); // 1e_182:dac_in1_b
437 + //printk("tx offset pairB 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181));
438 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0172) & (~0x003f));
439 + tx_offset_reg_shift = 0; // 1e_172[5:0]
440 + tx_offset_reg = 0x0172;
441 + //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
442 + } else if(calibration_pair == ANACAL_PAIR_C) {
443 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0010); // 1e_dd[4]:rg_txg_calen_c
444 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, (0x8000|DAC_IN_0V)); // 1e_17f:dac_in0_c
445 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, (0x8000|DAC_IN_0V)); // 1e_183:dac_in1_c
446 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0173) & (~0x3f00));
447 + //printk("tx offset pairC 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181));
448 + tx_offset_reg_shift = 8; // 1e_173[13:8]
449 + tx_offset_reg = 0x0173;
450 + //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
451 + } else {// if(calibration_pair == ANACAL_PAIR_D)
452 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0001); // 1e_dd[0]:rg_txg_calen_d
453 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, (0x8000|DAC_IN_0V)); // 1e_180:dac_in0_d
454 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, (0x8000|DAC_IN_0V)); // 1e_184:dac_in1_d
455 + //printk("tx offset pairD 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181));
456 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0173) & (~0x003f));
457 + tx_offset_reg_shift = 0; // 1e_173[5:0]
458 + tx_offset_reg = 0x0173;
459 + //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
460 + }
461 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift))); // 1e_172, 1e_173
462 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
463 + if(all_ana_cal_status == 0) {
464 + all_ana_cal_status = ANACAL_ERROR;
465 + printk( " GE Tx offset AnaCal ERROR init! \r\n");
466 + return -1;
467 + }
468 +
469 + ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1; // 1e_17a[8]:ad_cal_comp_out
470 + if(ad_cal_comp_out_init == 1)
471 + calibration_polarity = 1;
472 + else
473 + calibration_polarity = -1;
474 +
475 + cnt = 0;
476 + //printk("TX offset cnt = %d, tabl_idx= %x, offset_val = %x\n", cnt, tabl_idx, MT753x_TX_OFFSET_TBL[tabl_idx]);
477 + while(all_ana_cal_status < ANACAL_ERROR) {
478 +
479 + cnt ++;
480 + tabl_idx += calibration_polarity;
481 + //tx_offset_temp += calibration_polarity;
482 + //cal_temp = tx_offset_temp;
483 + cal_temp = MT753x_TX_OFFSET_TBL[tabl_idx];
484 + //printk("TX offset cnt = %d, tabl_idx= %x, offset_val = %x\n", cnt, tabl_idx, MT753x_TX_OFFSET_TBL[tabl_idx]);
485 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg, (reg_temp|(cal_temp<<tx_offset_reg_shift)));
486 +
487 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
488 + if(all_ana_cal_status == 0) {
489 + all_ana_cal_status = ANACAL_ERROR;
490 + printk( " GE Tx offset AnaCal ERROR init 2! \r\n");
491 + return -1;
492 + } else if(((tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8)&0x1) != ad_cal_comp_out_init) {
493 + all_ana_cal_status = ANACAL_FINISH;
494 + } else {
495 + if((tabl_idx == 0)||(tabl_idx == 0x3f)) {
496 + all_ana_cal_status = ANACAL_SATURATION; // need to FT
497 + printk( " GE Tx offset AnaCal Saturation! \r\n");
498 + }
499 + }
500 + }
501 +
502 + if(all_ana_cal_status == ANACAL_ERROR) {
503 + tx_offset_temp = TX_AMP_OFFSET_0MV;
504 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
505 + } else {
506 + printk( " GE Tx offset AnaCal Done! (pair-%d)(%d)(0x%x) 0x1e_%x=0x%x\n", calibration_pair, cnt, MT753x_TX_OFFSET_TBL[tabl_idx], tx_offset_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg));
507 + }
508 + }
509 +
510 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, 0x0000);
511 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, 0x0000);
512 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, 0x0000);
513 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, 0x0000);
514 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, 0x0000);
515 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, 0x0000);
516 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, 0x0000);
517 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, 0x0000);
518 +
519 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000); // disable analog calibration circuit
520 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000); // disable Tx offset calibration circuit
521 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000); // disable analog calibration circuit
522 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000); // disable Tx offset calibration circuit
523 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0x0000); // disable Tx VLD force mode
524 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0000); // disable Tx offset/amplitude calibration circuit
525 +}
526 +
527 +int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
528 +{
529 + u8 all_ana_cal_status, calibration_pair, i;
530 + u16 ad_cal_comp_out_init;
531 + int calibration_polarity;
532 + u32 tx_amp_reg_shift;
533 + u16 reg_temp;
534 + u32 tx_amp_temp, tx_amp_reg, cnt=0, tx_amp_reg_100;
535 + u32 debug_tmp, reg_backup, reg_tmp;
536 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
537 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0001); // 1e_dc[0]:rg_txvos_calen
538 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e1, 0x0010); // 1e_e1[4]:select 1V
539 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0xf808); // 1e_3e:enable Tx VLD
540 +
541 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x11, 0xff00);
542 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27a, 0x33);
543 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0xc9, 0xffff);
544 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x300, 0x4);
545 + for(i = 0; i <= 4; i++)
546 + tc_phy_write_dev_reg(gsw, i, 0x1e, 0x00dd, 0x0000);
547 + for(calibration_pair = ANACAL_PAIR_A; calibration_pair <= ANACAL_PAIR_D; calibration_pair ++) {
548 + tx_amp_temp = 0x20; // start with 0 dB
549 +
550 + if(calibration_pair == ANACAL_PAIR_A) {
551 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x1000); // 1e_dd[12]:tx_a amp calibration enable
552 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, (0x8000|DAC_IN_2V)); // 1e_17d:dac_in0_a
553 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, (0x8000|DAC_IN_2V)); // 1e_181:dac_in1_a
554 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x012) & (~0xfc00));
555 + tx_amp_reg_shift = 10; // 1e_12[15:10]
556 + tx_amp_reg = 0x12;
557 + tx_amp_reg_100 = 0x16;
558 + } else if(calibration_pair == ANACAL_PAIR_B) {
559 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0100); // 1e_dd[8]:tx_b amp calibration enable
560 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, (0x8000|DAC_IN_2V)); // 1e_17e:dac_in0_b
561 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, (0x8000|DAC_IN_2V)); // 1e_182:dac_in1_b
562 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x017) & (~0x3f00));
563 + tx_amp_reg_shift = 8; // 1e_17[13:8]
564 + tx_amp_reg = 0x17;
565 + tx_amp_reg_100 = 0x18;
566 + } else if(calibration_pair == ANACAL_PAIR_C) {
567 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0010); // 1e_dd[4]:tx_c amp calibration enable
568 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, (0x8000|DAC_IN_2V)); // 1e_17f:dac_in0_c
569 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, (0x8000|DAC_IN_2V)); // 1e_183:dac_in1_c
570 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x019) & (~0x3f00));
571 + tx_amp_reg_shift = 8; // 1e_19[13:8]
572 + tx_amp_reg = 0x19;
573 + tx_amp_reg_100 = 0x20;
574 + } else { //if(calibration_pair == ANACAL_PAIR_D)
575 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0001); // 1e_dd[0]:tx_d amp calibration enable
576 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, (0x8000|DAC_IN_2V)); // 1e_180:dac_in0_d
577 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, (0x8000|DAC_IN_2V)); // 1e_184:dac_in1_d
578 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x021) & (~0x3f00));
579 + tx_amp_reg_shift = 8; // 1e_21[13:8]
580 + tx_amp_reg = 0x21;
581 + tx_amp_reg_100 = 0x22;
582 + }
583 + tc_phy_write_dev_reg( gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|(tx_amp_temp<<tx_amp_reg_shift))); // 1e_12, 1e_17, 1e_19, 1e_21
584 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100, (tx_amp_temp|(tx_amp_temp<<tx_amp_reg_shift)));
585 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
586 + if(all_ana_cal_status == 0) {
587 + all_ana_cal_status = ANACAL_ERROR;
588 + printk( " GE Tx amp AnaCal ERROR init init! \r\n");
589 + return -1;
590 + }
591 +
592 + ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1; // 1e_17a[8]:ad_cal_comp_out
593 + if(ad_cal_comp_out_init == 1)
594 + calibration_polarity = -1;
595 + else
596 + calibration_polarity = 1;
597 +
598 + cnt =0;
599 + while(all_ana_cal_status < ANACAL_ERROR) {
600 + cnt ++;
601 + tx_amp_temp += calibration_polarity;
602 + //printk("tx_amp : %x, 1e %x = %x\n", tx_amp_temp, tx_amp_reg, (reg_temp|(tx_amp_temp<<tx_amp_reg_shift)));
603 + tc_phy_write_dev_reg( gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|(tx_amp_temp<<tx_amp_reg_shift)));
604 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100, (tx_amp_temp|(tx_amp_temp<<tx_amp_reg_shift)));
605 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
606 + if(all_ana_cal_status == 0) {
607 + all_ana_cal_status = ANACAL_ERROR;
608 + printk( " GE Tx amp AnaCal ERROR 2! \r\n");
609 + return -1;
610 + } else if(((tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8)&0x1) != ad_cal_comp_out_init) {
611 + //printk("TX AMP ANACAL_FINISH\n");
612 + all_ana_cal_status = ANACAL_FINISH;
613 + if (phyaddr == 0) {
614 + if (calibration_pair == ANACAL_PAIR_A)
615 + tx_amp_temp = tx_amp_temp - 2;
616 + else if(calibration_pair == ANACAL_PAIR_B)
617 + tx_amp_temp = tx_amp_temp - 1;
618 + else if(calibration_pair == ANACAL_PAIR_C)
619 + tx_amp_temp = tx_amp_temp - 2;
620 + else if(calibration_pair == ANACAL_PAIR_D)
621 + tx_amp_temp = tx_amp_temp - 1;
622 + } else if (phyaddr == 1) {
623 + if (calibration_pair == ANACAL_PAIR_A)
624 + tx_amp_temp = tx_amp_temp - 1;
625 + else if(calibration_pair == ANACAL_PAIR_B)
626 + tx_amp_temp = tx_amp_temp ;
627 + else if(calibration_pair == ANACAL_PAIR_C)
628 + tx_amp_temp = tx_amp_temp - 1;
629 + else if(calibration_pair == ANACAL_PAIR_D)
630 + tx_amp_temp = tx_amp_temp - 1;
631 + } else if (phyaddr == 2) {
632 + if (calibration_pair == ANACAL_PAIR_A)
633 + tx_amp_temp = tx_amp_temp;
634 + else if(calibration_pair == ANACAL_PAIR_B)
635 + tx_amp_temp = tx_amp_temp - 1;
636 + else if(calibration_pair == ANACAL_PAIR_C)
637 + tx_amp_temp = tx_amp_temp;
638 + else if(calibration_pair == ANACAL_PAIR_D)
639 + tx_amp_temp = tx_amp_temp - 1;
640 + } else if (phyaddr == 3) {
641 + tx_amp_temp = tx_amp_temp;
642 + } else if (phyaddr == 4) {
643 + if (calibration_pair == ANACAL_PAIR_A)
644 + tx_amp_temp = tx_amp_temp;
645 + else if(calibration_pair == ANACAL_PAIR_B)
646 + tx_amp_temp = tx_amp_temp - 1;
647 + else if(calibration_pair == ANACAL_PAIR_C)
648 + tx_amp_temp = tx_amp_temp;
649 + else if(calibration_pair == ANACAL_PAIR_D)
650 + tx_amp_temp = tx_amp_temp;
651 + }
652 + reg_temp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)&(~0xff00);
653 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
654 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
655 + if (phyaddr == 0) {
656 + if ((tx_amp_reg == 0x12) || (tx_amp_reg == 0x17)) {
657 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
658 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 7));
659 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
660 + }
661 + if (tx_amp_reg_100 == 0x16) {
662 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
663 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp+1+4)<<tx_amp_reg_shift)));
664 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
665 + }
666 + if (tx_amp_reg_100 == 0x18) {
667 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
668 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp+4)<<tx_amp_reg_shift)));
669 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
670 + }
671 + } else if (phyaddr == 1) {
672 + if (tx_amp_reg == 0x12) {
673 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
674 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 9));
675 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
676 + }
677 + if (tx_amp_reg == 0x17){
678 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
679 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 7));
680 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
681 + }
682 + if (tx_amp_reg_100 == 0x16) {
683 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
684 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp+4)<<tx_amp_reg_shift)));
685 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
686 + }
687 + if (tx_amp_reg_100 == 0x18) {
688 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
689 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-1+4)<<tx_amp_reg_shift)));
690 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
691 + }
692 + } else if (phyaddr == 2) {
693 + if ((tx_amp_reg == 0x12) || (tx_amp_reg == 0x17)) {
694 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
695 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 6));
696 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
697 + }
698 + if ((tx_amp_reg_100 == 0x16) || (tx_amp_reg_100 == 0x18)) {
699 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
700 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-1+4)<<tx_amp_reg_shift)));
701 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
702 + }
703 + } else if (phyaddr == 3) {
704 + if (tx_amp_reg == 0x12) {
705 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
706 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 4));
707 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
708 + }
709 + if (tx_amp_reg == 0x17) {
710 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
711 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 7));
712 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
713 + }
714 + if (tx_amp_reg_100 == 0x16) {
715 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
716 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-2+4)<<tx_amp_reg_shift)));
717 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
718 + }
719 + if (tx_amp_reg_100 == 0x18) {
720 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
721 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-1+3)<<tx_amp_reg_shift)));
722 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
723 + }
724 + } else if (phyaddr == 4) {
725 + if ((tx_amp_reg == 0x12) || (tx_amp_reg == 0x17)) {
726 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
727 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 5));
728 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
729 + }
730 + if (tx_amp_reg_100 == 0x16) {
731 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
732 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-2+4)<<tx_amp_reg_shift)));
733 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
734 + }
735 + if (tx_amp_reg_100 == 0x18) {
736 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
737 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-1+4)<<tx_amp_reg_shift)));
738 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
739 + }
740 + }
741 +
742 + if (calibration_pair == ANACAL_PAIR_A){
743 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
744 + reg_tmp = ((reg_backup & 0xfc00) >> 10);
745 + reg_tmp -= 8;
746 + reg_backup = 0x0000;
747 + reg_backup |= ((reg_tmp << 10) | (reg_tmp << 0));
748 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x12, reg_backup);
749 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
750 + //printk("PORT[%d] 1e.012 = %x (OFFSET_1000M_PAIR_A)\n", phyaddr, reg_backup);
751 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
752 + reg_tmp = ((reg_backup & 0x3f) >> 0);
753 + reg_tmp -= 8;
754 + reg_backup = (reg_backup & (~0x3f));
755 + reg_backup |= (reg_tmp << 0);
756 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x16, reg_backup);
757 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
758 + //printk("PORT[%d] 1e.016 = %x (OFFSET_TESTMODE_1000M_PAIR_A)\n", phyaddr, reg_backup);
759 + }
760 + else if(calibration_pair == ANACAL_PAIR_B){
761 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
762 + reg_tmp = ((reg_backup & 0x3f00) >> 8);
763 + reg_tmp -= 8;
764 + reg_backup = 0x0000;
765 + reg_backup |= ((reg_tmp << 8) | (reg_tmp << 0));
766 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x17, reg_backup);
767 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
768 + //printk("PORT[%d] 1e.017 = %x (OFFSET_1000M_PAIR_B)\n", phyaddr, reg_backup);
769 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
770 + reg_tmp = ((reg_backup & 0x3f) >> 0);
771 + reg_tmp -= 8;
772 + reg_backup = (reg_backup & (~0x3f));
773 + reg_backup |= (reg_tmp << 0);
774 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18, reg_backup);
775 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
776 + //printk("PORT[%d] 1e.018 = %x (OFFSET_TESTMODE_1000M_PAIR_B)\n", phyaddr, reg_backup);
777 + }
778 + else if(calibration_pair == ANACAL_PAIR_C){
779 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
780 + reg_tmp = ((reg_backup & 0x3f00) >> 8);
781 + reg_tmp -= 8;
782 + reg_backup = (reg_backup & (~0x3f00));
783 + reg_backup |= (reg_tmp << 8);
784 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x19, reg_backup);
785 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
786 + //printk("PORT[%d] 1e.019 = %x (OFFSET_1000M_PAIR_C)\n", phyaddr, reg_backup);
787 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
788 + reg_tmp = ((reg_backup & 0x3f) >> 0);
789 + reg_tmp -= 8;
790 + reg_backup = (reg_backup & (~0x3f));
791 + reg_backup |= (reg_tmp << 0);
792 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x20, reg_backup);
793 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
794 + //printk("PORT[%d] 1e.020 = %x (OFFSET_TESTMODE_1000M_PAIR_C)\n", phyaddr, reg_backup);
795 + }
796 + else if(calibration_pair == ANACAL_PAIR_D){
797 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
798 + reg_tmp = ((reg_backup & 0x3f00) >> 8);
799 + reg_tmp -= 8;
800 + reg_backup = (reg_backup & (~0x3f00));
801 + reg_backup |= (reg_tmp << 8);
802 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x21, reg_backup);
803 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
804 + //printk("PORT[%d] 1e.021 = %x (OFFSET_1000M_PAIR_D)\n", phyaddr, reg_backup);
805 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
806 + reg_tmp = ((reg_backup & 0x3f) >> 0);
807 + reg_tmp -= 8;
808 + reg_backup = (reg_backup & (~0x3f));
809 + reg_backup |= (reg_tmp << 0);
810 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x22, reg_backup);
811 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
812 + //printk("PORT[%d] 1e.022 = %x (OFFSET_TESTMODE_1000M_PAIR_D)\n", phyaddr, reg_backup);
813 + }
814 +
815 + if (calibration_pair == ANACAL_PAIR_A){
816 + //printk("PORT (%d) TX_AMP PAIR (A) FINAL CALIBRATION RESULT\n", phyaddr);
817 + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
818 + //printk("1e.012 = 0x%x\n", debug_tmp);
819 + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
820 + //printk("1e.016 = 0x%x\n", debug_tmp);
821 + }
822 +
823 + else if(calibration_pair == ANACAL_PAIR_B){
824 + //printk("PORT (%d) TX_AMP PAIR (A) FINAL CALIBRATION RESULT\n", phyaddr);
825 + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
826 + //printk("1e.017 = 0x%x\n", debug_tmp);
827 + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
828 + //printk("1e.018 = 0x%x\n", debug_tmp);
829 + }
830 + else if(calibration_pair == ANACAL_PAIR_C){
831 + //printk("PORT (%d) TX_AMP PAIR (A) FINAL CALIBRATION RESULT\n", phyaddr);
832 + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
833 + //printk("1e.019 = 0x%x\n", debug_tmp);
834 + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
835 + //printk("1e.020 = 0x%x\n", debug_tmp);
836 + }
837 + else if(calibration_pair == ANACAL_PAIR_D){
838 + //printk("PORT (%d) TX_AMP PAIR (A) FINAL CALIBRATION RESULT\n", phyaddr);
839 + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
840 + //printk("1e.021 = 0x%x\n", debug_tmp);
841 + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
842 + //printk("1e.022 = 0x%x\n", debug_tmp);
843 + }
844 +
845 +
846 + printk( " GE Tx amp AnaCal Done! (pair-%d)(1e_%x = 0x%x)\n", calibration_pair, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
847 +
848 + } else {
849 + if((tx_amp_temp == 0x3f)||(tx_amp_temp == 0x00)) {
850 + all_ana_cal_status = ANACAL_SATURATION; // need to FT
851 + printk( " GE Tx amp AnaCal Saturation! \r\n");
852 + }
853 + }
854 + }
855 +
856 + if(all_ana_cal_status == ANACAL_ERROR) {
857 + tx_amp_temp = 0x20;
858 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, (reg_temp|(tx_amp_temp<<tx_amp_reg_shift)));
859 + }
860 + }
861 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, 0x0000);
862 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, 0x0000);
863 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, 0x0000);
864 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, 0x0000);
865 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, 0x0000);
866 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, 0x0000);
867 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, 0x0000);
868 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, 0x0000);
869 +
870 + /* disable analog calibration circuit */
871 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000);
872 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000); // disable Tx offset calibration circuit
873 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000); // disable analog calibration circuit
874 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000); // disable Tx offset calibration circuit
875 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0x0000); // disable Tx VLD force mode
876 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0000); // disable Tx offset/amplitude calibration circuit
877 +
878 +
879 +
880 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x273, 0x2000);
881 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0xc9, 0x0fff);
882 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x145, 0x1000);
883 +
884 +}
885 +
886 +//-----------------------------------------------------------------
887 +
888 +int phy_calibration(struct gsw_mt753x *gsw, u8 phyaddr)
889 +{
890 + u32 reg_tmp,reg_tmp0, reg_tmp1, i;
891 + u32 CALDLY = 40;
892 + int ret;
893 + /* set [12]AN disable, [8]full duplex, [13/6]1000Mbps */
894 + //tc_phy_write_dev_reg(phyaddr, 0x0, 0x0140);
895 + switch_phy_write(gsw, phyaddr, R0, 0x140);
896 +
897 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x145, 0x1010);/* fix mdi */
898 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, RG_185, 0);/* disable tx slew control */
899 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x100, 0xc000);/* BG voltage output */
900 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x403, 0x1099); //bypass efuse
901 +
902 +#if (1)
903 + // 1f_27c[12:8] cr_da_tx_i2mpb_10m Trimming TX bias setup(@10M)
904 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27c, 0x1f1f);
905 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27c, 0x3300);
906 +
907 + reg_tmp1 = tc_phy_read_dev_reg(gsw, PHY0, 0x1f, 0x27c);
908 + //dev1Fh_reg273h TXVLD DA register - Adjust voltage mode TX amplitude.
909 + //tc_phy_write_dev_reg(phyaddr, 0x1f, 0x273, 0);
910 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x273, 0x1000);
911 + //reg_tmp1 = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x273);
912 + //printk("reg_tmp1273 = %x\n", reg_tmp1);
913 + /*1e_11 TX overshoot Enable (PAIR A/B/C/D) in gbe mode*/
914 +
915 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x11);
916 + reg_tmp = reg_tmp | (0xf << 12);
917 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x11, reg_tmp);
918 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e1, 0x10);
919 + /* calibration start ============ */
920 + printk("CALDLY = %d\n", CALDLY);
921 + if(ge_cal_flag == 0){
922 + ret = ge_cal_rext(gsw, 0, CALDLY);
923 + if (ret == -1){
924 + printk("ge_cal_rext error K port =%d\n", phyaddr);
925 + return ret;
926 + }
927 + ge_cal_flag = 1;
928 + }
929 +
930 + /* *** R50 Cal start ***************************** */
931 + /*phyaddress = 0*/
932 + ret = ge_cal_r50(gsw, phyaddr, CALDLY);
933 + if (ret == -1){
934 + printk("R50 error K port =%d\n", phyaddr);
935 + return ret;
936 + }
937 + /* *** R50 Cal end *** */
938 + /* *** Tx offset Cal start *********************** */
939 + ret = ge_cal_tx_offset(gsw, phyaddr, CALDLY);
940 + if (ret == -1){
941 + printk("ge_cal_tx_offset error K port =%d\n", phyaddr);
942 + return ret;
943 + }
944 + /* *** Tx offset Cal end *** */
945 +
946 + /* *** Tx Amp Cal start *** */
947 + ret = ge_cal_tx_amp(gsw, phyaddr, CALDLY);
948 + if (ret == -1){
949 + printk("ge_cal_tx_amp error K port =%d\n", phyaddr);
950 + return ret;
951 + }
952 + /* *** Tx Amp Cal end *** */
953 + /*tmp maybe changed*/
954 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27c, 0x1111);
955 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27b, 0x47);
956 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x273, 0x2000);
957 +
958 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3a8, 0x0810);
959 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3aa, 0x0008);
960 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3ab, 0x0810);
961 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3ad, 0x0008);
962 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3ae, 0x0106);
963 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3b0, 0x0001);
964 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3b1, 0x0106);
965 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3b3, 0x0001);
966 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18c, 0x0001);
967 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18d, 0x0001);
968 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18e, 0x0001);
969 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18f, 0x0001);
970 +
971 + /*da_tx_bias1_b_tx_standby = 5'b10 (dev1eh_reg3aah[12:8])*/
972 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x3aa);
973 + reg_tmp = reg_tmp & ~(0x1f00);
974 + reg_tmp = reg_tmp | 0x2 << 8;
975 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3aa, reg_tmp);
976 +
977 + /*da_tx_bias1_a_tx_standby = 5'b10 (dev1eh_reg3a9h[4:0])*/
978 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x3a9);
979 + reg_tmp = reg_tmp & ~(0x1f);
980 + reg_tmp = reg_tmp | 0x2;
981 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3a9, reg_tmp);
982 +#endif
983 +}
984 +
985 +void rx_dc_offset(struct gsw_mt753x *gsw, u8 phyaddr)
986 +{
987 + u32 reg_tmp1;
988 +
989 + pr_info("PORT %d RX_DC_OFFSET\n", phyaddr);
990 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x96, 0x8000);
991 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x37, 0x3);
992 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x107, 0x4000);
993 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x171, 0x1e5);
994 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x39, 0x200f);
995 + udelay(40);
996 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x39, 0x000f);
997 + udelay(40);
998 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x171, 0x65);
999 +}
1000 +
1001 +void check_rx_dc_offset_pair_a(struct gsw_mt753x *gsw, u8 phyaddr)
1002 +{
1003 + u32 reg_tmp;
1004 + u8 reg_val;
1005 +
1006 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x114f);
1007 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
1008 + reg_tmp = reg_tmp & 0xff;
1009 + pr_info("before pairA output = %x\n", reg_tmp);
1010 + udelay(40);
1011 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1142);
1012 + udelay(40);
1013 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
1014 + reg_tmp = reg_tmp & 0xff;
1015 + pr_info("after pairA output = %x\n", reg_tmp);
1016 + if ((reg_tmp & 0x80) != 0)
1017 + reg_tmp = (~reg_tmp) + 1;
1018 + if ((reg_tmp & 0xff) >4)
1019 + pr_info("pairA RX_DC_OFFSET error");
1020 +}
1021 +
1022 +void check_rx_dc_offset_pair_b(struct gsw_mt753x *gsw, u8 phyaddr)
1023 +{
1024 + u32 reg_tmp;
1025 + u8 reg_val;
1026 +
1027 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1151);
1028 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
1029 + reg_tmp = reg_tmp & 0xff;
1030 + pr_info("before pairB output = %x\n", reg_tmp);
1031 + udelay(40);
1032 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1143);
1033 + udelay(40);
1034 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
1035 + reg_tmp = reg_tmp & 0xff;
1036 + pr_info("after pairB output = %x\n", reg_tmp);
1037 + if ((reg_tmp & 0x80) != 0)
1038 + reg_tmp = (~reg_tmp) + 1;
1039 + if ((reg_tmp & 0xff) >4)
1040 + pr_info("pairB RX_DC_OFFSET error");
1041 +}
1042 +
1043 +void check_rx_dc_offset_pair_c(struct gsw_mt753x *gsw, u8 phyaddr)
1044 +{
1045 + u32 reg_tmp;
1046 + u8 reg_val;
1047 +
1048 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1153);
1049 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
1050 + reg_tmp = reg_tmp & 0xff;
1051 + pr_info("before pairC output = %x\n", reg_tmp);
1052 + udelay(40);
1053 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1144);
1054 + udelay(40);
1055 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
1056 + reg_tmp = reg_tmp & 0xff;
1057 + pr_info("after pairC output = %x\n", reg_tmp);
1058 + if ((reg_tmp & 0x80) != 0)
1059 + reg_tmp = (~reg_tmp) + 1;
1060 + if ((reg_tmp & 0xff) >4)
1061 + pr_info("pairC RX_DC_OFFSET error");
1062 +}
1063 +
1064 +void check_rx_dc_offset_pair_d(struct gsw_mt753x *gsw, u8 phyaddr)
1065 +{
1066 + u32 reg_tmp;
1067 + u8 reg_val;
1068 +
1069 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1155);
1070 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
1071 + reg_tmp = reg_tmp & 0xff;
1072 + pr_info("before pairD output = %x\n", reg_tmp);
1073 + udelay(40);
1074 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1145);
1075 + udelay(40);
1076 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
1077 + reg_tmp = reg_tmp & 0xff;
1078 + pr_info("after pairD output = %x\n", reg_tmp);
1079 + if ((reg_tmp & 0x80) != 0)
1080 + reg_tmp = (~reg_tmp) + 1;
1081 + if ((reg_tmp & 0xff) >4)
1082 + pr_info("pairD RX_DC_OFFSET error");
1083 +}
1084 +
1085 +
1086 +int mt753x_phy_calibration(struct gsw_mt753x *gsw, u8 phyaddr){
1087 +
1088 + int ret;
1089 +
1090 + phy_calibration(gsw, phyaddr);
1091 +
1092 + /*eye pic*/
1093 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0, 0x187);
1094 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x1, 0x1c9);
1095 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x2, 0x1c6);
1096 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3, 0x182);
1097 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x4, 0x208);
1098 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x5, 0x205);
1099 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x6, 0x384);
1100 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x7, 0x3cb);
1101 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x8, 0x3c4);
1102 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x9, 0x30a);
1103 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0xa, 0x00b);
1104 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0xb, 0x002);
1105 +
1106 + rx_dc_offset(gsw, phyaddr);
1107 + check_rx_dc_offset_pair_a(gsw, phyaddr);
1108 + check_rx_dc_offset_pair_b(gsw, phyaddr);
1109 + check_rx_dc_offset_pair_c(gsw, phyaddr);
1110 + check_rx_dc_offset_pair_d(gsw, phyaddr);
1111 +
1112 + return ret;
1113 +}
1114 diff --git a/target/linux/generic/files/drivers/net/phy/mtk/mt753x/mt753x_phy.h b/target/linux/generic/files/drivers/net/phy/mtk/mt753x/mt753x_phy.h
1115 new file mode 100755
1116 --- /dev/null
1117 +++ b/drivers/net/phy/mtk/mt753x/mt753x_phy.h
1118 @@ -0,0 +1,145 @@
1119 +/* SPDX-License-Identifier: GPL-2.0+ */
1120 +/*
1121 + * Register definitions for MediaTek MT753x Gigabit switches
1122 + *
1123 + * Copyright (C) 2018 MediaTek Inc. All Rights Reserved.
1124 + *
1125 + * Author: Weijie Gao <weijie.gao@mediatek.com>
1126 + */
1127 +
1128 +#ifndef _MT753X_PHY_H_
1129 +#define _MT753X_PHY_H_
1130 +
1131 +#include <linux/bitops.h>
1132 +
1133 +/*phy calibration use*/
1134 +#define DEV_1E 0x1E
1135 +/*global device 0x1f, always set P0*/
1136 +#define DEV_1F 0x1F
1137 +
1138 +
1139 +/************IEXT/REXT CAL***************/
1140 +/* bits range: for example BITS(16,23) = 0xFF0000*/
1141 +#define BITS(m, n) (~(BIT(m) - 1) & ((BIT(n) - 1) | BIT(n)))
1142 +#define ANACAL_INIT 0x01
1143 +#define ANACAL_ERROR 0xFD
1144 +#define ANACAL_SATURATION 0xFE
1145 +#define ANACAL_FINISH 0xFF
1146 +#define ANACAL_PAIR_A 0
1147 +#define ANACAL_PAIR_B 1
1148 +#define ANACAL_PAIR_C 2
1149 +#define ANACAL_PAIR_D 3
1150 +#define DAC_IN_0V 0x00
1151 +#define DAC_IN_2V 0xf0
1152 +#define TX_AMP_OFFSET_0MV 0x20
1153 +#define TX_AMP_OFFSET_VALID_BITS 6
1154 +
1155 +#define R0 0
1156 +#define PHY0 0
1157 +#define PHY1 1
1158 +#define PHY2 2
1159 +#define PHY3 3
1160 +#define PHY4 4
1161 +#define ANA_TEST_MODE BITS(8, 15)
1162 +#define TST_TCLK_SEL BITs(6, 7)
1163 +#define ANA_TEST_VGA_RG 0x100
1164 +
1165 +#define FORCE_MDI_CROSS_OVER BITS(3, 4)
1166 +#define T10_TEST_CTL_RG 0x145
1167 +#define RG_185 0x185
1168 +#define RG_TX_SLEW BIT(0)
1169 +#define ANA_CAL_0 0xdb
1170 +#define RG_CAL_CKINV BIT(12)
1171 +#define RG_ANA_CALEN BIT(8)
1172 +#define RG_REXT_CALEN BIT(4)
1173 +#define RG_ZCALEN_A BIT(0)
1174 +#define ANA_CAL_1 0xdc
1175 +#define RG_ZCALEN_B BIT(12)
1176 +#define RG_ZCALEN_C BIT(8)
1177 +#define RG_ZCALEN_D BIT(4)
1178 +#define RG_TXVOS_CALEN BIT(0)
1179 +#define ANA_CAL_6 0xe1
1180 +#define RG_CAL_REFSEL BIT(4)
1181 +#define RG_CAL_COMP_PWD BIT(0)
1182 +#define ANA_CAL_5 0xe0
1183 +#define RG_REXT_TRIM BITs(8, 13)
1184 +#define RG_ZCAL_CTRL BITs(0, 5)
1185 +#define RG_17A 0x17a
1186 +#define AD_CAL_COMP_OUT BIT(8)
1187 +#define RG_17B 0x17b
1188 +#define AD_CAL_CLK bit(0)
1189 +#define RG_17C 0x17c
1190 +#define DA_CALIN_FLAG bit(0)
1191 +/************R50 CAL****************************/
1192 +#define RG_174 0x174
1193 +#define RG_R50OHM_RSEL_TX_A_EN BIT[15]
1194 +#define CR_R50OHM_RSEL_TX_A BITS[8:14]
1195 +#define RG_R50OHM_RSEL_TX_B_EN BIT[7]
1196 +#define CR_R50OHM_RSEL_TX_B BITS[6:0]
1197 +#define RG_175 0x175
1198 +#define RG_R50OHM_RSEL_TX_C_EN BITS[15]
1199 +#define CR_R50OHM_RSEL_TX_C BITS[8:14]
1200 +#define RG_R50OHM_RSEL_TX_D_EN BIT[7]
1201 +#define CR_R50OHM_RSEL_TX_D BITS[0:6]
1202 +/**********TX offset Calibration***************************/
1203 +#define RG_95 0x96
1204 +#define BYPASS_TX_OFFSET_CAL BIT(15)
1205 +#define RG_3E 0x3e
1206 +#define BYPASS_PD_TXVLD_A BIT(15)
1207 +#define BYPASS_PD_TXVLD_B BIT(14)
1208 +#define BYPASS_PD_TXVLD_C BIT(13)
1209 +#define BYPASS_PD_TXVLD_D BIT(12)
1210 +#define BYPASS_PD_TX_10M BIT(11)
1211 +#define POWER_DOWN_TXVLD_A BIT(7)
1212 +#define POWER_DOWN_TXVLD_B BIT(6)
1213 +#define POWER_DOWN_TXVLD_C BIT(5)
1214 +#define POWER_DOWN_TXVLD_D BIT(4)
1215 +#define POWER_DOWN_TX_10M BIT(3)
1216 +#define RG_DD 0xdd
1217 +#define RG_TXG_CALEN_A BIT(12)
1218 +#define RG_TXG_CALEN_B BIT(8)
1219 +#define RG_TXG_CALEN_C BIT(4)
1220 +#define RG_TXG_CALEN_D BIT(0)
1221 +#define RG_17D 0x17D
1222 +#define FORCE_DASN_DAC_IN0_A BIT(15)
1223 +#define DASN_DAC_IN0_A BITS(0, 9)
1224 +#define RG_17E 0x17E
1225 +#define FORCE_DASN_DAC_IN0_B BIT(15)
1226 +#define DASN_DAC_IN0_B BITS(0, 9)
1227 +#define RG_17F 0x17F
1228 +
1229 +#define FORCE_DASN_DAC_IN0_C BIT(15)
1230 +#define DASN_DAC_IN0_C BITS(0, 9)
1231 +#define RG_180 0x180
1232 +#define FORCE_DASN_DAC_IN0_D BIT(15)
1233 +#define DASN_DAC_IN0_D BITS(0, 9)
1234 +
1235 +#define RG_181 0x181
1236 +#define FORCE_DASN_DAC_IN1_A BIT(15)
1237 +#define DASN_DAC_IN1_A BITS(0, 9)
1238 +#define RG_182 0x182
1239 +#define FORCE_DASN_DAC_IN1_B BIT(15)
1240 +#define DASN_DAC_IN1_B BITS(0, 9)
1241 +#define RG_183 0x183
1242 +#define FORCE_DASN_DAC_IN1_C BIT15]
1243 +#define DASN_DAC_IN1_C BITS(0, 9)
1244 +#define RG_184 0x184
1245 +#define FORCE_DASN_DAC_IN1_D BIT(15)
1246 +#define DASN_DAC_IN1_D BITS(0, 9)
1247 +#define RG_172 0x172
1248 +#define CR_TX_AMP_OFFSET_A BITS(8, 13)
1249 +#define CR_TX_AMP_OFFSET_B BITS(0, 5)
1250 +#define RG_173 0x173
1251 +#define CR_TX_AMP_OFFSET_C BITS(8, 13)
1252 +#define CR_TX_AMP_OFFSET_D BITS(0, 5)
1253 +/**********TX Amp Calibration ***************************/
1254 +#define RG_12 0x12
1255 +#define DA_TX_I2MPB_A_GBE BITS(10, 15)
1256 +#define RG_17 0x17
1257 +#define DA_TX_I2MPB_B_GBE BITS(8, 13)
1258 +#define RG_19 0x19
1259 +#define DA_TX_I2MPB_C_GBE BITS(8, 13)
1260 +#define RG_21 0x21
1261 +#define DA_TX_I2MPB_D_GBE BITS(8, 13)
1262 +
1263 +#endif /* _MT753X_REGS_H_ */
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