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[openwrt/staging/rmilecki.git] / target / linux / mediatek / patches-4.14 / 0181-ASoC-mediatek-rework-clock-functions-for-MT2701.patch
1 From d038da516563d910dd39930777f431d4c65a56cd Mon Sep 17 00:00:00 2001
2 From: Ryder Lee <ryder.lee@mediatek.com>
3 Date: Tue, 2 Jan 2018 19:47:19 +0800
4 Subject: [PATCH 181/224] ASoC: mediatek: rework clock functions for MT2701
5
6 Reworks clock part to make it more reasonable. The current changes are:
7
8 - Replace regmap operations by CCF APIs. Doing so, we just need to handle
9 the element clocks and can also get accurate information via CCF.
10
11 - Rename clocks to make them more generic so that the future revisions
12 of the IP can adapt gracefully.
13
14 - Regroup 'aud_clks[]' by usage - the basic needs and I2S parts:
15
16 The new code just keep the common clocks in array and let SoC self decide
17 I2S numbers - If future chips have different sets of channels we will
18 add a little more abstract here.
19
20 Moreover, this patch moves I2S clocks to the struct mt2701_i2s_data
21 so that we can easily manage them when calls .prepare() and .shutdown().
22
23 Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
24 Tested-by: Garlic Tseng <garlic.tseng@mediatek.com>
25 Signed-off-by: Mark Brown <broonie@kernel.org>
26 ---
27 sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c | 518 +++++++---------------
28 sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h | 15 +-
29 sound/soc/mediatek/mt2701/mt2701-afe-common.h | 64 +--
30 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c | 45 +-
31 4 files changed, 200 insertions(+), 442 deletions(-)
32
33 --- a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
34 +++ b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
35 @@ -21,442 +21,256 @@
36 #include "mt2701-afe-common.h"
37 #include "mt2701-afe-clock-ctrl.h"
38
39 -static const char *aud_clks[MT2701_CLOCK_NUM] = {
40 - [MT2701_AUD_INFRA_SYS_AUDIO] = "infra_sys_audio_clk",
41 - [MT2701_AUD_AUD_MUX1_SEL] = "top_audio_mux1_sel",
42 - [MT2701_AUD_AUD_MUX2_SEL] = "top_audio_mux2_sel",
43 - [MT2701_AUD_AUD_MUX1_DIV] = "top_audio_mux1_div",
44 - [MT2701_AUD_AUD_MUX2_DIV] = "top_audio_mux2_div",
45 - [MT2701_AUD_AUD_48K_TIMING] = "top_audio_48k_timing",
46 - [MT2701_AUD_AUD_44K_TIMING] = "top_audio_44k_timing",
47 - [MT2701_AUD_AUDPLL_MUX_SEL] = "top_audpll_mux_sel",
48 - [MT2701_AUD_APLL_SEL] = "top_apll_sel",
49 - [MT2701_AUD_AUD1PLL_98M] = "top_aud1_pll_98M",
50 - [MT2701_AUD_AUD2PLL_90M] = "top_aud2_pll_90M",
51 - [MT2701_AUD_HADDS2PLL_98M] = "top_hadds2_pll_98M",
52 - [MT2701_AUD_HADDS2PLL_294M] = "top_hadds2_pll_294M",
53 - [MT2701_AUD_AUDPLL] = "top_audpll",
54 - [MT2701_AUD_AUDPLL_D4] = "top_audpll_d4",
55 - [MT2701_AUD_AUDPLL_D8] = "top_audpll_d8",
56 - [MT2701_AUD_AUDPLL_D16] = "top_audpll_d16",
57 - [MT2701_AUD_AUDPLL_D24] = "top_audpll_d24",
58 - [MT2701_AUD_AUDINTBUS] = "top_audintbus_sel",
59 - [MT2701_AUD_CLK_26M] = "clk_26m",
60 - [MT2701_AUD_SYSPLL1_D4] = "top_syspll1_d4",
61 - [MT2701_AUD_AUD_K1_SRC_SEL] = "top_aud_k1_src_sel",
62 - [MT2701_AUD_AUD_K2_SRC_SEL] = "top_aud_k2_src_sel",
63 - [MT2701_AUD_AUD_K3_SRC_SEL] = "top_aud_k3_src_sel",
64 - [MT2701_AUD_AUD_K4_SRC_SEL] = "top_aud_k4_src_sel",
65 - [MT2701_AUD_AUD_K5_SRC_SEL] = "top_aud_k5_src_sel",
66 - [MT2701_AUD_AUD_K6_SRC_SEL] = "top_aud_k6_src_sel",
67 - [MT2701_AUD_AUD_K1_SRC_DIV] = "top_aud_k1_src_div",
68 - [MT2701_AUD_AUD_K2_SRC_DIV] = "top_aud_k2_src_div",
69 - [MT2701_AUD_AUD_K3_SRC_DIV] = "top_aud_k3_src_div",
70 - [MT2701_AUD_AUD_K4_SRC_DIV] = "top_aud_k4_src_div",
71 - [MT2701_AUD_AUD_K5_SRC_DIV] = "top_aud_k5_src_div",
72 - [MT2701_AUD_AUD_K6_SRC_DIV] = "top_aud_k6_src_div",
73 - [MT2701_AUD_AUD_I2S1_MCLK] = "top_aud_i2s1_mclk",
74 - [MT2701_AUD_AUD_I2S2_MCLK] = "top_aud_i2s2_mclk",
75 - [MT2701_AUD_AUD_I2S3_MCLK] = "top_aud_i2s3_mclk",
76 - [MT2701_AUD_AUD_I2S4_MCLK] = "top_aud_i2s4_mclk",
77 - [MT2701_AUD_AUD_I2S5_MCLK] = "top_aud_i2s5_mclk",
78 - [MT2701_AUD_AUD_I2S6_MCLK] = "top_aud_i2s6_mclk",
79 - [MT2701_AUD_ASM_M_SEL] = "top_asm_m_sel",
80 - [MT2701_AUD_ASM_H_SEL] = "top_asm_h_sel",
81 - [MT2701_AUD_UNIVPLL2_D4] = "top_univpll2_d4",
82 - [MT2701_AUD_UNIVPLL2_D2] = "top_univpll2_d2",
83 - [MT2701_AUD_SYSPLL_D5] = "top_syspll_d5",
84 +static const char *const base_clks[] = {
85 + [MT2701_TOP_AUD_MCLK_SRC0] = "top_audio_mux1_sel",
86 + [MT2701_TOP_AUD_MCLK_SRC1] = "top_audio_mux2_sel",
87 + [MT2701_AUDSYS_AFE] = "audio_afe_pd",
88 + [MT2701_AUDSYS_AFE_CONN] = "audio_afe_conn_pd",
89 + [MT2701_AUDSYS_A1SYS] = "audio_a1sys_pd",
90 + [MT2701_AUDSYS_A2SYS] = "audio_a2sys_pd",
91 };
92
93 int mt2701_init_clock(struct mtk_base_afe *afe)
94 {
95 struct mt2701_afe_private *afe_priv = afe->platform_priv;
96 - int i = 0;
97 + int i;
98
99 - for (i = 0; i < MT2701_CLOCK_NUM; i++) {
100 - afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
101 - if (IS_ERR(afe_priv->clocks[i])) {
102 - dev_warn(afe->dev, "%s devm_clk_get %s fail\n",
103 - __func__, aud_clks[i]);
104 - return PTR_ERR(aud_clks[i]);
105 + for (i = 0; i < MT2701_BASE_CLK_NUM; i++) {
106 + afe_priv->base_ck[i] = devm_clk_get(afe->dev, base_clks[i]);
107 + if (IS_ERR(afe_priv->base_ck[i])) {
108 + dev_err(afe->dev, "failed to get %s\n", base_clks[i]);
109 + return PTR_ERR(afe_priv->base_ck[i]);
110 }
111 }
112
113 - return 0;
114 -}
115 + /* Get I2S related clocks */
116 + for (i = 0; i < MT2701_I2S_NUM; i++) {
117 + struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i];
118 + char name[13];
119 +
120 + snprintf(name, sizeof(name), "i2s%d_src_sel", i);
121 + i2s_path->sel_ck = devm_clk_get(afe->dev, name);
122 + if (IS_ERR(i2s_path->sel_ck)) {
123 + dev_err(afe->dev, "failed to get %s\n", name);
124 + return PTR_ERR(i2s_path->sel_ck);
125 + }
126
127 -int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
128 -{
129 - int ret = 0;
130 + snprintf(name, sizeof(name), "i2s%d_src_div", i);
131 + i2s_path->div_ck = devm_clk_get(afe->dev, name);
132 + if (IS_ERR(i2s_path->div_ck)) {
133 + dev_err(afe->dev, "failed to get %s\n", name);
134 + return PTR_ERR(i2s_path->div_ck);
135 + }
136
137 - ret = mt2701_turn_on_a1sys_clock(afe);
138 - if (ret) {
139 - dev_err(afe->dev, "%s turn_on_a1sys_clock fail %d\n",
140 - __func__, ret);
141 - return ret;
142 - }
143 + snprintf(name, sizeof(name), "i2s%d_mclk_en", i);
144 + i2s_path->mclk_ck = devm_clk_get(afe->dev, name);
145 + if (IS_ERR(i2s_path->mclk_ck)) {
146 + dev_err(afe->dev, "failed to get %s\n", name);
147 + return PTR_ERR(i2s_path->mclk_ck);
148 + }
149
150 - ret = mt2701_turn_on_a2sys_clock(afe);
151 - if (ret) {
152 - dev_err(afe->dev, "%s turn_on_a2sys_clock fail %d\n",
153 - __func__, ret);
154 - mt2701_turn_off_a1sys_clock(afe);
155 - return ret;
156 - }
157 + snprintf(name, sizeof(name), "i2so%d_hop_ck", i);
158 + i2s_path->hop_ck[I2S_OUT] = devm_clk_get(afe->dev, name);
159 + if (IS_ERR(i2s_path->hop_ck[I2S_OUT])) {
160 + dev_err(afe->dev, "failed to get %s\n", name);
161 + return PTR_ERR(i2s_path->hop_ck[I2S_OUT]);
162 + }
163
164 - ret = mt2701_turn_on_afe_clock(afe);
165 - if (ret) {
166 - dev_err(afe->dev, "%s turn_on_afe_clock fail %d\n",
167 - __func__, ret);
168 - mt2701_turn_off_a1sys_clock(afe);
169 - mt2701_turn_off_a2sys_clock(afe);
170 - return ret;
171 + snprintf(name, sizeof(name), "i2si%d_hop_ck", i);
172 + i2s_path->hop_ck[I2S_IN] = devm_clk_get(afe->dev, name);
173 + if (IS_ERR(i2s_path->hop_ck[I2S_IN])) {
174 + dev_err(afe->dev, "failed to get %s\n", name);
175 + return PTR_ERR(i2s_path->hop_ck[I2S_IN]);
176 + }
177 +
178 + snprintf(name, sizeof(name), "asrc%d_out_ck", i);
179 + i2s_path->asrco_ck = devm_clk_get(afe->dev, name);
180 + if (IS_ERR(i2s_path->asrco_ck)) {
181 + dev_err(afe->dev, "failed to get %s\n", name);
182 + return PTR_ERR(i2s_path->asrco_ck);
183 + }
184 }
185
186 - regmap_update_bits(afe->regmap, ASYS_TOP_CON,
187 - AUDIO_TOP_CON0_A1SYS_A2SYS_ON,
188 - AUDIO_TOP_CON0_A1SYS_A2SYS_ON);
189 - regmap_update_bits(afe->regmap, AFE_DAC_CON0,
190 - AFE_DAC_CON0_AFE_ON,
191 - AFE_DAC_CON0_AFE_ON);
192 - regmap_write(afe->regmap, PWR2_TOP_CON,
193 - PWR2_TOP_CON_INIT_VAL);
194 - regmap_write(afe->regmap, PWR1_ASM_CON1,
195 - PWR1_ASM_CON1_INIT_VAL);
196 - regmap_write(afe->regmap, PWR2_ASM_CON1,
197 - PWR2_ASM_CON1_INIT_VAL);
198 + /* Some platforms may support BT path */
199 + afe_priv->mrgif_ck = devm_clk_get(afe->dev, "audio_mrgif_pd");
200 + if (IS_ERR(afe_priv->mrgif_ck)) {
201 + if (PTR_ERR(afe_priv->mrgif_ck) == -EPROBE_DEFER)
202 + return -EPROBE_DEFER;
203
204 - return 0;
205 -}
206 + afe_priv->mrgif_ck = NULL;
207 + }
208
209 -void mt2701_afe_disable_clock(struct mtk_base_afe *afe)
210 -{
211 - mt2701_turn_off_afe_clock(afe);
212 - mt2701_turn_off_a1sys_clock(afe);
213 - mt2701_turn_off_a2sys_clock(afe);
214 - regmap_update_bits(afe->regmap, ASYS_TOP_CON,
215 - AUDIO_TOP_CON0_A1SYS_A2SYS_ON, 0);
216 - regmap_update_bits(afe->regmap, AFE_DAC_CON0,
217 - AFE_DAC_CON0_AFE_ON, 0);
218 + return 0;
219 }
220
221 -int mt2701_turn_on_a1sys_clock(struct mtk_base_afe *afe)
222 +int mt2701_afe_enable_i2s(struct mtk_base_afe *afe, int id, int dir)
223 {
224 struct mt2701_afe_private *afe_priv = afe->platform_priv;
225 - int ret = 0;
226 + struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
227 + int ret;
228
229 - /* Set Mux */
230 - ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
231 + ret = clk_prepare_enable(i2s_path->asrco_ck);
232 if (ret) {
233 - dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
234 - __func__, aud_clks[MT2701_AUD_AUD_MUX1_SEL], ret);
235 - goto A1SYS_CLK_AUD_MUX1_SEL_ERR;
236 + dev_err(afe->dev, "failed to enable ASRC clock %d\n", ret);
237 + return ret;
238 }
239
240 - ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL],
241 - afe_priv->clocks[MT2701_AUD_AUD1PLL_98M]);
242 + ret = clk_prepare_enable(i2s_path->hop_ck[dir]);
243 if (ret) {
244 - dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
245 - aud_clks[MT2701_AUD_AUD_MUX1_SEL],
246 - aud_clks[MT2701_AUD_AUD1PLL_98M], ret);
247 - goto A1SYS_CLK_AUD_MUX1_SEL_ERR;
248 + dev_err(afe->dev, "failed to enable I2S clock %d\n", ret);
249 + goto err_hop_ck;
250 }
251
252 - /* Set Divider */
253 - ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
254 - if (ret) {
255 - dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
256 - __func__,
257 - aud_clks[MT2701_AUD_AUD_MUX1_DIV],
258 - ret);
259 - goto A1SYS_CLK_AUD_MUX1_DIV_ERR;
260 - }
261 + return 0;
262
263 - ret = clk_set_rate(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV],
264 - MT2701_AUD_AUD_MUX1_DIV_RATE);
265 - if (ret) {
266 - dev_err(afe->dev, "%s clk_set_parent %s-%d fail %d\n", __func__,
267 - aud_clks[MT2701_AUD_AUD_MUX1_DIV],
268 - MT2701_AUD_AUD_MUX1_DIV_RATE, ret);
269 - goto A1SYS_CLK_AUD_MUX1_DIV_ERR;
270 - }
271 +err_hop_ck:
272 + clk_disable_unprepare(i2s_path->asrco_ck);
273
274 - /* Enable clock gate */
275 - ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]);
276 - if (ret) {
277 - dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
278 - __func__, aud_clks[MT2701_AUD_AUD_48K_TIMING], ret);
279 - goto A1SYS_CLK_AUD_48K_ERR;
280 - }
281 + return ret;
282 +}
283
284 - /* Enable infra audio */
285 - ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
286 - if (ret) {
287 - dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
288 - __func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret);
289 - goto A1SYS_CLK_INFRA_ERR;
290 - }
291 +void mt2701_afe_disable_i2s(struct mtk_base_afe *afe, int id, int dir)
292 +{
293 + struct mt2701_afe_private *afe_priv = afe->platform_priv;
294 + struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
295
296 - return 0;
297 + clk_disable_unprepare(i2s_path->hop_ck[dir]);
298 + clk_disable_unprepare(i2s_path->asrco_ck);
299 +}
300
301 -A1SYS_CLK_INFRA_ERR:
302 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
303 -A1SYS_CLK_AUD_48K_ERR:
304 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]);
305 -A1SYS_CLK_AUD_MUX1_DIV_ERR:
306 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
307 -A1SYS_CLK_AUD_MUX1_SEL_ERR:
308 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
309 +int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id)
310 +{
311 + struct mt2701_afe_private *afe_priv = afe->platform_priv;
312 + struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
313
314 - return ret;
315 + return clk_prepare_enable(i2s_path->mclk_ck);
316 }
317
318 -void mt2701_turn_off_a1sys_clock(struct mtk_base_afe *afe)
319 +void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id)
320 {
321 struct mt2701_afe_private *afe_priv = afe->platform_priv;
322 + struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
323
324 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
325 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]);
326 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
327 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
328 + clk_disable_unprepare(i2s_path->mclk_ck);
329 }
330
331 -int mt2701_turn_on_a2sys_clock(struct mtk_base_afe *afe)
332 +int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe)
333 {
334 struct mt2701_afe_private *afe_priv = afe->platform_priv;
335 - int ret = 0;
336
337 - /* Set Mux */
338 - ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
339 - if (ret) {
340 - dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
341 - __func__, aud_clks[MT2701_AUD_AUD_MUX2_SEL], ret);
342 - goto A2SYS_CLK_AUD_MUX2_SEL_ERR;
343 - }
344 + return clk_prepare_enable(afe_priv->mrgif_ck);
345 +}
346
347 - ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL],
348 - afe_priv->clocks[MT2701_AUD_AUD2PLL_90M]);
349 - if (ret) {
350 - dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
351 - aud_clks[MT2701_AUD_AUD_MUX2_SEL],
352 - aud_clks[MT2701_AUD_AUD2PLL_90M], ret);
353 - goto A2SYS_CLK_AUD_MUX2_SEL_ERR;
354 - }
355 +void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe)
356 +{
357 + struct mt2701_afe_private *afe_priv = afe->platform_priv;
358
359 - /* Set Divider */
360 - ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]);
361 - if (ret) {
362 - dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
363 - __func__, aud_clks[MT2701_AUD_AUD_MUX2_DIV], ret);
364 - goto A2SYS_CLK_AUD_MUX2_DIV_ERR;
365 - }
366 + clk_disable_unprepare(afe_priv->mrgif_ck);
367 +}
368
369 - ret = clk_set_rate(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV],
370 - MT2701_AUD_AUD_MUX2_DIV_RATE);
371 - if (ret) {
372 - dev_err(afe->dev, "%s clk_set_parent %s-%d fail %d\n", __func__,
373 - aud_clks[MT2701_AUD_AUD_MUX2_DIV],
374 - MT2701_AUD_AUD_MUX2_DIV_RATE, ret);
375 - goto A2SYS_CLK_AUD_MUX2_DIV_ERR;
376 - }
377 +static int mt2701_afe_enable_audsys(struct mtk_base_afe *afe)
378 +{
379 + struct mt2701_afe_private *afe_priv = afe->platform_priv;
380 + int ret;
381
382 - /* Enable clock gate */
383 - ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]);
384 - if (ret) {
385 - dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
386 - __func__, aud_clks[MT2701_AUD_AUD_44K_TIMING], ret);
387 - goto A2SYS_CLK_AUD_44K_ERR;
388 - }
389 + ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
390 + if (ret)
391 + return ret;
392
393 - /* Enable infra audio */
394 - ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
395 - if (ret) {
396 - dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
397 - __func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret);
398 - goto A2SYS_CLK_INFRA_ERR;
399 - }
400 + ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
401 + if (ret)
402 + goto err_audio_a1sys;
403 +
404 + ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
405 + if (ret)
406 + goto err_audio_a2sys;
407 +
408 + ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
409 + if (ret)
410 + goto err_afe_conn;
411
412 return 0;
413
414 -A2SYS_CLK_INFRA_ERR:
415 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
416 -A2SYS_CLK_AUD_44K_ERR:
417 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]);
418 -A2SYS_CLK_AUD_MUX2_DIV_ERR:
419 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]);
420 -A2SYS_CLK_AUD_MUX2_SEL_ERR:
421 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
422 +err_afe_conn:
423 + clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
424 +err_audio_a2sys:
425 + clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
426 +err_audio_a1sys:
427 + clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
428
429 return ret;
430 }
431
432 -void mt2701_turn_off_a2sys_clock(struct mtk_base_afe *afe)
433 +static void mt2701_afe_disable_audsys(struct mtk_base_afe *afe)
434 {
435 struct mt2701_afe_private *afe_priv = afe->platform_priv;
436
437 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
438 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]);
439 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]);
440 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
441 + clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
442 + clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
443 + clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
444 + clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
445 }
446
447 -int mt2701_turn_on_afe_clock(struct mtk_base_afe *afe)
448 +int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
449 {
450 - struct mt2701_afe_private *afe_priv = afe->platform_priv;
451 int ret;
452
453 - /* enable INFRA_SYS */
454 - ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
455 + /* Enable audio system */
456 + ret = mt2701_afe_enable_audsys(afe);
457 if (ret) {
458 - dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
459 - __func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret);
460 - goto AFE_AUD_INFRA_ERR;
461 - }
462 -
463 - /* Set MT2701_AUD_AUDINTBUS to MT2701_AUD_SYSPLL1_D4 */
464 - ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
465 - if (ret) {
466 - dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
467 - __func__, aud_clks[MT2701_AUD_AUDINTBUS], ret);
468 - goto AFE_AUD_AUDINTBUS_ERR;
469 - }
470 -
471 - ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUDINTBUS],
472 - afe_priv->clocks[MT2701_AUD_SYSPLL1_D4]);
473 - if (ret) {
474 - dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
475 - aud_clks[MT2701_AUD_AUDINTBUS],
476 - aud_clks[MT2701_AUD_SYSPLL1_D4], ret);
477 - goto AFE_AUD_AUDINTBUS_ERR;
478 - }
479 -
480 - /* Set MT2701_AUD_ASM_H_SEL to MT2701_AUD_UNIVPLL2_D2 */
481 - ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
482 - if (ret) {
483 - dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
484 - __func__, aud_clks[MT2701_AUD_ASM_H_SEL], ret);
485 - goto AFE_AUD_ASM_H_ERR;
486 - }
487 -
488 - ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_ASM_H_SEL],
489 - afe_priv->clocks[MT2701_AUD_UNIVPLL2_D2]);
490 - if (ret) {
491 - dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
492 - aud_clks[MT2701_AUD_ASM_H_SEL],
493 - aud_clks[MT2701_AUD_UNIVPLL2_D2], ret);
494 - goto AFE_AUD_ASM_H_ERR;
495 - }
496 -
497 - /* Set MT2701_AUD_ASM_M_SEL to MT2701_AUD_UNIVPLL2_D4 */
498 - ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
499 - if (ret) {
500 - dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
501 - __func__, aud_clks[MT2701_AUD_ASM_M_SEL], ret);
502 - goto AFE_AUD_ASM_M_ERR;
503 + dev_err(afe->dev, "failed to enable audio system %d\n", ret);
504 + return ret;
505 }
506
507 - ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_ASM_M_SEL],
508 - afe_priv->clocks[MT2701_AUD_UNIVPLL2_D4]);
509 - if (ret) {
510 - dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
511 - aud_clks[MT2701_AUD_ASM_M_SEL],
512 - aud_clks[MT2701_AUD_UNIVPLL2_D4], ret);
513 - goto AFE_AUD_ASM_M_ERR;
514 - }
515 + regmap_update_bits(afe->regmap, ASYS_TOP_CON,
516 + AUDIO_TOP_CON0_A1SYS_A2SYS_ON,
517 + AUDIO_TOP_CON0_A1SYS_A2SYS_ON);
518 + regmap_update_bits(afe->regmap, AFE_DAC_CON0,
519 + AFE_DAC_CON0_AFE_ON,
520 + AFE_DAC_CON0_AFE_ON);
521
522 - regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
523 - AUDIO_TOP_CON0_PDN_AFE, 0);
524 - regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
525 - AUDIO_TOP_CON0_PDN_APLL_CK, 0);
526 - regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
527 - AUDIO_TOP_CON4_PDN_A1SYS, 0);
528 - regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
529 - AUDIO_TOP_CON4_PDN_A2SYS, 0);
530 - regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
531 - AUDIO_TOP_CON4_PDN_AFE_CONN, 0);
532 + /* Configure ASRC */
533 + regmap_write(afe->regmap, PWR1_ASM_CON1, PWR1_ASM_CON1_INIT_VAL);
534 + regmap_write(afe->regmap, PWR2_ASM_CON1, PWR2_ASM_CON1_INIT_VAL);
535
536 return 0;
537 -
538 -AFE_AUD_ASM_M_ERR:
539 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
540 -AFE_AUD_ASM_H_ERR:
541 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
542 -AFE_AUD_AUDINTBUS_ERR:
543 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
544 -AFE_AUD_INFRA_ERR:
545 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
546 -
547 - return ret;
548 }
549
550 -void mt2701_turn_off_afe_clock(struct mtk_base_afe *afe)
551 +int mt2701_afe_disable_clock(struct mtk_base_afe *afe)
552 {
553 - struct mt2701_afe_private *afe_priv = afe->platform_priv;
554 + regmap_update_bits(afe->regmap, ASYS_TOP_CON,
555 + AUDIO_TOP_CON0_A1SYS_A2SYS_ON, 0);
556 + regmap_update_bits(afe->regmap, AFE_DAC_CON0,
557 + AFE_DAC_CON0_AFE_ON, 0);
558
559 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
560 + mt2701_afe_disable_audsys(afe);
561
562 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
563 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
564 - clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
565 -
566 - regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
567 - AUDIO_TOP_CON0_PDN_AFE, AUDIO_TOP_CON0_PDN_AFE);
568 - regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
569 - AUDIO_TOP_CON0_PDN_APLL_CK,
570 - AUDIO_TOP_CON0_PDN_APLL_CK);
571 - regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
572 - AUDIO_TOP_CON4_PDN_A1SYS,
573 - AUDIO_TOP_CON4_PDN_A1SYS);
574 - regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
575 - AUDIO_TOP_CON4_PDN_A2SYS,
576 - AUDIO_TOP_CON4_PDN_A2SYS);
577 - regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
578 - AUDIO_TOP_CON4_PDN_AFE_CONN,
579 - AUDIO_TOP_CON4_PDN_AFE_CONN);
580 + return 0;
581 }
582
583 void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain,
584 int mclk)
585 {
586 - struct mt2701_afe_private *afe_priv = afe->platform_priv;
587 + struct mt2701_afe_private *priv = afe->platform_priv;
588 + struct mt2701_i2s_path *i2s_path = &priv->i2s_path[id];
589 int ret;
590 - int aud_src_div_id = MT2701_AUD_AUD_K1_SRC_DIV + id;
591 - int aud_src_clk_id = MT2701_AUD_AUD_K1_SRC_SEL + id;
592
593 - /* Set MCLK Kx_SRC_SEL(domain) */
594 - ret = clk_prepare_enable(afe_priv->clocks[aud_src_clk_id]);
595 - if (ret)
596 - dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
597 - __func__, aud_clks[aud_src_clk_id], ret);
598 -
599 - if (domain == 0) {
600 - ret = clk_set_parent(afe_priv->clocks[aud_src_clk_id],
601 - afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
602 - if (ret)
603 - dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
604 - __func__, aud_clks[aud_src_clk_id],
605 - aud_clks[MT2701_AUD_AUD_MUX1_SEL], ret);
606 - } else {
607 - ret = clk_set_parent(afe_priv->clocks[aud_src_clk_id],
608 - afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
609 - if (ret)
610 - dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
611 - __func__, aud_clks[aud_src_clk_id],
612 - aud_clks[MT2701_AUD_AUD_MUX2_SEL], ret);
613 - }
614 - clk_disable_unprepare(afe_priv->clocks[aud_src_clk_id]);
615 + /* Set mclk source */
616 + if (domain == 0)
617 + ret = clk_set_parent(i2s_path->sel_ck,
618 + priv->base_ck[MT2701_TOP_AUD_MCLK_SRC0]);
619 + else
620 + ret = clk_set_parent(i2s_path->sel_ck,
621 + priv->base_ck[MT2701_TOP_AUD_MCLK_SRC1]);
622
623 - /* Set MCLK Kx_SRC_DIV(divider) */
624 - ret = clk_prepare_enable(afe_priv->clocks[aud_src_div_id]);
625 if (ret)
626 - dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
627 - __func__, aud_clks[aud_src_div_id], ret);
628 + dev_err(afe->dev, "failed to set domain%d mclk source %d\n",
629 + domain, ret);
630
631 - ret = clk_set_rate(afe_priv->clocks[aud_src_div_id], mclk);
632 + /* Set mclk divider */
633 + ret = clk_set_rate(i2s_path->div_ck, mclk);
634 if (ret)
635 - dev_err(afe->dev, "%s clk_set_rate %s-%d fail %d\n", __func__,
636 - aud_clks[aud_src_div_id], mclk, ret);
637 - clk_disable_unprepare(afe_priv->clocks[aud_src_div_id]);
638 + dev_err(afe->dev, "failed to set mclk divider %d\n", ret);
639 }
640
641 MODULE_DESCRIPTION("MT2701 afe clock control");
642 --- a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h
643 +++ b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h
644 @@ -21,16 +21,15 @@ struct mtk_base_afe;
645
646 int mt2701_init_clock(struct mtk_base_afe *afe);
647 int mt2701_afe_enable_clock(struct mtk_base_afe *afe);
648 -void mt2701_afe_disable_clock(struct mtk_base_afe *afe);
649 +int mt2701_afe_disable_clock(struct mtk_base_afe *afe);
650
651 -int mt2701_turn_on_a1sys_clock(struct mtk_base_afe *afe);
652 -void mt2701_turn_off_a1sys_clock(struct mtk_base_afe *afe);
653 +int mt2701_afe_enable_i2s(struct mtk_base_afe *afe, int id, int dir);
654 +void mt2701_afe_disable_i2s(struct mtk_base_afe *afe, int id, int dir);
655 +int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id);
656 +void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id);
657
658 -int mt2701_turn_on_a2sys_clock(struct mtk_base_afe *afe);
659 -void mt2701_turn_off_a2sys_clock(struct mtk_base_afe *afe);
660 -
661 -int mt2701_turn_on_afe_clock(struct mtk_base_afe *afe);
662 -void mt2701_turn_off_afe_clock(struct mtk_base_afe *afe);
663 +int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe);
664 +void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe);
665
666 void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain,
667 int mclk);
668 --- a/sound/soc/mediatek/mt2701/mt2701-afe-common.h
669 +++ b/sound/soc/mediatek/mt2701/mt2701-afe-common.h
670 @@ -69,53 +69,14 @@ enum {
671 MT2701_IRQ_ASYS_END,
672 };
673
674 -/* 2701 clock def */
675 -enum audio_system_clock_type {
676 - MT2701_AUD_INFRA_SYS_AUDIO,
677 - MT2701_AUD_AUD_MUX1_SEL,
678 - MT2701_AUD_AUD_MUX2_SEL,
679 - MT2701_AUD_AUD_MUX1_DIV,
680 - MT2701_AUD_AUD_MUX2_DIV,
681 - MT2701_AUD_AUD_48K_TIMING,
682 - MT2701_AUD_AUD_44K_TIMING,
683 - MT2701_AUD_AUDPLL_MUX_SEL,
684 - MT2701_AUD_APLL_SEL,
685 - MT2701_AUD_AUD1PLL_98M,
686 - MT2701_AUD_AUD2PLL_90M,
687 - MT2701_AUD_HADDS2PLL_98M,
688 - MT2701_AUD_HADDS2PLL_294M,
689 - MT2701_AUD_AUDPLL,
690 - MT2701_AUD_AUDPLL_D4,
691 - MT2701_AUD_AUDPLL_D8,
692 - MT2701_AUD_AUDPLL_D16,
693 - MT2701_AUD_AUDPLL_D24,
694 - MT2701_AUD_AUDINTBUS,
695 - MT2701_AUD_CLK_26M,
696 - MT2701_AUD_SYSPLL1_D4,
697 - MT2701_AUD_AUD_K1_SRC_SEL,
698 - MT2701_AUD_AUD_K2_SRC_SEL,
699 - MT2701_AUD_AUD_K3_SRC_SEL,
700 - MT2701_AUD_AUD_K4_SRC_SEL,
701 - MT2701_AUD_AUD_K5_SRC_SEL,
702 - MT2701_AUD_AUD_K6_SRC_SEL,
703 - MT2701_AUD_AUD_K1_SRC_DIV,
704 - MT2701_AUD_AUD_K2_SRC_DIV,
705 - MT2701_AUD_AUD_K3_SRC_DIV,
706 - MT2701_AUD_AUD_K4_SRC_DIV,
707 - MT2701_AUD_AUD_K5_SRC_DIV,
708 - MT2701_AUD_AUD_K6_SRC_DIV,
709 - MT2701_AUD_AUD_I2S1_MCLK,
710 - MT2701_AUD_AUD_I2S2_MCLK,
711 - MT2701_AUD_AUD_I2S3_MCLK,
712 - MT2701_AUD_AUD_I2S4_MCLK,
713 - MT2701_AUD_AUD_I2S5_MCLK,
714 - MT2701_AUD_AUD_I2S6_MCLK,
715 - MT2701_AUD_ASM_M_SEL,
716 - MT2701_AUD_ASM_H_SEL,
717 - MT2701_AUD_UNIVPLL2_D4,
718 - MT2701_AUD_UNIVPLL2_D2,
719 - MT2701_AUD_SYSPLL_D5,
720 - MT2701_CLOCK_NUM
721 +enum audio_base_clock {
722 + MT2701_TOP_AUD_MCLK_SRC0,
723 + MT2701_TOP_AUD_MCLK_SRC1,
724 + MT2701_AUDSYS_AFE,
725 + MT2701_AUDSYS_AFE_CONN,
726 + MT2701_AUDSYS_A1SYS,
727 + MT2701_AUDSYS_A2SYS,
728 + MT2701_BASE_CLK_NUM,
729 };
730
731 static const unsigned int mt2701_afe_backup_list[] = {
732 @@ -144,7 +105,6 @@ struct mtk_base_irq_data;
733
734 struct mt2701_i2s_data {
735 int i2s_ctrl_reg;
736 - int i2s_pwn_shift;
737 int i2s_asrc_fs_shift;
738 int i2s_asrc_fs_mask;
739 };
740 @@ -161,11 +121,17 @@ struct mt2701_i2s_path {
741 int on[I2S_DIR_NUM];
742 int occupied[I2S_DIR_NUM];
743 const struct mt2701_i2s_data *i2s_data[2];
744 + struct clk *hop_ck[I2S_DIR_NUM];
745 + struct clk *sel_ck;
746 + struct clk *div_ck;
747 + struct clk *mclk_ck;
748 + struct clk *asrco_ck;
749 };
750
751 struct mt2701_afe_private {
752 - struct clk *clocks[MT2701_CLOCK_NUM];
753 struct mt2701_i2s_path i2s_path[MT2701_I2S_NUM];
754 + struct clk *base_ck[MT2701_BASE_CLK_NUM];
755 + struct clk *mrgif_ck;
756 bool mrg_enable[MT2701_STREAM_DIR_NUM];
757 };
758
759 --- a/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
760 +++ b/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
761 @@ -97,21 +97,12 @@ static int mt2701_afe_i2s_startup(struct
762 {
763 struct snd_soc_pcm_runtime *rtd = substream->private_data;
764 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
765 - struct mt2701_afe_private *afe_priv = afe->platform_priv;
766 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
767 - int clk_num = MT2701_AUD_AUD_I2S1_MCLK + i2s_num;
768 - int ret = 0;
769
770 if (i2s_num < 0)
771 return i2s_num;
772
773 - /* enable mclk */
774 - ret = clk_prepare_enable(afe_priv->clocks[clk_num]);
775 - if (ret)
776 - dev_err(afe->dev, "Failed to enable mclk for I2S: %d\n",
777 - i2s_num);
778 -
779 - return ret;
780 + return mt2701_afe_enable_mclk(afe, i2s_num);
781 }
782
783 static int mt2701_afe_i2s_path_shutdown(struct snd_pcm_substream *substream,
784 @@ -151,9 +142,9 @@ static int mt2701_afe_i2s_path_shutdown(
785 /* disable i2s */
786 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
787 ASYS_I2S_CON_I2S_EN, 0);
788 - regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
789 - 1 << i2s_data->i2s_pwn_shift,
790 - 1 << i2s_data->i2s_pwn_shift);
791 +
792 + mt2701_afe_disable_i2s(afe, i2s_num, stream_dir);
793 +
794 return 0;
795 }
796
797 @@ -165,7 +156,6 @@ static void mt2701_afe_i2s_shutdown(stru
798 struct mt2701_afe_private *afe_priv = afe->platform_priv;
799 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
800 struct mt2701_i2s_path *i2s_path;
801 - int clk_num = MT2701_AUD_AUD_I2S1_MCLK + i2s_num;
802
803 if (i2s_num < 0)
804 return;
805 @@ -185,7 +175,7 @@ static void mt2701_afe_i2s_shutdown(stru
806
807 I2S_UNSTART:
808 /* disable mclk */
809 - clk_disable_unprepare(afe_priv->clocks[clk_num]);
810 + mt2701_afe_disable_mclk(afe, i2s_num);
811 }
812
813 static int mt2701_i2s_path_prepare_enable(struct snd_pcm_substream *substream,
814 @@ -251,9 +241,7 @@ static int mt2701_i2s_path_prepare_enabl
815 fs << i2s_data->i2s_asrc_fs_shift);
816
817 /* enable i2s */
818 - regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
819 - 1 << i2s_data->i2s_pwn_shift,
820 - 0 << i2s_data->i2s_pwn_shift);
821 + mt2701_afe_enable_i2s(afe, i2s_num, stream_dir);
822
823 /* reset i2s hw status before enable */
824 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
825 @@ -339,9 +327,11 @@ static int mt2701_btmrg_startup(struct s
826 struct snd_soc_pcm_runtime *rtd = substream->private_data;
827 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
828 struct mt2701_afe_private *afe_priv = afe->platform_priv;
829 + int ret;
830
831 - regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
832 - AUDIO_TOP_CON4_PDN_MRGIF, 0);
833 + ret = mt2701_enable_btmrg_clk(afe);
834 + if (ret)
835 + return ret;
836
837 afe_priv->mrg_enable[substream->stream] = 1;
838 return 0;
839 @@ -406,9 +396,7 @@ static void mt2701_btmrg_shutdown(struct
840 AFE_MRGIF_CON_MRG_EN, 0);
841 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
842 AFE_MRGIF_CON_MRG_I2S_EN, 0);
843 - regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
844 - AUDIO_TOP_CON4_PDN_MRGIF,
845 - AUDIO_TOP_CON4_PDN_MRGIF);
846 + mt2701_disable_btmrg_clk(afe);
847 }
848 afe_priv->mrg_enable[substream->stream] = 0;
849 }
850 @@ -1386,14 +1374,12 @@ static const struct mt2701_i2s_data mt27
851 {
852 {
853 .i2s_ctrl_reg = ASYS_I2SO1_CON,
854 - .i2s_pwn_shift = 6,
855 .i2s_asrc_fs_shift = 0,
856 .i2s_asrc_fs_mask = 0x1f,
857
858 },
859 {
860 .i2s_ctrl_reg = ASYS_I2SIN1_CON,
861 - .i2s_pwn_shift = 0,
862 .i2s_asrc_fs_shift = 0,
863 .i2s_asrc_fs_mask = 0x1f,
864
865 @@ -1402,14 +1388,12 @@ static const struct mt2701_i2s_data mt27
866 {
867 {
868 .i2s_ctrl_reg = ASYS_I2SO2_CON,
869 - .i2s_pwn_shift = 7,
870 .i2s_asrc_fs_shift = 5,
871 .i2s_asrc_fs_mask = 0x1f,
872
873 },
874 {
875 .i2s_ctrl_reg = ASYS_I2SIN2_CON,
876 - .i2s_pwn_shift = 1,
877 .i2s_asrc_fs_shift = 5,
878 .i2s_asrc_fs_mask = 0x1f,
879
880 @@ -1418,14 +1402,12 @@ static const struct mt2701_i2s_data mt27
881 {
882 {
883 .i2s_ctrl_reg = ASYS_I2SO3_CON,
884 - .i2s_pwn_shift = 8,
885 .i2s_asrc_fs_shift = 10,
886 .i2s_asrc_fs_mask = 0x1f,
887
888 },
889 {
890 .i2s_ctrl_reg = ASYS_I2SIN3_CON,
891 - .i2s_pwn_shift = 2,
892 .i2s_asrc_fs_shift = 10,
893 .i2s_asrc_fs_mask = 0x1f,
894
895 @@ -1434,14 +1416,12 @@ static const struct mt2701_i2s_data mt27
896 {
897 {
898 .i2s_ctrl_reg = ASYS_I2SO4_CON,
899 - .i2s_pwn_shift = 9,
900 .i2s_asrc_fs_shift = 15,
901 .i2s_asrc_fs_mask = 0x1f,
902
903 },
904 {
905 .i2s_ctrl_reg = ASYS_I2SIN4_CON,
906 - .i2s_pwn_shift = 3,
907 .i2s_asrc_fs_shift = 15,
908 .i2s_asrc_fs_mask = 0x1f,
909
910 @@ -1483,8 +1463,7 @@ static int mt2701_afe_runtime_suspend(st
911 {
912 struct mtk_base_afe *afe = dev_get_drvdata(dev);
913
914 - mt2701_afe_disable_clock(afe);
915 - return 0;
916 + return mt2701_afe_disable_clock(afe);
917 }
918
919 static int mt2701_afe_runtime_resume(struct device *dev)
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