target/linux/mediatek/files-5.10/drivers/net/phy/rtk/rtl8367s_mdio.c

   1 /*
   2  * This program is free software; you can redistribute it and/or
   3  * modify it under the terms of the GNU General Public License
   4  * as published by the Free Software Foundation; either version 2
   5  * of the License, or (at your option) any later version.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/delay.h>
  19 #include <linux/of_mdio.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/of_gpio.h>
  22
  23
  24 #include  "./rtl8367c/include/rtk_switch.h"
  25 #include  "./rtl8367c/include/port.h"
  26 #include  "./rtl8367c/include/vlan.h"
  27 #include  "./rtl8367c/include/rtl8367c_asicdrv_port.h"
  28
  29 struct rtk_gsw {
  30         struct device           *dev;
  31         struct mii_bus          *bus;
  32         int reset_pin;
  33 };
  34
  35 static struct rtk_gsw *_gsw;
  36
  37 extern int gsw_debug_proc_init(void);
  38 extern void gsw_debug_proc_exit(void);
  39
  40 #ifdef CONFIG_SWCONFIG
  41 extern int rtl8367s_swconfig_init( void (*reset_func)(void) );
  42 #endif
  43
  44 /*mii_mgr_read/mii_mgr_write is the callback API for rtl8367 driver*/
  45 unsigned int mii_mgr_read(unsigned int phy_addr,unsigned int phy_register,unsigned int *read_data)
  46 {
  47         struct mii_bus *bus = _gsw->bus;
  48
  49         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
  50
  51         *read_data = bus->read(bus, phy_addr, phy_register);
  52
  53         mutex_unlock(&bus->mdio_lock);
  54
  55         return 0;
  56 }
  57
  58 unsigned int mii_mgr_write(unsigned int phy_addr,unsigned int phy_register,unsigned int write_data)
  59 {
  60         struct mii_bus *bus =  _gsw->bus;
  61
  62         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
  63
  64         bus->write(bus, phy_addr, phy_register, write_data);
  65
  66         mutex_unlock(&bus->mdio_lock);
  67
  68         return 0;
  69 }
  70
  71 static int rtl8367s_hw_reset(void)
  72 {
  73         struct rtk_gsw *gsw = _gsw;
  74         int ret;
  75
  76         if (gsw->reset_pin < 0)
  77                 return 0;
  78
  79         ret = devm_gpio_request(gsw->dev, gsw->reset_pin, "mediatek,reset-pin");
  80
  81         if (ret)
  82                 printk("fail to devm_gpio_request\n");
  83
  84         gpio_direction_output(gsw->reset_pin, 0);
  85
  86         usleep_range(1000, 1100);
  87
  88         gpio_set_value(gsw->reset_pin, 1);
  89
  90         mdelay(500);
  91
  92         devm_gpio_free(gsw->dev, gsw->reset_pin);
  93
  94         return 0;
  95
  96 }
  97
  98 static int rtl8367s_vlan_config(int want_at_p0)
  99 {
 100         rtk_vlan_cfg_t vlan1, vlan2;
 101
 102         /* Set LAN/WAN VLAN partition */
 103         memset(&vlan1, 0x00, sizeof(rtk_vlan_cfg_t));
 104
 105         RTK_PORTMASK_PORT_SET(vlan1.mbr, EXT_PORT0);
 106         RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT1);
 107         RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT2);
 108         RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT3);
 109         RTK_PORTMASK_PORT_SET(vlan1.untag, EXT_PORT0);
 110         RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT1);
 111         RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT2);
 112         RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT3);
 113
 114          if (want_at_p0) {
 115                 RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT4);
 116                 RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT4);
 117         } else {
 118                 RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT0);
 119                 RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT0);
 120         }
 121
 122         vlan1.ivl_en = 1;
 123
 124         rtk_vlan_set(1, &vlan1);
 125
 126         memset(&vlan2, 0x00, sizeof(rtk_vlan_cfg_t));
 127
 128         RTK_PORTMASK_PORT_SET(vlan2.mbr, EXT_PORT1);
 129         RTK_PORTMASK_PORT_SET(vlan2.untag, EXT_PORT1);
 130
 131         if (want_at_p0) {
 132                 RTK_PORTMASK_PORT_SET(vlan2.mbr, UTP_PORT0);
 133                 RTK_PORTMASK_PORT_SET(vlan2.untag, UTP_PORT0);
 134         } else {
 135                 RTK_PORTMASK_PORT_SET(vlan2.mbr, UTP_PORT4);
 136                 RTK_PORTMASK_PORT_SET(vlan2.untag, UTP_PORT4);
 137         }
 138
 139         vlan2.ivl_en = 1;
 140         rtk_vlan_set(2, &vlan2);
 141
 142         rtk_vlan_portPvid_set(EXT_PORT0, 1, 0);
 143         rtk_vlan_portPvid_set(UTP_PORT1, 1, 0);
 144         rtk_vlan_portPvid_set(UTP_PORT2, 1, 0);
 145         rtk_vlan_portPvid_set(UTP_PORT3, 1, 0);
 146         rtk_vlan_portPvid_set(EXT_PORT1, 2, 0);
 147
 148         if (want_at_p0) {
 149                 rtk_vlan_portPvid_set(UTP_PORT0, 2, 0);
 150                 rtk_vlan_portPvid_set(UTP_PORT4, 1, 0);
 151         } else {
 152                 rtk_vlan_portPvid_set(UTP_PORT0, 1, 0);
 153                 rtk_vlan_portPvid_set(UTP_PORT4, 2, 0);
 154         }
 155
 156         return 0;
 157 }
 158
 159 static int rtl8367s_hw_init(void)
 160 {
 161
 162         rtl8367s_hw_reset();
 163
 164         if(rtk_switch_init())
 165                 return -1;
 166
 167         mdelay(500);
 168
 169         if (rtk_vlan_reset())
 170                 return -1;
 171
 172         if (rtk_vlan_init())
 173                 return -1;
 174
 175         return 0;
 176 }
 177
 178 static void set_rtl8367s_sgmii(void)
 179 {
 180         rtk_port_mac_ability_t mac_cfg;
 181         rtk_mode_ext_t mode;
 182
 183         mode = MODE_EXT_HSGMII;
 184         mac_cfg.forcemode = MAC_FORCE;
 185         mac_cfg.speed = PORT_SPEED_2500M;
 186         mac_cfg.duplex = PORT_FULL_DUPLEX;
 187         mac_cfg.link = PORT_LINKUP;
 188         mac_cfg.nway = DISABLED;
 189         mac_cfg.txpause = ENABLED;
 190         mac_cfg.rxpause = ENABLED;
 191         rtk_port_macForceLinkExt_set(EXT_PORT0, mode, &mac_cfg);
 192         rtk_port_sgmiiNway_set(EXT_PORT0, DISABLED);
 193         rtk_port_phyEnableAll_set(ENABLED);
 194
 195 }
 196
 197 static void set_rtl8367s_rgmii(void)
 198 {
 199         rtk_port_mac_ability_t mac_cfg;
 200         rtk_mode_ext_t mode;
 201
 202         mode = MODE_EXT_RGMII;
 203         mac_cfg.forcemode = MAC_FORCE;
 204         mac_cfg.speed = PORT_SPEED_1000M;
 205         mac_cfg.duplex = PORT_FULL_DUPLEX;
 206         mac_cfg.link = PORT_LINKUP;
 207         mac_cfg.nway = DISABLED;
 208         mac_cfg.txpause = ENABLED;
 209         mac_cfg.rxpause = ENABLED;
 210         rtk_port_macForceLinkExt_set(EXT_PORT1, mode, &mac_cfg);
 211         rtk_port_rgmiiDelayExt_set(EXT_PORT1, 1, 3);
 212         rtk_port_phyEnableAll_set(ENABLED);
 213
 214 }
 215
 216 void init_gsw(void)
 217 {
 218         rtl8367s_hw_init();
 219         set_rtl8367s_sgmii();
 220         set_rtl8367s_rgmii();
 221 }
 222
 223 // bleow are platform driver
 224 static const struct of_device_id rtk_gsw_match[] = {
 225         { .compatible = "mediatek,rtk-gsw" },
 226         {},
 227 };
 228
 229 MODULE_DEVICE_TABLE(of, rtk_gsw_match);
 230
 231 static int rtk_gsw_probe(struct platform_device *pdev)
 232 {
 233         struct device_node *np = pdev->dev.of_node;
 234         struct device_node *mdio;
 235         struct mii_bus *mdio_bus;
 236         struct rtk_gsw *gsw;
 237         const char *pm;
 238
 239         mdio = of_parse_phandle(np, "mediatek,mdio", 0);
 240
 241         if (!mdio)
 242                 return -EINVAL;
 243
 244         mdio_bus = of_mdio_find_bus(mdio);
 245
 246         if (!mdio_bus)
 247                 return -EPROBE_DEFER;
 248
 249         gsw = devm_kzalloc(&pdev->dev, sizeof(struct rtk_gsw), GFP_KERNEL);
 250
 251         if (!gsw)
 252                 return -ENOMEM;
 253
 254         gsw->dev = &pdev->dev;
 255
 256         gsw->bus = mdio_bus;
 257
 258         gsw->reset_pin = of_get_named_gpio(np, "mediatek,reset-pin", 0);
 259
 260         _gsw = gsw;
 261
 262         init_gsw();
 263
 264         //init default vlan or init swocnfig
 265         if(!of_property_read_string(pdev->dev.of_node,
 266                                                 "mediatek,port_map", &pm)) {
 267
 268                 if (!strcasecmp(pm, "wllll"))
 269                         rtl8367s_vlan_config(1);
 270                 else
 271                         rtl8367s_vlan_config(0);
 272
 273                 } else {
 274 #ifdef CONFIG_SWCONFIG
 275                 rtl8367s_swconfig_init(&init_gsw);
 276 #else
 277                 rtl8367s_vlan_config(0);
 278 #endif
 279         }
 280
 281         gsw_debug_proc_init();
 282
 283         platform_set_drvdata(pdev, gsw);
 284
 285         return 0;
 286
 287 }
 288
 289 static int rtk_gsw_remove(struct platform_device *pdev)
 290 {
 291         platform_set_drvdata(pdev, NULL);
 292         gsw_debug_proc_exit();
 293
 294         return 0;
 295 }
 296
 297 static struct platform_driver gsw_driver = {
 298         .probe = rtk_gsw_probe,
 299         .remove = rtk_gsw_remove,
 300         .driver = {
 301                 .name = "rtk-gsw",
 302                 .owner = THIS_MODULE,
 303                 .of_match_table = rtk_gsw_match,
 304         },
 305 };
 306
 307 module_platform_driver(gsw_driver);
 308
 309 MODULE_LICENSE("GPL");
 310 MODULE_AUTHOR("Mark Lee <marklee0201@gmail.com>");
 311 MODULE_DESCRIPTION("rtl8367c switch driver for MT7622");
 312