target/linux/mediatek/files-5.10/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_acl.h

   1 /*
   2  * Copyright (C) 2013 Realtek Semiconductor Corp.
   3  * All Rights Reserved.
   4  *
   5  * Unless you and Realtek execute a separate written software license
   6  * agreement governing use of this software, this software is licensed
   7  * to you under the terms of the GNU General Public License version 2,
   8  * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
   9  *
  10  * $Revision: 76306 $
  11  * $Date: 2017-03-08 15:13:58 +0800 (¶g¤T, 08 ¤T¤ë 2017) $
  12  *
  13  * Purpose : RTL8367C switch high-level API for RTL8367C
  14  * Feature : ACL related function drivers
  15  *
  16  */
  17
  18 #ifndef _RTL8367C_ASICDRV_ACL_H_
  19 #define _RTL8367C_ASICDRV_ACL_H_
  20
  21 #include <rtl8367c_asicdrv.h>
  22
  23 #define RTL8367C_ACLRULENO                  96
  24
  25 #define RTL8367C_ACLRULEMAX                 (RTL8367C_ACLRULENO-1)
  26 #define RTL8367C_ACLRULEFIELDNO             8
  27 #define RTL8367C_ACLTEMPLATENO              5
  28 #define RTL8367C_ACLTYPEMAX                 (RTL8367C_ACLTEMPLATENO-1)
  29
  30 #define RTL8367C_ACLRULETBLEN               9
  31 #define RTL8367C_ACLACTTBLEN                4
  32 #define RTL8367C_ACLRULETBADDR(type, rule)  ((type << 6) | rule)
  33 #define RTL8367C_ACLRULETBADDR2(type, rule) ((type << 5) | (rule + 64))
  34
  35 #define ACL_ACT_CVLAN_ENABLE_MASK           0x1
  36 #define ACL_ACT_SVLAN_ENABLE_MASK           0x2
  37 #define ACL_ACT_PRIORITY_ENABLE_MASK        0x4
  38 #define ACL_ACT_POLICING_ENABLE_MASK        0x8
  39 #define ACL_ACT_FWD_ENABLE_MASK             0x10
  40 #define ACL_ACT_INTGPIO_ENABLE_MASK         0x20
  41
  42 #define RTL8367C_ACLRULETAGBITS             5
  43
  44 #define RTL8367C_ACLRANGENO                 16
  45
  46 #define RTL8367C_ACLRANGEMAX                (RTL8367C_ACLRANGENO-1)
  47
  48 #define RTL8367C_ACL_PORTRANGEMAX           (0xFFFF)
  49 #define RTL8367C_ACL_ACT_TABLE_LEN          (4)
  50
  51 enum ACLTCAMTYPES
  52 {
  53     CAREBITS= 0,
  54     DATABITS
  55 };
  56
  57 typedef enum aclFwdAct
  58 {
  59     RTL8367C_ACL_FWD_MIRROR = 0,
  60     RTL8367C_ACL_FWD_REDIRECT,
  61     RTL8367C_ACL_FWD_MIRRORFUNTION,
  62     RTL8367C_ACL_FWD_TRAP,
  63 } rtl8367c_aclFwd_t;
  64
  65 enum ACLFIELDTYPES
  66 {
  67     ACL_UNUSED,
  68     ACL_DMAC0,
  69     ACL_DMAC1,
  70     ACL_DMAC2,
  71     ACL_SMAC0,
  72     ACL_SMAC1,
  73     ACL_SMAC2,
  74     ACL_ETHERTYPE,
  75     ACL_STAG,
  76     ACL_CTAG,
  77     ACL_IP4SIP0 = 0x10,
  78     ACL_IP4SIP1,
  79     ACL_IP4DIP0,
  80     ACL_IP4DIP1,
  81     ACL_IP6SIP0WITHIPV4 = 0x20,
  82     ACL_IP6SIP1WITHIPV4,
  83     ACL_IP6DIP0WITHIPV4 = 0x28,
  84     ACL_IP6DIP1WITHIPV4,
  85     ACL_VIDRANGE = 0x30,
  86     ACL_IPRANGE,
  87     ACL_PORTRANGE,
  88     ACL_FIELD_VALID,
  89     ACL_FIELD_SELECT00 = 0x40,
  90     ACL_FIELD_SELECT01,
  91     ACL_FIELD_SELECT02,
  92     ACL_FIELD_SELECT03,
  93     ACL_FIELD_SELECT04,
  94     ACL_FIELD_SELECT05,
  95     ACL_FIELD_SELECT06,
  96     ACL_FIELD_SELECT07,
  97     ACL_FIELD_SELECT08,
  98     ACL_FIELD_SELECT09,
  99     ACL_FIELD_SELECT10,
 100     ACL_FIELD_SELECT11,
 101     ACL_FIELD_SELECT12,
 102     ACL_FIELD_SELECT13,
 103     ACL_FIELD_SELECT14,
 104     ACL_FIELD_SELECT15,
 105     ACL_TCPSPORT = 0x80,
 106     ACL_TCPDPORT,
 107     ACL_TCPFLAG,
 108     ACL_UDPSPORT,
 109     ACL_UDPDPORT,
 110     ACL_ICMPCODETYPE,
 111     ACL_IGMPTYPE,
 112     ACL_SPORT,
 113     ACL_DPORT,
 114     ACL_IP4TOSPROTO,
 115     ACL_IP4FLAGOFF,
 116     ACL_TCNH,
 117     ACL_CPUTAG,
 118     ACL_L2PAYLOAD,
 119     ACL_IP6SIP0,
 120     ACL_IP6SIP1,
 121     ACL_IP6SIP2,
 122     ACL_IP6SIP3,
 123     ACL_IP6SIP4,
 124     ACL_IP6SIP5,
 125     ACL_IP6SIP6,
 126     ACL_IP6SIP7,
 127     ACL_IP6DIP0,
 128     ACL_IP6DIP1,
 129     ACL_IP6DIP2,
 130     ACL_IP6DIP3,
 131     ACL_IP6DIP4,
 132     ACL_IP6DIP5,
 133     ACL_IP6DIP6,
 134     ACL_IP6DIP7,
 135     ACL_TYPE_END
 136 };
 137
 138 struct acl_rule_smi_st{
 139     rtk_uint16 rule_info;
 140     rtk_uint16 field[RTL8367C_ACLRULEFIELDNO];
 141 };
 142
 143 struct acl_rule_smi_ext_st{
 144     rtk_uint16 rule_info;
 145 };
 146
 147 typedef struct ACLRULESMI{
 148     struct acl_rule_smi_st  care_bits;
 149     rtk_uint16      valid:1;
 150     struct acl_rule_smi_st  data_bits;
 151
 152     struct acl_rule_smi_ext_st care_bits_ext;
 153     struct acl_rule_smi_ext_st data_bits_ext;
 154 }rtl8367c_aclrulesmi;
 155
 156 struct acl_rule_st{
 157     rtk_uint16 active_portmsk:11;
 158     rtk_uint16 type:3;
 159     rtk_uint16 tag_exist:5;
 160     rtk_uint16 field[RTL8367C_ACLRULEFIELDNO];
 161 };
 162
 163 typedef struct ACLRULE{
 164     struct acl_rule_st  data_bits;
 165     rtk_uint16      valid:1;
 166     struct acl_rule_st  care_bits;
 167 }rtl8367c_aclrule;
 168
 169
 170 typedef struct rtl8367c_acltemplate_s{
 171     rtk_uint8 field[8];
 172 }rtl8367c_acltemplate_t;
 173
 174
 175 typedef struct acl_act_s{
 176     rtk_uint16 cvidx_cact:7;
 177     rtk_uint16 cact:2;
 178     rtk_uint16 svidx_sact:7;
 179     rtk_uint16 sact:2;
 180
 181
 182     rtk_uint16 aclmeteridx:7;
 183     rtk_uint16 fwdpmask:11;
 184     rtk_uint16 fwdact:2;
 185
 186     rtk_uint16 pridx:7;
 187     rtk_uint16 priact:2;
 188     rtk_uint16 gpio_pin:4;
 189     rtk_uint16 gpio_en:1;
 190     rtk_uint16 aclint:1;
 191
 192     rtk_uint16 cact_ext:2;
 193     rtk_uint16 fwdact_ext:1;
 194     rtk_uint16 tag_fmt:2;
 195 }rtl8367c_acl_act_t;
 196
 197 typedef struct acl_rule_union_s
 198 {
 199     rtl8367c_aclrule aclRule;
 200     rtl8367c_acl_act_t aclAct;
 201     rtk_uint32 aclActCtrl;
 202     rtk_uint32 aclNot;
 203 }rtl8367c_acl_rule_union_t;
 204
 205
 206 extern ret_t rtl8367c_setAsicAcl(rtk_uint32 port, rtk_uint32 enabled);
 207 extern ret_t rtl8367c_getAsicAcl(rtk_uint32 port, rtk_uint32* pEnabled);
 208 extern ret_t rtl8367c_setAsicAclUnmatchedPermit(rtk_uint32 port, rtk_uint32 enabled);
 209 extern ret_t rtl8367c_getAsicAclUnmatchedPermit(rtk_uint32 port, rtk_uint32* pEnabled);
 210 extern ret_t rtl8367c_setAsicAclRule(rtk_uint32 index, rtl8367c_aclrule *pAclRule);
 211 extern ret_t rtl8367c_getAsicAclRule(rtk_uint32 index, rtl8367c_aclrule *pAclRule);
 212 extern ret_t rtl8367c_setAsicAclNot(rtk_uint32 index, rtk_uint32 not);
 213 extern ret_t rtl8367c_getAsicAclNot(rtk_uint32 index, rtk_uint32* pNot);
 214 extern ret_t rtl8367c_setAsicAclTemplate(rtk_uint32 index, rtl8367c_acltemplate_t* pAclType);
 215 extern ret_t rtl8367c_getAsicAclTemplate(rtk_uint32 index, rtl8367c_acltemplate_t *pAclType);
 216 extern ret_t rtl8367c_setAsicAclAct(rtk_uint32 index, rtl8367c_acl_act_t* pAclAct);
 217 extern ret_t rtl8367c_getAsicAclAct(rtk_uint32 index, rtl8367c_acl_act_t *pAclAct);
 218 extern ret_t rtl8367c_setAsicAclActCtrl(rtk_uint32 index, rtk_uint32 aclActCtrl);
 219 extern ret_t rtl8367c_getAsicAclActCtrl(rtk_uint32 index, rtk_uint32 *aclActCtrl);
 220 extern ret_t rtl8367c_setAsicAclPortRange(rtk_uint32 index, rtk_uint32 type, rtk_uint32 upperPort, rtk_uint32 lowerPort);
 221 extern ret_t rtl8367c_getAsicAclPortRange(rtk_uint32 index, rtk_uint32* pType, rtk_uint32* pUpperPort, rtk_uint32* pLowerPort);
 222 extern ret_t rtl8367c_setAsicAclVidRange(rtk_uint32 index, rtk_uint32 type, rtk_uint32 upperVid, rtk_uint32 lowerVid);
 223 extern ret_t rtl8367c_getAsicAclVidRange(rtk_uint32 index, rtk_uint32* pType, rtk_uint32* pUpperVid, rtk_uint32* pLowerVid);
 224 extern ret_t rtl8367c_setAsicAclIpRange(rtk_uint32 index, rtk_uint32 type, ipaddr_t upperIp, ipaddr_t lowerIp);
 225 extern ret_t rtl8367c_getAsicAclIpRange(rtk_uint32 index, rtk_uint32* pType, ipaddr_t* pUpperIp, ipaddr_t* pLowerIp);
 226 extern ret_t rtl8367c_setAsicAclGpioPolarity(rtk_uint32 polarity);
 227 extern ret_t rtl8367c_getAsicAclGpioPolarity(rtk_uint32* pPolarity);
 228
 229 #endif /*_RTL8367C_ASICDRV_ACL_H_*/
 230
 231