target/linux/mediatek/files-4.19/drivers/net/phy/mtk/mt753x/mt753x.h

   1 /*
   2  * Driver for MediaTek MT753x gigabit switch
   3  *
   4  * Copyright (C) 2018 MediaTek Inc. All Rights Reserved.
   5  *
   6  * Author: Weijie Gao <weijie.gao@mediatek.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef _MT753X_H_
  12 #define _MT753X_H_
  13
  14 #include <linux/list.h>
  15 #include <linux/mutex.h>
  16 #include <linux/netdevice.h>
  17 #include <linux/of_mdio.h>
  18 #include <linux/workqueue.h>
  19 #include <linux/gpio/consumer.h>
  20
  21 #ifdef CONFIG_SWCONFIG
  22 #include <linux/switch.h>
  23 #endif
  24
  25 #define MT753X_DFL_CPU_PORT     6
  26 #define MT753X_NUM_PORTS        7
  27 #define MT753X_NUM_PHYS         5
  28 #define MT753X_NUM_VLANS        4095
  29
  30 #define MT753X_MAX_VID          4095
  31 #define MT753X_MIN_VID          0
  32
  33 #define MT753X_DFL_SMI_ADDR     0x1f
  34 #define MT753X_SMI_ADDR_MASK    0x1f
  35
  36 struct gsw_mt753x;
  37
  38 enum mt753x_model {
  39         MT7530 = 0x7530,
  40         MT7531 = 0x7531
  41 };
  42
  43 struct mt753x_port_entry {
  44         u16     pvid;
  45 };
  46
  47 struct mt753x_vlan_entry {
  48         u16     vid;
  49         u8      member;
  50         u8      etags;
  51 };
  52
  53 struct mt753x_port_cfg {
  54         struct device_node *np;
  55         int phy_mode;
  56         u32 enabled: 1;
  57         u32 force_link: 1;
  58         u32 speed: 2;
  59         u32 duplex: 1;
  60 };
  61
  62 struct mt753x_phy {
  63         struct gsw_mt753x *gsw;
  64         struct net_device netdev;
  65         struct phy_device *phydev;
  66 };
  67
  68 struct gsw_mt753x {
  69         u32 id;
  70
  71         struct device *dev;
  72         struct mii_bus *host_bus;
  73         struct mii_bus *gphy_bus;
  74         struct mutex mii_lock;  /* MII access lock */
  75         u32 smi_addr;
  76         u32 phy_base;
  77         int direct_phy_access;
  78
  79         enum mt753x_model model;
  80         const char *name;
  81
  82         struct mt753x_port_cfg port5_cfg;
  83         struct mt753x_port_cfg port6_cfg;
  84
  85         bool phy_status_poll;
  86         struct mt753x_phy phys[MT753X_NUM_PHYS];
  87
  88         int phy_link_sts;
  89
  90         int irq;
  91         int reset_pin;
  92         struct work_struct irq_worker;
  93
  94 #ifdef CONFIG_SWCONFIG
  95         struct switch_dev swdev;
  96
  97         struct mt753x_vlan_entry vlan_entries[MT753X_NUM_VLANS];
  98         struct mt753x_port_entry port_entries[MT753X_NUM_PORTS];
  99
 100         int global_vlan_enable;
 101         u32 cpu_port;
 102 #endif
 103
 104         int (*mii_read)(struct gsw_mt753x *gsw, int phy, int reg);
 105         void (*mii_write)(struct gsw_mt753x *gsw, int phy, int reg, u16 val);
 106
 107         int (*mmd_read)(struct gsw_mt753x *gsw, int addr, int devad, u16 reg);
 108         void (*mmd_write)(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
 109                           u16 val);
 110
 111         struct list_head list;
 112 };
 113
 114 struct chip_rev {
 115         const char *name;
 116         u32 rev;
 117 };
 118
 119 struct mt753x_sw_id {
 120         enum mt753x_model model;
 121         int (*detect)(struct gsw_mt753x *gsw, struct chip_rev *crev);
 122         int (*init)(struct gsw_mt753x *gsw);
 123         int (*post_init)(struct gsw_mt753x *gsw);
 124 };
 125
 126 extern struct list_head mt753x_devs;
 127
 128 struct gsw_mt753x *mt753x_get_gsw(u32 id);
 129 struct gsw_mt753x *mt753x_get_first_gsw(void);
 130 void mt753x_put_gsw(void);
 131 void mt753x_lock_gsw(void);
 132
 133 u32 mt753x_reg_read(struct gsw_mt753x *gsw, u32 reg);
 134 void mt753x_reg_write(struct gsw_mt753x *gsw, u32 reg, u32 val);
 135
 136 int mt753x_mii_read(struct gsw_mt753x *gsw, int phy, int reg);
 137 void mt753x_mii_write(struct gsw_mt753x *gsw, int phy, int reg, u16 val);
 138
 139 int mt753x_mmd_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg);
 140 void mt753x_mmd_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
 141                       u16 val);
 142
 143 int mt753x_mmd_ind_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg);
 144 void mt753x_mmd_ind_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
 145                           u16 val);
 146
 147 void mt753x_irq_worker(struct work_struct *work);
 148 void mt753x_irq_enable(struct gsw_mt753x *gsw);
 149
 150 /* MDIO Indirect Access Registers */
 151 #define MII_MMD_ACC_CTL_REG             0x0d
 152 #define MMD_CMD_S                       14
 153 #define MMD_CMD_M                       0xc000
 154 #define MMD_DEVAD_S                     0
 155 #define MMD_DEVAD_M                     0x1f
 156
 157 /* MMD_CMD: MMD commands */
 158 #define MMD_ADDR                        0
 159 #define MMD_DATA                        1
 160
 161 #define MII_MMD_ADDR_DATA_REG           0x0e
 162
 163 /* Procedure of MT753x Internal Register Access
 164  *
 165  * 1. Internal Register Address
 166  *
 167  *    The MT753x has a 16-bit register address and each register is 32-bit.
 168  *    This means the lowest two bits are not used as the register address is
 169  *    4-byte aligned.
 170  *
 171  *    Rest of the valid bits are divided into two parts:
 172  *      Bit 15..6 is the Page address
 173  *      Bit 5..2 is the low address
 174  *
 175  *    -------------------------------------------------------------------
 176  *    | 15  14  13  12  11  10   9   8   7   6 | 5   4   3   2 | 1   0  |
 177  *    |----------------------------------------|---------------|--------|
 178  *    |              Page Address              |    Address    | Unused |
 179  *    -------------------------------------------------------------------
 180  *
 181  * 2. MDIO access timing
 182  *
 183  *    The MT753x uses the following MDIO timing for a single register read
 184  *
 185  *      Phase 1: Write Page Address
 186  *    -------------------------------------------------------------------
 187  *    | ST | OP | PHY_ADDR | TYPE | RSVD | TA |  RSVD |    PAGE_ADDR    |
 188  *    -------------------------------------------------------------------
 189  *    | 01 | 01 |   11111  |   1  | 1111 | xx | 00000 | REG_ADDR[15..6] |
 190  *    -------------------------------------------------------------------
 191  *
 192  *      Phase 2: Write low Address & Read low word
 193  *    -------------------------------------------------------------------
 194  *    | ST | OP | PHY_ADDR | TYPE |    LOW_ADDR    | TA |      DATA     |
 195  *    -------------------------------------------------------------------
 196  *    | 01 | 10 |   11111  |   0  | REG_ADDR[5..2] | xx |  DATA[15..0]  |
 197  *    -------------------------------------------------------------------
 198  *
 199  *      Phase 3: Read high word
 200  *    -------------------------------------------------------------------
 201  *    | ST | OP | PHY_ADDR | TYPE | RSVD | TA |           DATA          |
 202  *    -------------------------------------------------------------------
 203  *    | 01 | 10 |   11111  |   1  | 0000 | xx |       DATA[31..16]      |
 204  *    -------------------------------------------------------------------
 205  *
 206  *    The MT753x uses the following MDIO timing for a single register write
 207  *
 208  *      Phase 1: Write Page Address (The same as read)
 209  *
 210  *      Phase 2: Write low Address and low word
 211  *    -------------------------------------------------------------------
 212  *    | ST | OP | PHY_ADDR | TYPE |    LOW_ADDR    | TA |      DATA     |
 213  *    -------------------------------------------------------------------
 214  *    | 01 | 01 |   11111  |   0  | REG_ADDR[5..2] | xx |  DATA[15..0]  |
 215  *    -------------------------------------------------------------------
 216  *
 217  *      Phase 3: write high word
 218  *    -------------------------------------------------------------------
 219  *    | ST | OP | PHY_ADDR | TYPE | RSVD | TA |           DATA          |
 220  *    -------------------------------------------------------------------
 221  *    | 01 | 01 |   11111  |   1  | 0000 | xx |       DATA[31..16]      |
 222  *    -------------------------------------------------------------------
 223  *
 224  */
 225
 226 /* Internal Register Address fields */
 227 #define MT753X_REG_PAGE_ADDR_S          6
 228 #define MT753X_REG_PAGE_ADDR_M          0xffc0
 229 #define MT753X_REG_ADDR_S               2
 230 #define MT753X_REG_ADDR_M               0x3c
 231
 232 #endif /* _MT753X_H_ */