target/linux/mediatek/files-4.19/arch/arm/boot/dts/mt7629.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2019 MediaTek Inc.
   4  *
   5  * Author: Ryder Lee <ryder.lee@mediatek.com>
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/clock/mt7629-clk.h>
  11 #include <dt-bindings/power/mt7622-power.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/phy/phy.h>
  14 #include <dt-bindings/reset/mt7629-resets.h>
  15
  16 / {
  17         compatible = "mediatek,mt7629";
  18         interrupt-parent = <&sysirq>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25                 enable-method = "mediatek,mt6589-smp";
  26
  27                 cpu0: cpu@0 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a7";
  30                         reg = <0x0>;
  31                         clock-frequency = <1250000000>;
  32                         cci-control-port = <&cci_control2>;
  33                 };
  34
  35                 cpu1: cpu@1 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a7";
  38                         reg = <0x1>;
  39                         clock-frequency = <1250000000>;
  40                         cci-control-port = <&cci_control2>;
  41                 };
  42         };
  43
  44         pmu {
  45                 compatible = "arm,cortex-a7-pmu";
  46                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
  47                              <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
  48                 interrupt-affinity = <&cpu0>, <&cpu1>;
  49         };
  50
  51         clk20m: oscillator-0 {
  52                 compatible = "fixed-clock";
  53                 #clock-cells = <0>;
  54                 clock-frequency = <20000000>;
  55                 clock-output-names = "clk20m";
  56         };
  57
  58         clk40m: oscillator-1 {
  59                 compatible = "fixed-clock";
  60                 #clock-cells = <0>;
  61                 clock-frequency = <40000000>;
  62                 clock-output-names = "clkxtal";
  63         };
  64
  65         timer {
  66                 compatible = "arm,armv7-timer";
  67                 interrupt-parent = <&gic>;
  68                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  69                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  70                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  71                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  72                 clock-frequency = <20000000>;
  73                 arm,cpu-registers-not-fw-configured;
  74         };
  75
  76         soc {
  77                 compatible = "simple-bus";
  78                 #address-cells = <1>;
  79                 #size-cells = <1>;
  80                 ranges;
  81
  82                 infracfg: syscon@10000000 {
  83                         compatible = "mediatek,mt7629-infracfg", "syscon";
  84                         reg = <0x10000000 0x1000>;
  85                         #clock-cells = <1>;
  86                 };
  87
  88                 pericfg: syscon@10002000 {
  89                         compatible = "mediatek,mt7629-pericfg", "syscon";
  90                         reg = <0x10002000 0x1000>;
  91                         #clock-cells = <1>;
  92                 };
  93
  94                 scpsys: scpsys@10006000 {
  95                         compatible = "mediatek,mt7629-scpsys",
  96                                      "mediatek,mt7622-scpsys";
  97                         #power-domain-cells = <1>;
  98                         reg = <0x10006000 0x1000>;
  99                         clocks = <&topckgen CLK_TOP_HIF_SEL>;
 100                         clock-names = "hif_sel";
 101                         assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
 102                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
 103                         infracfg = <&infracfg>;
 104                 };
 105
 106                 timer: timer@10009000 {
 107                         compatible = "mediatek,mt7629-timer",
 108                                      "mediatek,mt6765-timer";
 109                         reg = <0x10009000 0x60>;
 110                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 111                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 112                         clocks = <&clk20m>;
 113                         clock-names = "clk20m";
 114                 };
 115
 116                 sysirq: interrupt-controller@10200a80 {
 117                         compatible = "mediatek,mt7629-sysirq",
 118                                      "mediatek,mt6577-sysirq";
 119                         reg = <0x10200a80 0x20>;
 120                         interrupt-controller;
 121                         #interrupt-cells = <3>;
 122                         interrupt-parent = <&gic>;
 123                 };
 124
 125                 apmixedsys: syscon@10209000 {
 126                         compatible = "mediatek,mt7629-apmixedsys", "syscon";
 127                         reg = <0x10209000 0x1000>;
 128                         #clock-cells = <1>;
 129                 };
 130
 131                 rng: rng@1020f000 {
 132                         compatible = "mediatek,mt7629-rng",
 133                                      "mediatek,mt7623-rng";
 134                         reg = <0x1020f000 0x100>;
 135                         clocks = <&infracfg CLK_INFRA_TRNG_PD>;
 136                         clock-names = "rng";
 137                 };
 138
 139                 topckgen: syscon@10210000 {
 140                         compatible = "mediatek,mt7629-topckgen", "syscon";
 141                         reg = <0x10210000 0x1000>;
 142                         #clock-cells = <1>;
 143                 };
 144
 145                 watchdog: watchdog@10212000 {
 146                         compatible = "mediatek,mt7629-wdt",
 147                                      "mediatek,mt6589-wdt";
 148                         reg = <0x10212000 0x100>;
 149                 };
 150
 151                 pio: pinctrl@10217000 {
 152                         compatible = "mediatek,mt7629-pinctrl";
 153                         reg = <0x10217000 0x8000>,
 154                               <0x10005000 0x1000>;
 155                         reg-names = "base", "eint";
 156                         gpio-controller;
 157                         gpio-ranges = <&pio 0 0 79>;
 158                         #gpio-cells = <2>;
 159                         #interrupt-cells = <2>;
 160                         interrupt-controller;
 161                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 162                         interrupt-parent = <&gic>;
 163                 };
 164
 165                 gic: interrupt-controller@10300000 {
 166                         compatible = "arm,gic-400";
 167                         interrupt-controller;
 168                         #interrupt-cells = <3>;
 169                         interrupt-parent = <&gic>;
 170                         reg = <0x10310000 0x1000>,
 171                               <0x10320000 0x1000>,
 172                               <0x10340000 0x2000>,
 173                               <0x10360000 0x2000>;
 174                 };
 175
 176                 cci: cci@10390000 {
 177                         compatible = "arm,cci-400";
 178                         #address-cells = <1>;
 179                         #size-cells = <1>;
 180                         reg = <0x10390000 0x1000>;
 181                         ranges = <0 0x10390000 0x10000>;
 182
 183                         cci_control0: slave-if@1000 {
 184                                 compatible = "arm,cci-400-ctrl-if";
 185                                 interface-type = "ace-lite";
 186                                 reg = <0x1000 0x1000>;
 187                         };
 188
 189                         cci_control1: slave-if@4000 {
 190                                 compatible = "arm,cci-400-ctrl-if";
 191                                 interface-type = "ace";
 192                                 reg = <0x4000 0x1000>;
 193                         };
 194
 195                         cci_control2: slave-if@5000 {
 196                                 compatible = "arm,cci-400-ctrl-if";
 197                                 interface-type = "ace";
 198                                 reg = <0x5000 0x1000>;
 199                         };
 200
 201                         pmu@9000 {
 202                                 compatible = "arm,cci-400-pmu,r1";
 203                                 reg = <0x9000 0x5000>;
 204                                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 205                                              <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 206                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 207                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 208                                              <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 209                         };
 210                 };
 211
 212                 uart0: serial@11002000 {
 213                         compatible = "mediatek,mt7629-uart",
 214                                      "mediatek,mt6577-uart";
 215                         reg = <0x11002000 0x400>;
 216                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 217                         clocks = <&topckgen CLK_TOP_UART_SEL>,
 218                                  <&pericfg CLK_PERI_UART0_PD>;
 219                         clock-names = "baud", "bus";
 220                         status = "disabled";
 221                 };
 222
 223                 uart1: serial@11003000 {
 224                         compatible = "mediatek,mt7629-uart",
 225                                      "mediatek,mt6577-uart";
 226                         reg = <0x11003000 0x400>;
 227                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 228                         clocks = <&topckgen CLK_TOP_UART_SEL>,
 229                                  <&pericfg CLK_PERI_UART1_PD>;
 230                         clock-names = "baud", "bus";
 231                         status = "disabled";
 232                 };
 233
 234                 uart2: serial@11004000 {
 235                         compatible = "mediatek,mt7629-uart",
 236                                      "mediatek,mt6577-uart";
 237                         reg = <0x11004000 0x400>;
 238                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 239                         clocks = <&topckgen CLK_TOP_UART_SEL>,
 240                                  <&pericfg CLK_PERI_UART2_PD>;
 241                         clock-names = "baud", "bus";
 242                         status = "disabled";
 243                 };
 244
 245                 i2c: i2c@11007000 {
 246                         compatible = "mediatek,mt7629-i2c",
 247                                      "mediatek,mt2712-i2c";
 248                         reg = <0x11007000 0x90>,
 249                               <0x11000100 0x80>;
 250                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 251                         clock-div = <4>;
 252                         clocks = <&pericfg CLK_PERI_I2C0_PD>,
 253                                  <&pericfg CLK_PERI_AP_DMA_PD>;
 254                         clock-names = "main", "dma";
 255                         assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
 256                         assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
 257                         #address-cells = <1>;
 258                         #size-cells = <0>;
 259                         status = "disabled";
 260                 };
 261
 262                 spi: spi@1100a000 {
 263                         compatible = "mediatek,mt7629-spi",
 264                                      "mediatek,mt7622-spi";
 265                         #address-cells = <1>;
 266                         #size-cells = <0>;
 267                         reg = <0x1100a000 0x100>;
 268                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
 269                         clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 270                                  <&topckgen CLK_TOP_SPI0_SEL>,
 271                                  <&pericfg CLK_PERI_SPI0_PD>;
 272                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 273                         status = "disabled";
 274                 };
 275
 276                 qspi: spi@11014000 {
 277                         compatible = "mediatek,mt7629-nor",
 278                                      "mediatek,mt8173-nor";
 279                         reg = <0x11014000 0xe0>;
 280                         clocks = <&pericfg CLK_PERI_FLASH_PD>,
 281                                  <&topckgen CLK_TOP_FLASH_SEL>;
 282                         clock-names = "spi", "sf";
 283                         #address-cells = <1>;
 284                         #size-cells = <0>;
 285                         status = "disabled";
 286                 };
 287
 288                 wmac: wmac@18000000 {
 289                         compatible = "mediatek,mt7629-wmac";
 290                         reg = <0x18000000 0x100000>;
 291                         interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>,
 292                                      <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
 293                         mediatek,mtd-eeprom = <&factory 0x0000>;
 294                         status = "disabled";
 295                 };
 296
 297                 ssusbsys: syscon@1a000000 {
 298                         compatible = "mediatek,mt7629-ssusbsys", "syscon";
 299                         reg = <0x1a000000 0x1000>;
 300                         #clock-cells = <1>;
 301                         #reset-cells = <1>;
 302                 };
 303
 304                 ssusb: usb@1a0c0000 {
 305                         compatible = "mediatek,mt7629-xhci",
 306                                      "mediatek,mtk-xhci";
 307                         reg = <0x1a0c0000 0x01000>,
 308                               <0x1a0c3e00 0x0100>;
 309                         reg-names = "mac", "ippc";
 310                         interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
 311                         clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
 312                                  <&ssusbsys CLK_SSUSB_REF_EN>,
 313                                  <&ssusbsys CLK_SSUSB_MCU_EN>,
 314                                  <&ssusbsys CLK_SSUSB_DMA_EN>;
 315                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
 316                         assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
 317                                           <&topckgen CLK_TOP_SATA_SEL>,
 318                                           <&topckgen CLK_TOP_HIF_SEL>;
 319                         assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
 320                                                  <&topckgen CLK_TOP_UNIVPLL2_D4>,
 321                                                  <&topckgen CLK_TOP_UNIVPLL1_D2>;
 322                         power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
 323                         phys = <&u2port0 PHY_TYPE_USB2>,
 324                                <&u3port0 PHY_TYPE_USB3>;
 325                         status = "disabled";
 326                 };
 327
 328                 u3phy1: usb-phy@1a0c4000 {
 329                         compatible = "mediatek,generic-tphy-v2";
 330                         #address-cells = <1>;
 331                         #size-cells = <1>;
 332                         ranges;
 333                         status = "disabled";
 334
 335                         u2port0: usb-phy@1a0c4000 {
 336                                 reg = <0x1a0c4000 0x700>;
 337                                 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
 338                                 clock-names = "ref";
 339                                 #phy-cells = <1>;
 340                                 status = "okay";
 341                         };
 342
 343                         u3port0: usb-phy@1a1c4700 {
 344                                 reg = <0x1a1c4700 0x700>;
 345                                 clocks = <&clk20m>;
 346                                 clock-names = "ref";
 347                                 #phy-cells = <1>;
 348                                 status = "okay";
 349                         };
 350                 };
 351
 352                 pciesys: syscon@1a100800 {
 353                         compatible = "mediatek,mt7629-pciesys", "syscon";
 354                         reg = <0x1a100800 0x1000>;
 355                         #clock-cells = <1>;
 356                         #reset-cells = <1>;
 357                 };
 358
 359                 ethsys: syscon@1b000000 {
 360                         compatible = "mediatek,mt7629-ethsys", "syscon";
 361                         reg = <0x1b000000 0x1000>;
 362                         #clock-cells = <1>;
 363                         #reset-cells = <1>;
 364                 };
 365
 366                 eth: ethernet@1b100000 {
 367                 compatible = "mediatek,mt7629-eth",
 368                                 "syscon";
 369                 reg = <0x1b100000 0x20000>;
 370                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
 371                              <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
 372                              <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
 373                 clocks = <&topckgen CLK_TOP_ETH_SEL>,
 374                          <&topckgen CLK_TOP_F10M_REF_SEL>,
 375                          <&ethsys CLK_ETH_ESW_EN>,
 376                          <&ethsys CLK_ETH_GP0_EN>,
 377                          <&ethsys CLK_ETH_GP1_EN>,
 378                          <&ethsys CLK_ETH_GP2_EN>,
 379                          <&ethsys CLK_ETH_FE_EN>,
 380                          <&sgmiisys0 CLK_SGMII_TX_EN>,
 381                          <&sgmiisys0 CLK_SGMII_RX_EN>,
 382                          <&sgmiisys0 CLK_SGMII_CDR_REF>,
 383                          <&sgmiisys0 CLK_SGMII_CDR_FB>,
 384                          <&sgmiisys1 CLK_SGMII_TX_EN>,
 385                          <&sgmiisys1 CLK_SGMII_RX_EN>,
 386                          <&sgmiisys1 CLK_SGMII_CDR_REF>,
 387                          <&sgmiisys1 CLK_SGMII_CDR_FB>,
 388                          <&apmixedsys CLK_APMIXED_SGMIPLL>,
 389                          <&apmixedsys CLK_APMIXED_ETH2PLL>;
 390                 clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2",
 391                               "fe", "sgmii_tx250m", "sgmii_rx250m",
 392                               "sgmii_cdr_ref", "sgmii_cdr_fb",
 393                               "sgmii2_tx250m", "sgmii2_rx250m",
 394                               "sgmii2_cdr_ref", "sgmii2_cdr_fb",
 395                               "sgmii_ck", "eth2pll";
 396                 assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
 397                                   <&topckgen CLK_TOP_F10M_REF_SEL>;
 398                 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
 399                                          <&topckgen CLK_TOP_SGMIIPLL_D2>;
 400                 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
 401                 mediatek,ethsys = <&ethsys>;
 402                 mediatek,sgmiisys = <&sgmiisys0>,<&sgmiisys1>;
 403                 mediatek,infracfg = <&infracfg>;
 404                 #address-cells = <1>;
 405                 #size-cells = <0>;
 406                 status = "disabled";
 407                 };
 408
 409                 sgmiisys0: syscon@1b128000 {
 410                         compatible = "mediatek,mt7629-sgmiisys", "syscon";
 411                         reg = <0x1b128000 0x3000>;
 412                         #clock-cells = <1>;
 413                         mediatek,physpeed = "2500";
 414                 };
 415
 416                 sgmiisys1: syscon@1b130000 {
 417                         compatible = "mediatek,mt7629-sgmiisys", "syscon";
 418                         reg = <0x1b130000 0x3000>;
 419                         #clock-cells = <1>;
 420                         mediatek,physpeed = "2500";
 421                 };
 422         };
 423 };