mediatek: rewrite flow offload code
[openwrt/staging/rmilecki.git] / target / linux / generic / pending-5.4 / 770-13-net-ethernet-mtk_eth_soc-fix-parsing-packets-in-GDM.patch
1 From: Felix Fietkau <nbd@nbd.name>
2 Date: Sun, 13 Sep 2020 08:17:02 +0200
3 Subject: [PATCH] net: ethernet: mtk_eth_soc: fix parsing packets in GDM
4
5 When using DSA, set the special tag in GDM ingress control to allow the MAC
6 to parse packets properly earlier. This affects rx DMA source port reporting.
7
8 Signed-off-by: Felix Fietkau <nbd@nbd.name>
9 ---
10
11 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
12 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
13 @@ -19,6 +19,7 @@
14 #include <linux/interrupt.h>
15 #include <linux/pinctrl/devinfo.h>
16 #include <linux/phylink.h>
17 +#include <net/dsa.h>
18
19 #include "mtk_eth_soc.h"
20
21 @@ -1246,6 +1247,7 @@ static int mtk_poll_rx(struct napi_struc
22 unsigned int pktlen;
23 dma_addr_t dma_addr;
24 int mac;
25 + u16 hash;
26
27 ring = mtk_get_rx_ring(eth);
28 if (unlikely(!ring))
29 @@ -1259,13 +1261,12 @@ static int mtk_poll_rx(struct napi_struc
30 break;
31
32 /* find out which mac the packet come from. values start at 1 */
33 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
34 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) ||
35 + (trxd.rxd4 & RX_DMA_SPECIAL_TAG))
36 mac = 0;
37 - } else {
38 - mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
39 - RX_DMA_FPORT_MASK;
40 - mac--;
41 - }
42 + else
43 + mac = ((trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
44 + RX_DMA_FPORT_MASK) - 1;
45
46 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
47 !eth->netdev[mac]))
48 @@ -2247,6 +2248,9 @@ static void mtk_gdm_config(struct mtk_et
49
50 val |= config;
51
52 + if (!i && eth->netdev[0] && netdev_uses_dsa(eth->netdev[0]))
53 + val |= MTK_GDMA_SPECIAL_TAG;
54 +
55 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
56 }
57 /* Reset and enable PSE */
58 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
59 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
60 @@ -82,6 +82,7 @@
61
62 /* GDM Exgress Control Register */
63 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
64 +#define MTK_GDMA_SPECIAL_TAG BIT(24)
65 #define MTK_GDMA_ICS_EN BIT(22)
66 #define MTK_GDMA_TCS_EN BIT(21)
67 #define MTK_GDMA_UCS_EN BIT(20)
68 @@ -311,6 +312,7 @@
69 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
70 #define RX_DMA_FPORT_SHIFT 19
71 #define RX_DMA_FPORT_MASK 0x7
72 +#define RX_DMA_SPECIAL_TAG BIT(22)
73
74 /* PHY Indirect Access Control registers */
75 #define MTK_PHY_IAC 0x10004