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[openwrt/staging/rmilecki.git] / target / linux / cns3xxx / files / arch / arm / mach-cns3xxx / laguna.c
1 /*
2 * Gateworks Corporation Laguna Platform
3 *
4 * Copyright 2000 Deep Blue Solutions Ltd
5 * Copyright 2008 ARM Limited
6 * Copyright 2008 Cavium Networks
7 * Scott Shu
8 * Copyright 2010 MontaVista Software, LLC.
9 * Anton Vorontsov <avorontsov@mvista.com>
10 * Copyright 2011 Gateworks Corporation
11 * Chris Lang <clang@gateworks.com>
12 * Copyright 2012-2013 Gateworks Corporation
13 * Tim Harvey <tharvey@gateworks.com>
14 *
15 * This file is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License, Version 2, as
17 * published by the Free Software Foundation.
18 */
19
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/compiler.h>
23 #include <linux/io.h>
24 #include <linux/irq.h>
25 #include <linux/gpio.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/serial_core.h>
28 #include <linux/serial_8250.h>
29 #include <linux/platform_device.h>
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/physmap.h>
32 #include <linux/mtd/partitions.h>
33 #include <linux/leds.h>
34 #include <linux/i2c.h>
35 #include <linux/platform_data/at24.h>
36 #include <linux/platform_data/pca953x.h>
37 #include <linux/spi/spi.h>
38 #include <linux/spi/flash.h>
39 #include <linux/if_ether.h>
40 #include <linux/pps-gpio.h>
41 #include <linux/usb/ehci_pdriver.h>
42 #include <linux/usb/ohci_pdriver.h>
43 #include <linux/clk-provider.h>
44 #include <linux/clkdev.h>
45 #include <linux/platform_data/cns3xxx.h>
46 #include <asm/setup.h>
47 #include <asm/mach-types.h>
48 #include <asm/mach/arch.h>
49 #include <asm/mach/map.h>
50 #include <asm/mach/time.h>
51 #include <mach/gpio.h>
52 #include "core.h"
53 #include "devices.h"
54 #include "cns3xxx.h"
55 #include "pm.h"
56
57 #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
58
59 // Config 1 Bitmap
60 #define ETH0_LOAD BIT(0)
61 #define ETH1_LOAD BIT(1)
62 #define ETH2_LOAD BIT(2)
63 #define SATA0_LOAD BIT(3)
64 #define SATA1_LOAD BIT(4)
65 #define PCM_LOAD BIT(5)
66 #define I2S_LOAD BIT(6)
67 #define SPI0_LOAD BIT(7)
68 #define SPI1_LOAD BIT(8)
69 #define PCIE0_LOAD BIT(9)
70 #define PCIE1_LOAD BIT(10)
71 #define USB0_LOAD BIT(11)
72 #define USB1_LOAD BIT(12)
73 #define USB1_ROUTE BIT(13)
74 #define SD_LOAD BIT(14)
75 #define UART0_LOAD BIT(15)
76 #define UART1_LOAD BIT(16)
77 #define UART2_LOAD BIT(17)
78 #define MPCI0_LOAD BIT(18)
79 #define MPCI1_LOAD BIT(19)
80 #define MPCI2_LOAD BIT(20)
81 #define MPCI3_LOAD BIT(21)
82 #define FP_BUT_LOAD BIT(22)
83 #define FP_BUT_HEADER_LOAD BIT(23)
84 #define FP_LED_LOAD BIT(24)
85 #define FP_LED_HEADER_LOAD BIT(25)
86 #define FP_TAMPER_LOAD BIT(26)
87 #define HEADER_33V_LOAD BIT(27)
88 #define SATA_POWER_LOAD BIT(28)
89 #define FP_POWER_LOAD BIT(29)
90 #define GPIO_HEADER_LOAD BIT(30)
91 #define GSP_BAT_LOAD BIT(31)
92
93 // Config 2 Bitmap
94 #define FAN_LOAD BIT(0)
95 #define SPI_FLASH_LOAD BIT(1)
96 #define NOR_FLASH_LOAD BIT(2)
97 #define GPS_LOAD BIT(3)
98 #define SUPPLY_5V_LOAD BIT(6)
99 #define SUPPLY_33V_LOAD BIT(7)
100
101 struct laguna_board_info {
102 char model[16];
103 u32 config_bitmap;
104 u32 config2_bitmap;
105 u8 nor_flash_size;
106 u8 spi_flash_size;
107 };
108
109 static struct laguna_board_info laguna_info __initdata;
110
111 /*
112 * NOR Flash
113 */
114 static struct mtd_partition laguna_nor_partitions[] = {
115 {
116 .name = "uboot",
117 .size = SZ_256K,
118 .offset = 0,
119 .mask_flags = MTD_WRITEABLE,
120 }, {
121 .name = "params",
122 .size = SZ_128K,
123 .offset = SZ_256K,
124 }, {
125 .name = "kernel",
126 .size = SZ_2M,
127 .offset = SZ_256K + SZ_128K,
128 }, {
129 .name = "rootfs",
130 .size = SZ_16M - SZ_256K - SZ_128K - SZ_2M,
131 .offset = SZ_256K + SZ_128K + SZ_2M,
132 },
133 };
134
135 static struct physmap_flash_data laguna_nor_pdata = {
136 .width = 2,
137 .parts = laguna_nor_partitions,
138 .nr_parts = ARRAY_SIZE(laguna_nor_partitions),
139 };
140
141 static struct resource laguna_nor_res = {
142 .start = CNS3XXX_FLASH_BASE,
143 .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
144 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
145 };
146
147 static struct platform_device laguna_nor_pdev = {
148 .name = "physmap-flash",
149 .id = 0,
150 .resource = &laguna_nor_res,
151 .num_resources = 1,
152 .dev = {
153 .platform_data = &laguna_nor_pdata,
154 },
155 };
156
157 /*
158 * SPI
159 */
160 static struct mtd_partition laguna_spi_partitions[] = {
161 {
162 .name = "uboot",
163 .size = SZ_256K,
164 .offset = 0,
165 .mask_flags = MTD_WRITEABLE,
166 }, {
167 .name = "params",
168 .size = SZ_256K,
169 .offset = SZ_256K,
170 }, {
171 .name = "kernel",
172 .size = SZ_1M + SZ_512K,
173 .offset = SZ_512K,
174 }, {
175 .name = "rootfs",
176 .size = SZ_16M - SZ_2M,
177 .offset = SZ_2M,
178 },
179 };
180
181 static struct flash_platform_data laguna_spi_pdata = {
182 .parts = laguna_spi_partitions,
183 .nr_parts = ARRAY_SIZE(laguna_spi_partitions),
184 };
185
186 static struct spi_board_info __initdata laguna_spi_devices[] = {
187 {
188 .modalias = "m25p80",
189 .platform_data = &laguna_spi_pdata,
190 .max_speed_hz = 50000000,
191 .bus_num = 1,
192 .chip_select = 0,
193 },
194 };
195
196 static struct resource laguna_spi_resource = {
197 .start = CNS3XXX_SSP_BASE + 0x40,
198 .end = CNS3XXX_SSP_BASE + 0x6f,
199 .flags = IORESOURCE_MEM,
200 };
201
202 static struct platform_device laguna_spi_controller = {
203 .name = "cns3xxx_spi",
204 .resource = &laguna_spi_resource,
205 .num_resources = 1,
206 };
207
208 /*
209 * LED's
210 */
211 static struct gpio_led laguna_gpio_leds[] = {
212 {
213 .name = "user1", /* Green Led */
214 .gpio = 115,
215 .active_low = 1,
216 },{
217 .name = "user2", /* Red Led */
218 .gpio = 114,
219 .active_low = 1,
220 },{
221 .name = "pwr1", /* Green Led */
222 .gpio = 116,
223 .active_low = 1,
224 },{
225 .name = "pwr2", /* Yellow Led */
226 .gpio = 117,
227 .active_low = 1,
228 },{
229 .name = "txd1", /* Green Led */
230 .gpio = 118,
231 .active_low = 1,
232 },{
233 .name = "txd2", /* Yellow Led */
234 .gpio = 119,
235 .active_low = 1,
236 },{
237 .name = "rxd1", /* Green Led */
238 .gpio = 120,
239 .active_low = 1,
240 },{
241 .name = "rxd2", /* Yellow Led */
242 .gpio = 121,
243 .active_low = 1,
244 },{
245 .name = "ser1", /* Green Led */
246 .gpio = 122,
247 .active_low = 1,
248 },{
249 .name = "ser2", /* Yellow Led */
250 .gpio = 123,
251 .active_low = 1,
252 },{
253 .name = "enet1", /* Green Led */
254 .gpio = 124,
255 .active_low = 1,
256 },{
257 .name = "enet2", /* Yellow Led */
258 .gpio = 125,
259 .active_low = 1,
260 },{
261 .name = "sig1_1", /* Green Led */
262 .gpio = 126,
263 .active_low = 1,
264 },{
265 .name = "sig1_2", /* Yellow Led */
266 .gpio = 127,
267 .active_low = 1,
268 },{
269 .name = "sig2_1", /* Green Led */
270 .gpio = 128,
271 .active_low = 1,
272 },{
273 .name = "sig2_2", /* Yellow Led */
274 .gpio = 129,
275 .active_low = 1,
276 },{
277 .name = "sig3_1", /* Green Led */
278 .gpio = 130,
279 .active_low = 1,
280 },{
281 .name = "sig3_2", /* Yellow Led */
282 .gpio = 131,
283 .active_low = 1,
284 },{
285 .name = "net1", /*Green Led */
286 .gpio = 109,
287 .active_low = 1,
288 },{
289 .name = "net2", /* Red Led */
290 .gpio = 110,
291 .active_low = 1,
292 },{
293 .name = "mod1", /* Green Led */
294 .gpio = 111,
295 .active_low = 1,
296 },{
297 .name = "mod2", /* Red Led */
298 .gpio = 112,
299 .active_low = 1,
300 },
301 };
302
303 static struct gpio_led_platform_data laguna_gpio_leds_data = {
304 .num_leds = 22,
305 .leds = laguna_gpio_leds,
306 };
307
308 static struct platform_device laguna_gpio_leds_device = {
309 .name = "leds-gpio",
310 .id = -1,
311 .dev.platform_data = &laguna_gpio_leds_data,
312 };
313
314 /*
315 * Ethernet
316 */
317 static struct cns3xxx_plat_info laguna_net_data = {
318 .ports = 0,
319 .phy = {
320 0,
321 1,
322 2,
323 },
324 };
325
326 static struct resource laguna_net_resource[] = {
327 {
328 .name = "eth0_mem",
329 .start = CNS3XXX_SWITCH_BASE,
330 .end = CNS3XXX_SWITCH_BASE + SZ_4K - 1,
331 .flags = IORESOURCE_MEM
332 }, {
333 .name = "eth_rx",
334 .start = IRQ_CNS3XXX_SW_R0RXC,
335 .end = IRQ_CNS3XXX_SW_R0RXC,
336 .flags = IORESOURCE_IRQ
337 }, {
338 .name = "eth_stat",
339 .start = IRQ_CNS3XXX_SW_STATUS,
340 .end = IRQ_CNS3XXX_SW_STATUS,
341 .flags = IORESOURCE_IRQ
342 }
343 };
344
345 static u64 laguna_net_dmamask = DMA_BIT_MASK(32);
346 static struct platform_device laguna_net_device = {
347 .name = "cns3xxx_eth",
348 .id = 0,
349 .resource = laguna_net_resource,
350 .num_resources = ARRAY_SIZE(laguna_net_resource),
351 .dev = {
352 .dma_mask = &laguna_net_dmamask,
353 .coherent_dma_mask = DMA_BIT_MASK(32),
354 .platform_data = &laguna_net_data,
355 }
356 };
357
358 /*
359 * UART
360 */
361 static void __init laguna_early_serial_setup(void)
362 {
363 #ifdef CONFIG_SERIAL_8250_CONSOLE
364 static struct uart_port laguna_serial_port = {
365 .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
366 .mapbase = CNS3XXX_UART0_BASE,
367 .irq = IRQ_CNS3XXX_UART0,
368 .iotype = UPIO_MEM,
369 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
370 .regshift = 2,
371 .uartclk = 24000000,
372 .line = 0,
373 .type = PORT_16550A,
374 .fifosize = 16,
375 };
376
377 early_serial_setup(&laguna_serial_port);
378 #endif
379 }
380
381 static struct resource laguna_uart_resources[] = {
382 {
383 .start = CNS3XXX_UART0_BASE,
384 .end = CNS3XXX_UART0_BASE + SZ_4K - 1,
385 .flags = IORESOURCE_MEM
386 },{
387 .start = CNS3XXX_UART2_BASE,
388 .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
389 .flags = IORESOURCE_MEM
390 },{
391 .start = CNS3XXX_UART2_BASE,
392 .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
393 .flags = IORESOURCE_MEM
394 },
395 };
396
397 static struct plat_serial8250_port laguna_uart_data[] = {
398 {
399 .mapbase = (CNS3XXX_UART0_BASE),
400 .irq = IRQ_CNS3XXX_UART0,
401 .iotype = UPIO_MEM,
402 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
403 .regshift = 2,
404 .uartclk = 24000000,
405 .type = PORT_16550A,
406 },{
407 .mapbase = (CNS3XXX_UART1_BASE),
408 .irq = IRQ_CNS3XXX_UART1,
409 .iotype = UPIO_MEM,
410 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
411 .regshift = 2,
412 .uartclk = 24000000,
413 .type = PORT_16550A,
414 },{
415 .mapbase = (CNS3XXX_UART2_BASE),
416 .irq = IRQ_CNS3XXX_UART2,
417 .iotype = UPIO_MEM,
418 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
419 .regshift = 2,
420 .uartclk = 24000000,
421 .type = PORT_16550A,
422 },
423 { },
424 };
425
426 static struct platform_device laguna_uart = {
427 .name = "serial8250",
428 .id = PLAT8250_DEV_PLATFORM,
429 .dev.platform_data = laguna_uart_data,
430 .num_resources = 3,
431 .resource = laguna_uart_resources
432 };
433
434 /*
435 * USB
436 */
437 static struct resource cns3xxx_usb_ehci_resources[] = {
438 [0] = {
439 .start = CNS3XXX_USB_BASE,
440 .end = CNS3XXX_USB_BASE + SZ_16M - 1,
441 .flags = IORESOURCE_MEM,
442 },
443 [1] = {
444 .start = IRQ_CNS3XXX_USB_EHCI,
445 .flags = IORESOURCE_IRQ,
446 },
447 };
448
449 static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
450
451 static int csn3xxx_usb_power_on(struct platform_device *pdev)
452 {
453 /*
454 * EHCI and OHCI share the same clock and power,
455 * resetting twice would cause the 1st controller been reset.
456 * Therefore only do power up at the first up device, and
457 * power down at the last down device.
458 *
459 * Set USB AHB INCR length to 16
460 */
461 if (atomic_inc_return(&usb_pwr_ref) == 1) {
462 cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
463 cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
464 cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
465 __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
466 MISC_CHIP_CONFIG_REG);
467 }
468
469 return 0;
470 }
471
472 static void csn3xxx_usb_power_off(struct platform_device *pdev)
473 {
474 /*
475 * EHCI and OHCI share the same clock and power,
476 * resetting twice would cause the 1st controller been reset.
477 * Therefore only do power up at the first up device, and
478 * power down at the last down device.
479 */
480 if (atomic_dec_return(&usb_pwr_ref) == 0)
481 cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
482 }
483
484 static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
485 .power_on = csn3xxx_usb_power_on,
486 .power_off = csn3xxx_usb_power_off,
487 };
488
489 static struct platform_device cns3xxx_usb_ehci_device = {
490 .name = "ehci-platform",
491 .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
492 .resource = cns3xxx_usb_ehci_resources,
493 .dev = {
494 .dma_mask = &cns3xxx_usb_ehci_dma_mask,
495 .coherent_dma_mask = DMA_BIT_MASK(32),
496 .platform_data = &cns3xxx_usb_ehci_pdata,
497 },
498 };
499
500 static struct resource cns3xxx_usb_ohci_resources[] = {
501 [0] = {
502 .start = CNS3XXX_USB_OHCI_BASE,
503 .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
504 .flags = IORESOURCE_MEM,
505 },
506 [1] = {
507 .start = IRQ_CNS3XXX_USB_OHCI,
508 .flags = IORESOURCE_IRQ,
509 },
510 };
511
512 static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
513
514 static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
515 .num_ports = 1,
516 .power_on = csn3xxx_usb_power_on,
517 .power_off = csn3xxx_usb_power_off,
518 };
519
520 static struct platform_device cns3xxx_usb_ohci_device = {
521 .name = "ohci-platform",
522 .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
523 .resource = cns3xxx_usb_ohci_resources,
524 .dev = {
525 .dma_mask = &cns3xxx_usb_ohci_dma_mask,
526 .coherent_dma_mask = DMA_BIT_MASK(32),
527 .platform_data = &cns3xxx_usb_ohci_pdata,
528 },
529 };
530
531 static struct resource cns3xxx_usb_otg_resources[] = {
532 [0] = {
533 .start = CNS3XXX_USBOTG_BASE,
534 .end = CNS3XXX_USBOTG_BASE + SZ_16M - 1,
535 .flags = IORESOURCE_MEM,
536 },
537 [1] = {
538 .start = IRQ_CNS3XXX_USB_OTG,
539 .flags = IORESOURCE_IRQ,
540 },
541 };
542
543 static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32);
544
545 static struct platform_device cns3xxx_usb_otg_device = {
546 .name = "dwc2",
547 .num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources),
548 .resource = cns3xxx_usb_otg_resources,
549 .dev = {
550 .dma_mask = &cns3xxx_usb_otg_dma_mask,
551 .coherent_dma_mask = DMA_BIT_MASK(32),
552 },
553 };
554
555 /*
556 * I2C
557 */
558 static struct resource laguna_i2c_resource[] = {
559 {
560 .start = CNS3XXX_SSP_BASE + 0x20,
561 .end = CNS3XXX_SSP_BASE + 0x3f,
562 .flags = IORESOURCE_MEM,
563 },{
564 .start = IRQ_CNS3XXX_I2C,
565 .flags = IORESOURCE_IRQ,
566 },
567 };
568
569 static struct platform_device laguna_i2c_controller = {
570 .name = "cns3xxx-i2c",
571 .num_resources = 2,
572 .resource = laguna_i2c_resource,
573 };
574
575 static struct memory_accessor *at24_mem_acc;
576
577 static void at24_setup(struct memory_accessor *mem_acc, void *context)
578 {
579 char buf[16];
580
581 at24_mem_acc = mem_acc;
582
583 /* Read MAC addresses */
584 if (at24_mem_acc->read(at24_mem_acc, buf, 0x100, 6) == 6)
585 memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN);
586 if (at24_mem_acc->read(at24_mem_acc, buf, 0x106, 6) == 6)
587 memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN);
588 if (at24_mem_acc->read(at24_mem_acc, buf, 0x10C, 6) == 6)
589 memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN);
590 if (at24_mem_acc->read(at24_mem_acc, buf, 0x112, 6) == 6)
591 memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN);
592
593 /* Read out Model Information */
594 if (at24_mem_acc->read(at24_mem_acc, buf, 0x130, 16) == 16)
595 memcpy(&laguna_info.model, buf, 16);
596 if (at24_mem_acc->read(at24_mem_acc, buf, 0x140, 1) == 1)
597 memcpy(&laguna_info.nor_flash_size, buf, 1);
598 if (at24_mem_acc->read(at24_mem_acc, buf, 0x141, 1) == 1)
599 memcpy(&laguna_info.spi_flash_size, buf, 1);
600 if (at24_mem_acc->read(at24_mem_acc, buf, 0x142, 4) == 4)
601 memcpy(&laguna_info.config_bitmap, buf, 4);
602 if (at24_mem_acc->read(at24_mem_acc, buf, 0x146, 4) == 4)
603 memcpy(&laguna_info.config2_bitmap, buf, 4);
604 };
605
606 static struct at24_platform_data laguna_eeprom_info = {
607 .byte_len = 1024,
608 .page_size = 16,
609 .flags = AT24_FLAG_READONLY,
610 .setup = at24_setup,
611 };
612
613 static struct pca953x_platform_data laguna_pca_data = {
614 .gpio_base = 100,
615 .irq_base = -1,
616 };
617
618 static struct pca953x_platform_data laguna_pca2_data = {
619 .gpio_base = 116,
620 .irq_base = -1,
621 };
622
623 static struct i2c_board_info __initdata laguna_i2c_devices[] = {
624 {
625 I2C_BOARD_INFO("pca9555", 0x23),
626 .platform_data = &laguna_pca_data,
627 },{
628 I2C_BOARD_INFO("pca9555", 0x27),
629 .platform_data = &laguna_pca2_data,
630 },{
631 I2C_BOARD_INFO("gsp", 0x29),
632 },{
633 I2C_BOARD_INFO ("24c08",0x50),
634 .platform_data = &laguna_eeprom_info,
635 },{
636 I2C_BOARD_INFO("ds1672", 0x68),
637 },
638 };
639
640 /*
641 * Watchdog
642 */
643
644 static struct resource laguna_watchdog_resources[] = {
645 [0] = {
646 .start = CNS3XXX_TC11MP_TWD_BASE + 0x100, // CPU0 watchdog
647 .end = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
648 .flags = IORESOURCE_MEM,
649 },
650 };
651
652 static struct platform_device laguna_watchdog = {
653 .name = "mpcore_wdt",
654 .id = -1,
655 .num_resources = ARRAY_SIZE(laguna_watchdog_resources),
656 .resource = laguna_watchdog_resources,
657 };
658
659 /*
660 * GPS PPS
661 */
662 static struct pps_gpio_platform_data laguna_pps_data = {
663 .gpio_pin = 0,
664 .gpio_label = "GPS_PPS",
665 .assert_falling_edge = 0,
666 .capture_clear = 0,
667 };
668
669 static struct platform_device laguna_pps_device = {
670 .name = "pps-gpio",
671 .id = -1,
672 .dev.platform_data = &laguna_pps_data,
673 };
674
675 /*
676 * GPIO
677 */
678
679 static struct gpio laguna_gpio_gw2391[] = {
680 { 0, GPIOF_IN , "*GPS_PPS" },
681 { 1, GPIOF_IN , "*GSC_IRQ#" },
682 { 2, GPIOF_IN , "*USB_FAULT#" },
683 { 5, GPIOF_OUT_INIT_LOW , "*USB0_PCI_SEL" },
684 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
685 { 7, GPIOF_OUT_INIT_LOW , "*USB1_PCI_SEL" },
686 { 8, GPIOF_OUT_INIT_HIGH, "*PERST#" },
687 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN#" },
688 { 100, GPIOF_IN , "*USER_PB#" },
689 { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
690 { 108, GPIOF_IN , "DIO0" },
691 { 109, GPIOF_IN , "DIO1" },
692 { 110, GPIOF_IN , "DIO2" },
693 { 111, GPIOF_IN , "DIO3" },
694 { 112, GPIOF_IN , "DIO4" },
695 };
696
697 static struct gpio laguna_gpio_gw2388[] = {
698 { 0, GPIOF_IN , "*GPS_PPS" },
699 { 1, GPIOF_IN , "*GSC_IRQ#" },
700 { 3, GPIOF_IN , "*USB_FAULT#" },
701 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
702 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
703 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
704 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
705 { 100, GPIOF_OUT_INIT_HIGH, "*USER_PB#" },
706 { 108, GPIOF_IN , "DIO0" },
707 { 109, GPIOF_IN , "DIO1" },
708 { 110, GPIOF_IN , "DIO2" },
709 { 111, GPIOF_IN , "DIO3" },
710 { 112, GPIOF_IN , "DIO4" },
711 };
712
713 static struct gpio laguna_gpio_gw2387[] = {
714 { 0, GPIOF_IN , "*GPS_PPS" },
715 { 1, GPIOF_IN , "*GSC_IRQ#" },
716 { 2, GPIOF_IN , "*USB_FAULT#" },
717 { 5, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" },
718 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
719 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
720 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
721 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
722 { 100, GPIOF_IN , "*USER_PB#" },
723 { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
724 { 108, GPIOF_IN , "DIO0" },
725 { 109, GPIOF_IN , "DIO1" },
726 { 110, GPIOF_IN , "DIO2" },
727 { 111, GPIOF_IN , "DIO3" },
728 { 112, GPIOF_IN , "DIO4" },
729 { 113, GPIOF_IN , "DIO5" },
730 };
731
732 static struct gpio laguna_gpio_gw2386[] = {
733 { 0, GPIOF_IN , "*GPS_PPS" },
734 { 2, GPIOF_IN , "*USB_FAULT#" },
735 { 6, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" },
736 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
737 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
738 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
739 { 108, GPIOF_IN , "DIO0" },
740 { 109, GPIOF_IN , "DIO1" },
741 { 110, GPIOF_IN , "DIO2" },
742 { 111, GPIOF_IN , "DIO3" },
743 { 112, GPIOF_IN , "DIO4" },
744 { 113, GPIOF_IN , "DIO5" },
745 };
746
747 static struct gpio laguna_gpio_gw2385[] = {
748 { 0, GPIOF_IN , "*GSC_IRQ#" },
749 { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
750 { 2, GPIOF_IN , "*USB_HST_FAULT#" },
751 { 5, GPIOF_IN , "*USB_OTG_FAULT#" },
752 { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
753 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
754 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
755 { 9, GPIOF_OUT_INIT_LOW , "*SER_EN" },
756 { 10, GPIOF_IN, "*USER_PB#" },
757 { 11, GPIOF_OUT_INIT_HIGH, "*PERST#" },
758 { 100, GPIOF_IN , "*USER_PB#" },
759 { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
760 };
761
762 static struct gpio laguna_gpio_gw2384[] = {
763 { 0, GPIOF_IN , "*GSC_IRQ#" },
764 { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
765 { 2, GPIOF_IN , "*USB_HST_FAULT#" },
766 { 5, GPIOF_IN , "*USB_OTG_FAULT#" },
767 { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
768 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
769 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
770 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
771 { 12, GPIOF_OUT_INIT_LOW , "J10_DIOLED0" },
772 { 13, GPIOF_OUT_INIT_HIGH, "*I2CMUX_RST#" },
773 { 14, GPIOF_OUT_INIT_LOW , "J10_DIOLED1" },
774 { 15, GPIOF_OUT_INIT_LOW , "J10_DIOLED2" },
775 { 100, GPIOF_IN , "*USER_PB#" },
776 { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
777 { 108, GPIOF_IN , "J9_DIOGSC0" },
778 };
779
780 static struct gpio laguna_gpio_gw2383[] = {
781 { 0, GPIOF_IN , "*GPS_PPS" },
782 { 1, GPIOF_IN , "*GSC_IRQ#" },
783 { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
784 { 3, GPIOF_IN , "GPIO0" },
785 { 8, GPIOF_IN , "GPIO1" },
786 { 100, GPIOF_IN , "DIO0" },
787 { 101, GPIOF_IN , "DIO1" },
788 { 108, GPIOF_IN , "*USER_PB#" },
789 };
790
791 static struct gpio laguna_gpio_gw2382[] = {
792 { 0, GPIOF_IN , "*GPS_PPS" },
793 { 1, GPIOF_IN , "*GSC_IRQ#" },
794 { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
795 { 3, GPIOF_IN , "GPIO0" },
796 { 4, GPIOF_IN , "GPIO1" },
797 { 9, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
798 { 10, GPIOF_OUT_INIT_HIGH, "*USB_PCI_SEL#" },
799 { 100, GPIOF_IN , "DIO0" },
800 { 101, GPIOF_IN , "DIO1" },
801 { 108, GPIOF_IN , "*USER_PB#" },
802 };
803
804 static struct gpio laguna_gpio_gw2380[] = {
805 { 0, GPIOF_IN , "*GPS_PPS" },
806 { 1, GPIOF_IN , "*GSC_IRQ#" },
807 { 3, GPIOF_IN , "GPIO0" },
808 { 8, GPIOF_IN , "GPIO1" },
809 { 100, GPIOF_IN , "DIO0" },
810 { 101, GPIOF_IN , "DIO1" },
811 { 102, GPIOF_IN , "DIO2" },
812 { 103, GPIOF_IN , "DIO3" },
813 { 108, GPIOF_IN , "*USER_PB#" },
814 };
815
816 /*
817 * Initialization
818 */
819 static void __init laguna_init(void)
820 {
821 struct clk *clk;
822 u32 __iomem *reg;
823
824 clk = clk_register_fixed_rate(NULL, "cpu", NULL,
825 CLK_IS_ROOT | CLK_IGNORE_UNUSED,
826 cns3xxx_cpu_clock() * (1000000 / 8));
827 clk_register_clkdev(clk, "cpu", NULL);
828
829 platform_device_register(&laguna_watchdog);
830
831 platform_device_register(&laguna_i2c_controller);
832
833 /* Set I2C 0-3 drive strength to 21 mA */
834 reg = MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B;
835 *reg |= 0x300;
836
837 /* Enable SCL/SDA for I2C */
838 reg = MISC_GPIOB_PIN_ENABLE_REG;
839 *reg |= BIT(12) | BIT(13);
840
841 /* Enable MMC/SD pins */
842 *reg |= BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11);
843
844 cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
845 cns3xxx_pwr_power_up(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
846 cns3xxx_pwr_soft_rst(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
847
848 cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SPI_PCM_I2C));
849 cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SPI_PCM_I2C));
850
851 i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices));
852
853 pm_power_off = cns3xxx_power_off;
854 }
855
856 static struct map_desc laguna_io_desc[] __initdata = {
857 {
858 .virtual = CNS3XXX_UART0_BASE_VIRT,
859 .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
860 .length = SZ_4K,
861 .type = MT_DEVICE,
862 },
863 };
864
865 static void __init laguna_map_io(void)
866 {
867 cns3xxx_map_io();
868 iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
869 laguna_early_serial_setup();
870 }
871
872 static int laguna_register_gpio(struct gpio *array, size_t num)
873 {
874 int i, err, ret;
875
876 ret = 0;
877 for (i = 0; i < num; i++, array++) {
878 const char *label = array->label;
879 if (label[0] == '*')
880 label++;
881 err = gpio_request_one(array->gpio, array->flags, label);
882 if (err)
883 ret = err;
884 else {
885 err = gpio_export(array->gpio, array->label[0] != '*');
886 }
887 }
888 return ret;
889 }
890
891 /* allow disabling of external isolated PCIe IRQs */
892 static int cns3xxx_pciextirq = 1;
893 static int __init cns3xxx_pciextirq_disable(char *s)
894 {
895 cns3xxx_pciextirq = 0;
896 return 1;
897 }
898 __setup("noextirq", cns3xxx_pciextirq_disable);
899
900 static int __init laguna_pcie_init_irq(void)
901 {
902 u32 __iomem *mem = (void __iomem *)(CNS3XXX_GPIOB_BASE_VIRT + 0x0004);
903 u32 reg = (__raw_readl(mem) >> 26) & 0xf;
904 int irqs[] = {
905 IRQ_CNS3XXX_EXTERNAL_PIN0,
906 IRQ_CNS3XXX_EXTERNAL_PIN1,
907 IRQ_CNS3XXX_EXTERNAL_PIN2,
908 154,
909 };
910
911 if (!machine_is_gw2388())
912 return 0;
913
914 /* Verify GPIOB[26:29] == 0001b indicating support for ext irqs */
915 if (cns3xxx_pciextirq && reg != 1)
916 cns3xxx_pciextirq = 0;
917
918 if (cns3xxx_pciextirq) {
919 printk("laguna: using isolated PCI interrupts:"
920 " irq%d/irq%d/irq%d/irq%d\n",
921 irqs[0], irqs[1], irqs[2], irqs[3]);
922 cns3xxx_pcie_set_irqs(0, irqs);
923 } else {
924 printk("laguna: using shared PCI interrupts: irq%d\n",
925 IRQ_CNS3XXX_PCIE0_DEVICE);
926 }
927
928 return 0;
929 }
930 subsys_initcall(laguna_pcie_init_irq);
931
932 static int __init laguna_model_setup(void)
933 {
934 u32 __iomem *mem;
935 u32 reg;
936
937 if (!machine_is_gw2388())
938 return 0;
939
940 printk("Running on Gateworks Laguna %s\n", laguna_info.model);
941 cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
942 NR_IRQS_CNS3XXX);
943
944 /*
945 * If pcie external interrupts are supported and desired
946 * configure IRQ types and configure pin function.
947 * Note that cns3xxx_pciextirq is enabled by default, but can be
948 * unset via the 'noextirq' kernel param or by laguna_pcie_init() if
949 * the baseboard model does not support this hardware feature.
950 */
951 if (cns3xxx_pciextirq) {
952 mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0018);
953 reg = __raw_readl(mem);
954 /* GPIO26 is gpio, EXT_INT[0:2] not gpio func */
955 reg &= ~0x3c000000;
956 reg |= 0x38000000;
957 __raw_writel(reg, mem);
958
959 cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
960 IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
961
962 irq_set_irq_type(154, IRQ_TYPE_LEVEL_LOW);
963 irq_set_irq_type(93, IRQ_TYPE_LEVEL_HIGH);
964 irq_set_irq_type(94, IRQ_TYPE_LEVEL_HIGH);
965 irq_set_irq_type(95, IRQ_TYPE_LEVEL_HIGH);
966 } else {
967 cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
968 IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
969 }
970
971 if (strncmp(laguna_info.model, "GW", 2) == 0) {
972 if (laguna_info.config_bitmap & ETH0_LOAD)
973 laguna_net_data.ports |= BIT(0);
974 if (laguna_info.config_bitmap & ETH1_LOAD)
975 laguna_net_data.ports |= BIT(1);
976 if (laguna_info.config_bitmap & ETH2_LOAD)
977 laguna_net_data.ports |= BIT(2);
978 if (laguna_net_data.ports)
979 platform_device_register(&laguna_net_device);
980
981 if ((laguna_info.config_bitmap & SATA0_LOAD) ||
982 (laguna_info.config_bitmap & SATA1_LOAD))
983 cns3xxx_ahci_init();
984
985 if (laguna_info.config_bitmap & (USB0_LOAD)) {
986 cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
987
988 /* DRVVBUS pins share with GPIOA */
989 mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014);
990 reg = __raw_readl(mem);
991 reg |= 0x8;
992 __raw_writel(reg, mem);
993
994 /* Enable OTG */
995 mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808);
996 reg = __raw_readl(mem);
997 reg &= ~(1 << 10);
998 __raw_writel(reg, mem);
999
1000 platform_device_register(&cns3xxx_usb_otg_device);
1001 }
1002
1003 if (laguna_info.config_bitmap & (USB1_LOAD)) {
1004 platform_device_register(&cns3xxx_usb_ehci_device);
1005 platform_device_register(&cns3xxx_usb_ohci_device);
1006 }
1007
1008 if (laguna_info.config_bitmap & (SD_LOAD))
1009 cns3xxx_sdhci_init();
1010
1011 if (laguna_info.config_bitmap & (UART0_LOAD))
1012 laguna_uart.num_resources = 1;
1013 if (laguna_info.config_bitmap & (UART1_LOAD))
1014 laguna_uart.num_resources = 2;
1015 if (laguna_info.config_bitmap & (UART2_LOAD))
1016 laguna_uart.num_resources = 3;
1017 platform_device_register(&laguna_uart);
1018
1019 if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) {
1020 switch (laguna_info.nor_flash_size) {
1021 case 1:
1022 laguna_nor_partitions[3].size = SZ_8M - SZ_256K - SZ_128K - SZ_2M;
1023 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_8M - 1;
1024 break;
1025 case 2:
1026 laguna_nor_partitions[3].size = SZ_16M - SZ_256K - SZ_128K - SZ_2M;
1027 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_16M - 1;
1028 break;
1029 case 3:
1030 laguna_nor_partitions[3].size = SZ_32M - SZ_256K - SZ_128K - SZ_2M;
1031 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_32M - 1;
1032 break;
1033 case 4:
1034 laguna_nor_partitions[3].size = SZ_64M - SZ_256K - SZ_128K - SZ_2M;
1035 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_64M - 1;
1036 break;
1037 case 5:
1038 laguna_nor_partitions[3].size = SZ_128M - SZ_256K - SZ_128K - SZ_2M;
1039 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_128M - 1;
1040 break;
1041 }
1042 platform_device_register(&laguna_nor_pdev);
1043 }
1044
1045 if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) {
1046 switch (laguna_info.spi_flash_size) {
1047 case 1:
1048 laguna_spi_partitions[3].size = SZ_4M - SZ_2M;
1049 break;
1050 case 2:
1051 laguna_spi_partitions[3].size = SZ_8M - SZ_2M;
1052 break;
1053 case 3:
1054 laguna_spi_partitions[3].size = SZ_16M - SZ_2M;
1055 break;
1056 case 4:
1057 laguna_spi_partitions[3].size = SZ_32M - SZ_2M;
1058 break;
1059 case 5:
1060 laguna_spi_partitions[3].size = SZ_64M - SZ_2M;
1061 break;
1062 }
1063 spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices));
1064 }
1065
1066 if ((laguna_info.config_bitmap & SPI0_LOAD) ||
1067 (laguna_info.config_bitmap & SPI1_LOAD))
1068 platform_device_register(&laguna_spi_controller);
1069
1070 if (laguna_info.config2_bitmap & GPS_LOAD)
1071 platform_device_register(&laguna_pps_device);
1072
1073 /*
1074 * Do any model specific setup not known by the bitmap by matching
1075 * the first 6 characters of the model name
1076 */
1077
1078 if ( (strncmp(laguna_info.model, "GW2388", 6) == 0)
1079 || (strncmp(laguna_info.model, "GW2389", 6) == 0) )
1080 {
1081 // configure GPIO's
1082 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2388));
1083 // configure LED's
1084 laguna_gpio_leds_data.num_leds = 2;
1085 } else if (strncmp(laguna_info.model, "GW2387", 6) == 0) {
1086 // configure GPIO's
1087 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387));
1088 // configure LED's
1089 laguna_gpio_leds_data.num_leds = 2;
1090 } else if (strncmp(laguna_info.model, "GW2386", 6) == 0) {
1091 // configure GPIO's
1092 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2386));
1093 // configure LED's
1094 laguna_gpio_leds_data.num_leds = 2;
1095 } else if (strncmp(laguna_info.model, "GW2385", 6) == 0) {
1096 // configure GPIO's
1097 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2385));
1098 // configure LED's
1099 laguna_gpio_leds[0].gpio = 115;
1100 laguna_gpio_leds[1].gpio = 12;
1101 laguna_gpio_leds[1].name = "red";
1102 laguna_gpio_leds[1].active_low = 0,
1103 laguna_gpio_leds[2].gpio = 14;
1104 laguna_gpio_leds[2].name = "green";
1105 laguna_gpio_leds[2].active_low = 0,
1106 laguna_gpio_leds[3].gpio = 15;
1107 laguna_gpio_leds[3].name = "blue";
1108 laguna_gpio_leds[3].active_low = 0,
1109 laguna_gpio_leds_data.num_leds = 4;
1110 } else if ( (strncmp(laguna_info.model, "GW2384", 6) == 0)
1111 || (strncmp(laguna_info.model, "GW2394", 6) == 0) )
1112 {
1113 // configure GPIO's
1114 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384));
1115 // configure LED's
1116 laguna_gpio_leds_data.num_leds = 1;
1117 } else if (strncmp(laguna_info.model, "GW2383", 6) == 0) {
1118 // configure GPIO's
1119 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2383));
1120 // configure LED's
1121 laguna_gpio_leds[0].gpio = 107;
1122 laguna_gpio_leds_data.num_leds = 1;
1123 } else if (strncmp(laguna_info.model, "GW2382", 6) == 0) {
1124 // configure GPIO's
1125 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2382));
1126 // configure LED's
1127 laguna_gpio_leds[0].gpio = 107;
1128 laguna_gpio_leds_data.num_leds = 1;
1129 } else if (strncmp(laguna_info.model, "GW2380", 6) == 0) {
1130 // configure GPIO's
1131 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2380));
1132 // configure LED's
1133 laguna_gpio_leds[0].gpio = 107;
1134 laguna_gpio_leds[1].gpio = 106;
1135 laguna_gpio_leds_data.num_leds = 2;
1136 } else if ( (strncmp(laguna_info.model, "GW2391", 6) == 0)
1137 || (strncmp(laguna_info.model, "GW2393", 6) == 0) )
1138 {
1139 // configure GPIO's
1140 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391));
1141 // configure LED's
1142 laguna_gpio_leds_data.num_leds = 2;
1143 }
1144 platform_device_register(&laguna_gpio_leds_device);
1145 } else {
1146 // Do some defaults here, not sure what yet
1147 }
1148 return 0;
1149 }
1150 late_initcall(laguna_model_setup);
1151
1152 MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
1153 .smp = smp_ops(cns3xxx_smp_ops),
1154 .atag_offset = 0x100,
1155 .map_io = laguna_map_io,
1156 .init_irq = cns3xxx_init_irq,
1157 .init_time = cns3xxx_timer_init,
1158 .init_machine = laguna_init,
1159 .init_late = cns3xxx_pcie_init_late,
1160 .restart = cns3xxx_restart,
1161 MACHINE_END
Rafal Mileckis staging tree