target/linux/bmips/patches-5.10/200-mips-bmips-automatically-detect-CPU-frequency.patch

   1 From 0377ad93031d3e51c2afe44231241185f684b6af Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
   3 Date: Fri, 5 Mar 2021 15:14:32 +0100
   4 Subject: [PATCH 1/2] mips: bmips: automatically detect CPU frequency
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Some BCM63xx SoCs support multiple CPU frequencies depending on HW config.
  10
  11 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
  12 ---
  13  arch/mips/bmips/setup.c | 198 ++++++++++++++++++++++++++++++++++++++--
  14  1 file changed, 191 insertions(+), 7 deletions(-)
  15
  16 --- a/arch/mips/bmips/setup.c
  17 +++ b/arch/mips/bmips/setup.c
  18 @@ -31,11 +31,51 @@
  19
  20  #define RELO_NORMAL_VEC                BIT(18)
  21
  22 +#define REG_BCM6318_SOB                ((void __iomem *)CKSEG1ADDR(0x10000900))
  23 +#define BCM6318_FREQ_SHIFT     23
  24 +#define BCM6318_FREQ_MASK      (0x3 << BCM6318_FREQ_SHIFT)
  25 +
  26  #define REG_BCM6328_OTP                ((void __iomem *)CKSEG1ADDR(0x1000062c))
  27  #define BCM6328_TP1_DISABLED   BIT(9)
  28 +#define REG_BCM6328_MISC_SB    ((void __iomem *)CKSEG1ADDR(0x10001a40))
  29 +#define BCM6328_FCVO_SHIFT     7
  30 +#define BCM6328_FCVO_MASK      (0x1f << BCM6328_FCVO_SHIFT)
  31 +
  32 +#define REG_BCM6358_DDR_PLLC   ((void __iomem *)0xfffe12b8)
  33 +#define BCM6358_PLLC_M1_SHIFT  0
  34 +#define BCM6358_PLLC_M1_MASK   (0xff << BCM6358_PLLC_M1_SHIFT)
  35 +#define BCM6358_PLLC_N1_SHIFT  23
  36 +#define BCM6358_PLLC_N1_MASK   (0x3f << BCM6358_PLLC_N1_SHIFT)
  37 +#define BCM6358_PLLC_N2_SHIFT  29
  38 +#define BCM6358_PLLC_N2_MASK   (0x7 << BCM6358_PLLC_N2_SHIFT)
  39 +
  40 +#define REG_BCM6362_MISC_SB    ((void __iomem *)CKSEG1ADDR(0x10001814))
  41 +#define BCM6362_FCVO_SHIFT     1
  42 +#define BCM6362_FCVO_MASK      (0x1f << BCM6362_FCVO_SHIFT)
  43 +
  44 +#define REG_BCM6368_DDR_PLLC   ((void __iomem *)CKSEG1ADDR(0x100012a0))
  45 +#define BCM6368_PLLC_P1_SHIFT  0
  46 +#define BCM6368_PLLC_P1_MASK   (0xf << BCM6368_PLLC_P1_SHIFT)
  47 +#define BCM6368_PLLC_P2_SHIFT  4
  48 +#define BCM6368_PLLC_P2_MASK   (0xf << BCM6368_PLLC_P2_SHIFT)
  49 +#define BCM6368_PLLC_NDIV_SHIFT        16
  50 +#define BCM6368_PLLC_NDIV_MASK (0x1ff << BCM6368_PLLC_NDIV_SHIFT)
  51 +#define REG_BCM6368_DDR_PLLD   ((void __iomem *)CKSEG1ADDR(0x100012a4))
  52 +#define BCM6368_PLLD_MDIV_SHIFT        0
  53 +#define BCM6368_PLLD_MDIV_MASK (0xff << BCM6368_PLLD_MDIV_SHIFT)
  54 +
  55 +#define REG_BCM63268_MISC_SB   ((void __iomem *)CKSEG1ADDR(0x10001814))
  56 +#define BCM63268_FCVO_SHIFT    21
  57 +#define BCM63268_FCVO_MASK     (0xf << BCM63268_FCVO_SHIFT)
  58 +
  59
  60  static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
  61
  62 +struct bmips_cpufreq {
  63 +       const char              *compatible;
  64 +       u32                     (*cpu_freq)(void);
  65 +};
  66 +
  67  struct bmips_quirk {
  68         const char              *compatible;
  69         void                    (*quirk_fn)(void);
  70 @@ -138,17 +178,161 @@ const char *get_system_type(void)
  71         return "Generic BMIPS kernel";
  72  }
  73
  74 +static u32 bcm6318_cpufreq(void)
  75 +{
  76 +       u32 val = __raw_readl(REG_BCM6318_SOB);
  77 +
  78 +       switch ((val & BCM6318_FREQ_MASK) >> BCM6318_FREQ_SHIFT) {
  79 +       case 0:
  80 +               return 166000000;
  81 +       case 2:
  82 +               return 250000000;
  83 +       case 3:
  84 +               return 333000000;
  85 +       case 1:
  86 +               return 400000000;
  87 +       default:
  88 +               return 0;
  89 +       }
  90 +}
  91 +
  92 +static u32 bcm6328_cpufreq(void)
  93 +{
  94 +       u32 val = __raw_readl(REG_BCM6328_MISC_SB);
  95 +
  96 +       switch ((val & BCM6328_FCVO_MASK) >> BCM6328_FCVO_SHIFT) {
  97 +       case 0x12:
  98 +       case 0x14:
  99 +       case 0x19:
 100 +               return 160000000;
 101 +       case 0x1c:
 102 +               return 192000000;
 103 +       case 0x13:
 104 +       case 0x15:
 105 +               return 200000000;
 106 +       case 0x1a:
 107 +               return 384000000;
 108 +       case 0x16:
 109 +               return 400000000;
 110 +       default:
 111 +               return 320000000;
 112 +       }
 113 +}
 114 +
 115 +static u32 bcm6358_cpufreq(void)
 116 +{
 117 +       u32 val, n1, n2, m1;
 118 +
 119 +       val = __raw_readl(REG_BCM6358_DDR_PLLC);
 120 +       n1 = (val & BCM6358_PLLC_N1_MASK) >> BCM6358_PLLC_N1_SHIFT;
 121 +       n2 = (val & BCM6358_PLLC_N2_MASK) >> BCM6358_PLLC_N2_SHIFT;
 122 +       m1 = (val & BCM6358_PLLC_M1_MASK) >> BCM6358_PLLC_M1_SHIFT;
 123 +
 124 +       return (16 * 1000000 * n1 * n2) / m1;
 125 +}
 126 +
 127 +static u32 bcm6362_cpufreq(void)
 128 +{
 129 +       u32 val = __raw_readl(REG_BCM6362_MISC_SB);
 130 +
 131 +       switch ((val & BCM6362_FCVO_MASK) >> BCM6362_FCVO_SHIFT) {
 132 +       case 0x04:
 133 +       case 0x0c:
 134 +       case 0x14:
 135 +       case 0x1c:
 136 +               return 160000000;
 137 +       case 0x15:
 138 +       case 0x1d:
 139 +               return 200000000;
 140 +       case 0x03:
 141 +       case 0x0b:
 142 +       case 0x13:
 143 +       case 0x1b:
 144 +               return 240000000;
 145 +       case 0x07:
 146 +       case 0x17:
 147 +               return 384000000;
 148 +       case 0x05:
 149 +       case 0x0e:
 150 +       case 0x16:
 151 +       case 0x1e:
 152 +       case 0x1f:
 153 +               return 400000000;
 154 +       case 0x06:
 155 +               return 440000000;
 156 +       default:
 157 +               return 320000000;
 158 +       }
 159 +}
 160 +
 161 +static u32 bcm6368_cpufreq(void)
 162 +{
 163 +       u32 val, p1, p2, ndiv, m1;
 164 +
 165 +       val = __raw_readl(REG_BCM6368_DDR_PLLC);
 166 +       p1 = (val & BCM6368_PLLC_P1_MASK) >> BCM6368_PLLC_P1_SHIFT;
 167 +       p2 = (val & BCM6368_PLLC_P2_MASK) >> BCM6368_PLLC_P2_SHIFT;
 168 +       ndiv = (val & BCM6368_PLLC_NDIV_MASK) >>
 169 +              BCM6368_PLLC_NDIV_SHIFT;
 170 +
 171 +       val = __raw_readl(REG_BCM6368_DDR_PLLD);
 172 +       m1 = (val & BCM6368_PLLD_MDIV_MASK) >> BCM6368_PLLD_MDIV_SHIFT;
 173 +
 174 +       return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
 175 +}
 176 +
 177 +static u32 bcm63268_cpufreq(void)
 178 +{
 179 +       u32 val = __raw_readl(REG_BCM63268_MISC_SB);
 180 +
 181 +       switch ((val & BCM63268_FCVO_MASK) >> BCM63268_FCVO_SHIFT) {
 182 +       case 0x3:
 183 +       case 0xe:
 184 +               return 320000000;
 185 +       case 0xa:
 186 +               return 333000000;
 187 +       case 0x2:
 188 +       case 0xb:
 189 +       case 0xf:
 190 +               return 400000000;
 191 +       default:
 192 +               return 0;
 193 +       }
 194 +}
 195 +
 196 +static const struct bmips_cpufreq bmips_cpufreq_list[] = {
 197 +       { "brcm,bcm6318", &bcm6318_cpufreq },
 198 +       { "brcm,bcm6328", &bcm6328_cpufreq },
 199 +       { "brcm,bcm6358", &bcm6358_cpufreq },
 200 +       { "brcm,bcm6362", &bcm6362_cpufreq },
 201 +       { "brcm,bcm6368", &bcm6368_cpufreq },
 202 +       { "brcm,bcm63268", &bcm63268_cpufreq },
 203 +       { /* sentinel */ }
 204 +};
 205 +
 206  void __init plat_time_init(void)
 207  {
 208 +       const struct bmips_cpufreq *cf;
 209         struct device_node *np;
 210 -       u32 freq;
 211 +       u32 freq = 0;
 212
 213 -       np = of_find_node_by_name(NULL, "cpus");
 214 -       if (!np)
 215 -               panic("missing 'cpus' DT node");
 216 -       if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
 217 -               panic("missing 'mips-hpt-frequency' property");
 218 -       of_node_put(np);
 219 +       for (cf = bmips_cpufreq_list; cf->cpu_freq; cf++) {
 220 +               if (of_flat_dt_is_compatible(of_get_flat_dt_root(),
 221 +                                            cf->compatible)) {
 222 +                       freq = cf->cpu_freq() / 2;
 223 +                       printk("%s detected @ %u MHz\n", cf->compatible, freq / 500000);
 224 +                       break;
 225 +               }
 226 +       }
 227 +
 228 +       if (!freq) {
 229 +               np = of_find_node_by_name(NULL, "cpus");
 230 +               if (!np)
 231 +                       panic("missing 'cpus' DT node");
 232 +               if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
 233 +                       panic("missing 'mips-hpt-frequency' property");
 234 +               of_node_put(np);
 235 +       }
 236
 237         mips_hpt_frequency = freq;
 238  }