package/kernel/mac80211/patches/652-0045-rtl8xxxu-Implement-rtl8188eu_config_channel.patch

   1 From b3ce6298eb09b26c5abbc5dca8c8dfa18f41ea12 Mon Sep 17 00:00:00 2001
   2 From: Jes Sorensen <Jes.Sorensen@redhat.com>
   3 Date: Thu, 18 Aug 2016 12:20:31 -0400
   4 Subject: [PATCH] rtl8xxxu: Implement rtl8188eu_config_channel()
   5
   6 The 8188eu doesn't seem to have REG_FPGA0_ANALOG2
   7
   8 Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
   9 ---
  10  .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c | 118 ++++++++++++++++++++-
  11  1 file changed, 117 insertions(+), 1 deletion(-)
  12
  13 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
  14 +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
  15 @@ -345,6 +345,122 @@ rtl8188e_set_tx_power(struct rtl8xxxu_pr
  16         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs);
  17  }
  18
  19 +void rtl8188eu_config_channel(struct ieee80211_hw *hw)
  20 +{
  21 +       struct rtl8xxxu_priv *priv = hw->priv;
  22 +       u32 val32, rsr;
  23 +       u8 val8, opmode;
  24 +       bool ht = true;
  25 +       int sec_ch_above, channel;
  26 +       int i;
  27 +
  28 +       opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
  29 +       rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
  30 +       channel = hw->conf.chandef.chan->hw_value;
  31 +
  32 +       switch (hw->conf.chandef.width) {
  33 +       case NL80211_CHAN_WIDTH_20_NOHT:
  34 +               ht = false;
  35 +       case NL80211_CHAN_WIDTH_20:
  36 +               opmode |= BW_OPMODE_20MHZ;
  37 +               rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
  38 +
  39 +               val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
  40 +               val32 &= ~FPGA_RF_MODE;
  41 +               rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
  42 +
  43 +               val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
  44 +               val32 &= ~FPGA_RF_MODE;
  45 +               rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
  46 +               break;
  47 +       case NL80211_CHAN_WIDTH_40:
  48 +               if (hw->conf.chandef.center_freq1 >
  49 +                   hw->conf.chandef.chan->center_freq) {
  50 +                       sec_ch_above = 1;
  51 +                       channel += 2;
  52 +               } else {
  53 +                       sec_ch_above = 0;
  54 +                       channel -= 2;
  55 +               }
  56 +
  57 +               opmode &= ~BW_OPMODE_20MHZ;
  58 +               rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
  59 +               rsr &= ~RSR_RSC_BANDWIDTH_40M;
  60 +               if (sec_ch_above)
  61 +                       rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
  62 +               else
  63 +                       rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
  64 +               rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
  65 +
  66 +               val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
  67 +               val32 |= FPGA_RF_MODE;
  68 +               rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
  69 +
  70 +               val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
  71 +               val32 |= FPGA_RF_MODE;
  72 +               rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
  73 +
  74 +               /*
  75 +                * Set Control channel to upper or lower. These settings
  76 +                * are required only for 40MHz
  77 +                */
  78 +               val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
  79 +               val32 &= ~CCK0_SIDEBAND;
  80 +               if (!sec_ch_above)
  81 +                       val32 |= CCK0_SIDEBAND;
  82 +               rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
  83 +
  84 +               val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
  85 +               val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
  86 +               if (sec_ch_above)
  87 +                       val32 |= OFDM_LSTF_PRIME_CH_LOW;
  88 +               else
  89 +                       val32 |= OFDM_LSTF_PRIME_CH_HIGH;
  90 +               rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
  91 +
  92 +               val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
  93 +               val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
  94 +               if (sec_ch_above)
  95 +                       val32 |= FPGA0_PS_UPPER_CHANNEL;
  96 +               else
  97 +                       val32 |= FPGA0_PS_LOWER_CHANNEL;
  98 +               rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
  99 +               break;
 100 +
 101 +       default:
 102 +               break;
 103 +       }
 104 +
 105 +       for (i = RF_A; i < priv->rf_paths; i++) {
 106 +               val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
 107 +               val32 &= ~MODE_AG_CHANNEL_MASK;
 108 +               val32 |= channel;
 109 +               rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
 110 +       }
 111 +
 112 +       if (ht)
 113 +               val8 = 0x0e;
 114 +       else
 115 +               val8 = 0x0a;
 116 +
 117 +#if 0
 118 +       rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
 119 +       rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
 120 +
 121 +       rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
 122 +       rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
 123 +#endif
 124 +
 125 +       for (i = RF_A; i < priv->rf_paths; i++) {
 126 +               val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
 127 +               if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
 128 +                       val32 &= ~MODE_AG_CHANNEL_20MHZ;
 129 +               else
 130 +                       val32 |= MODE_AG_CHANNEL_20MHZ;
 131 +               rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
 132 +       }
 133 +}
 134 +
 135  void rtl8188eu_init_aggregation(struct rtl8xxxu_priv *priv)
 136  {
 137         u8 agg_ctrl, usb_spec;
 138 @@ -1118,7 +1234,7 @@ struct rtl8xxxu_fileops rtl8188eu_fops =
 139         .init_phy_bb = rtl8188eu_init_phy_bb,
 140         .init_phy_rf = rtl8188eu_init_phy_rf,
 141         .phy_iq_calibrate = rtl8188eu_phy_iq_calibrate,
 142 -       .config_channel = rtl8xxxu_gen1_config_channel,
 143 +       .config_channel = rtl8188eu_config_channel,
 144         .parse_rx_desc = rtl8xxxu_parse_rxdesc16,
 145         .init_aggregation = rtl8188eu_init_aggregation,
 146         .enable_rf = rtl8188e_enable_rf,