package/kernel/mac80211/patches/652-0038-rtl8xxxu-Add-some-8188eu-registers-and-update-CCK0_A.patch

   1 From cbbf4d6e0a8d8230aff7c4088cf1ed593e6002dd Mon Sep 17 00:00:00 2001
   2 From: Jes Sorensen <Jes.Sorensen@redhat.com>
   3 Date: Fri, 29 Jul 2016 15:25:34 -0400
   4 Subject: [PATCH] rtl8xxxu: Add some 8188eu registers and update
   5  CCK0_AFE_SETTING bit defines
   6
   7 CCK0_AFE_SETTING is particular, it has the notion of primary RX antenna
   8 and optional RX antenna. When configuring RX for single antenna, setup
   9 should use the same antenna for default and optional. For AB setup,
  10 use antenna A as default and B as optional.
  11
  12 Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
  13 ---
  14  .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h  | 24 ++++++++++++++++++++--
  15  1 file changed, 22 insertions(+), 2 deletions(-)
  16
  17 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
  18 +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
  19 @@ -938,6 +938,7 @@
  20  #define REG_FPGA1_RF_MODE              0x0900
  21
  22  #define REG_FPGA1_TX_INFO              0x090c
  23 +#define REG_ANT_MAPPING1               0x0914
  24  #define REG_DPDT_CTRL                  0x092c  /* 8723BU */
  25  #define REG_RFE_CTRL_ANTA_SRC          0x0930  /* 8723BU */
  26  #define REG_RFE_PATH_SELECT            0x0940  /* 8723BU */
  27 @@ -949,9 +950,25 @@
  28
  29  #define REG_CCK0_AFE_SETTING           0x0a04
  30  #define  CCK0_AFE_RX_MASK              0x0f000000
  31 -#define  CCK0_AFE_RX_ANT_AB            BIT(24)
  32 +#define  CCK0_AFE_TX_MASK              0xf0000000
  33  #define  CCK0_AFE_RX_ANT_A             0
  34 -#define  CCK0_AFE_RX_ANT_B             (BIT(24) | BIT(26))
  35 +#define  CCK0_AFE_RX_ANT_B             BIT(26)
  36 +#define  CCK0_AFE_RX_ANT_C             BIT(27)
  37 +#define  CCK0_AFE_RX_ANT_D             (BIT(26) | BIT(27))
  38 +#define  CCK0_AFE_RX_ANT_OPTION_A      0
  39 +#define  CCK0_AFE_RX_ANT_OPTION_B      BIT(24)
  40 +#define  CCK0_AFE_RX_ANT_OPTION_C      BIT(25)
  41 +#define  CCK0_AFE_RX_ANT_OPTION_D      (BIT(24) | BIT(25))
  42 +#define  CCK0_AFE_TX_ANT_A             BIT(31)
  43 +#define  CCK0_AFE_TX_ANT_B             BIT(30)
  44 +
  45 +#define REG_CCK_ANTDIV_PARA2           0x0a04
  46 +#define REG_BB_POWER_SAVE4             0x0a74
  47 +
  48 +/* 8188eu */
  49 +#define REG_LNA_SWITCH                 0x0b2c
  50 +#define  LNA_SWITCH_DISABLE_CSCG       BIT(22)
  51 +#define  LNA_SWITCH_OUTPUT_CG          BIT(31)
  52
  53  #define REG_CONFIG_ANT_A               0x0b68
  54  #define REG_CONFIG_ANT_B               0x0b6c
  55 @@ -1004,6 +1021,9 @@
  56
  57  #define REG_OFDM0_RX_IQ_EXT_ANTA       0x0ca0
  58
  59 +/* 8188eu */
  60 +#define REG_ANTDIV_PARA1               0x0ca4
  61 +
  62  /* 8723bu */
  63  #define REG_OFDM0_TX_PSDO_NOISE_WEIGHT 0x0ce4
  64