package/kernel/mac80211/patches/652-0036-rtl8xxxu-Implement-rtl8188e_set_tx_power.patch

   1 From cf02f3fe981c1f11a41cf885d7c5a0298378b0d6 Mon Sep 17 00:00:00 2001
   2 From: Jes Sorensen <Jes.Sorensen@redhat.com>
   3 Date: Fri, 22 Jul 2016 16:50:59 -0400
   4 Subject: [PATCH] rtl8xxxu: Implement rtl8188e_set_tx_power()
   5
   6 This matches the code used to set TX power on 8192eu, except it only
   7 handles path A.
   8
   9 We should be able to consolidate this code.
  10
  11 Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
  12 ---
  13  .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c | 57 ++++++++++++++++++++++
  14  1 file changed, 57 insertions(+)
  15
  16 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
  17 +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
  18 @@ -283,9 +283,66 @@ static struct rtl8xxxu_rfregval rtl8188e
  19         {0xff, 0xffffffff}
  20  };
  21
  22 +int rtl8xxxu_8188e_channel_to_group(int channel)
  23 +{
  24 +       int group;
  25 +
  26 +       if (channel < 3)
  27 +               group = 0;
  28 +       else if (channel < 6)
  29 +               group = 1;
  30 +       else if (channel < 9)
  31 +               group = 2;
  32 +       else if (channel < 12)
  33 +               group = 3;
  34 +       else if (channel < 14)
  35 +               group = 4;
  36 +       else
  37 +               group = 5;
  38 +
  39 +       return group;
  40 +}
  41 +
  42  static void
  43  rtl8188e_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
  44  {
  45 +       u32 val32, ofdm, mcs;
  46 +       u8 cck, ofdmbase, mcsbase;
  47 +       int group, tx_idx;
  48 +
  49 +       tx_idx = 0;
  50 +       group = rtl8xxxu_8188e_channel_to_group(channel);
  51 +
  52 +       cck = priv->cck_tx_power_index_A[group];
  53 +
  54 +       val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
  55 +       val32 &= 0xffff00ff;
  56 +       val32 |= (cck << 8);
  57 +       rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
  58 +
  59 +       val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
  60 +       val32 &= 0xff;
  61 +       val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
  62 +       rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
  63 +
  64 +       ofdmbase = priv->ht40_1s_tx_power_index_A[group];
  65 +       ofdmbase += priv->ofdm_tx_power_diff[tx_idx].a;
  66 +       ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
  67 +
  68 +       rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
  69 +       rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
  70 +
  71 +       mcsbase = priv->ht40_1s_tx_power_index_A[group];
  72 +       if (ht40)
  73 +               mcsbase += priv->ht40_tx_power_diff[tx_idx++].a;
  74 +       else
  75 +               mcsbase += priv->ht20_tx_power_diff[tx_idx++].a;
  76 +       mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
  77 +
  78 +       rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
  79 +       rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
  80 +       rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs);
  81 +       rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs);
  82  }
  83
  84  static int rtl8188eu_parse_efuse(struct rtl8xxxu_priv *priv)