package/kernel/mac80211/patches/651-0011-rtl8xxxu-Add-interrupt-bit-definitions-for-gen2-part.patch

   1 From b11b4053e28ebcd35fca0b81448ee91ef88a6fed Mon Sep 17 00:00:00 2001
   2 From: Jes Sorensen <Jes.Sorensen@redhat.com>
   3 Date: Wed, 20 Jul 2016 16:52:13 -0400
   4 Subject: [PATCH] rtl8xxxu: Add interrupt bit definitions for gen2 parts
   5
   6 These are primarily needed for SDIO/PCI parts, but the vendor driver
   7 still sets them for some USB devices.
   8
   9 Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
  10 ---
  11  .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h  | 56 ++++++++++++++++++++++
  12  1 file changed, 56 insertions(+)
  13
  14 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
  15 +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
  16 @@ -213,10 +213,66 @@
  17  #define REG_HMBOX_EXT_1                        0x008a
  18  #define REG_HMBOX_EXT_2                        0x008c
  19  #define REG_HMBOX_EXT_3                        0x008e
  20 +
  21  /* Interrupt registers for 8192e/8723bu/8812 */
  22  #define REG_HIMR0                      0x00b0
  23 +#define         IMR0_TXCCK                     BIT(30) /* TXRPT interrupt when CCX bit
  24 +                                                  of the packet is set */
  25 +#define         IMR0_PSTIMEOUT                 BIT(29) /* Power Save Time Out Int */
  26 +#define         IMR0_GTINT4                    BIT(28) /* Set when GTIMER4 expires */
  27 +#define         IMR0_GTINT3                    BIT(27) /* Set when GTIMER3 expires */
  28 +#define         IMR0_TBDER                     BIT(26) /* Transmit Beacon0 Error */
  29 +#define         IMR0_TBDOK                     BIT(25) /* Transmit Beacon0 OK */
  30 +#define         IMR0_TSF_BIT32_TOGGLE          BIT(24) /* TSF Timer BIT32 toggle
  31 +                                                  indication interrupt */
  32 +#define         IMR0_BCNDMAINT0                BIT(20) /* Beacon DMA Interrupt 0 */
  33 +#define         IMR0_BCNDERR0                  BIT(16) /* Beacon Queue DMA Error 0 */
  34 +#define         IMR0_HSISR_IND_ON_INT          BIT(15) /* HSISR Indicator (HSIMR &
  35 +                                                  HSISR is true) */
  36 +#define         IMR0_BCNDMAINT_E               BIT(14) /* Beacon DMA Interrupt
  37 +                                                  Extension for Win7 */
  38 +#define         IMR0_ATIMEND                   BIT(12) /* CTWidnow End or
  39 +                                                  ATIM Window End */
  40 +#define         IMR0_HISR1_IND_INT             BIT(11) /* HISR1 Indicator
  41 +                                                  (HISR1 & HIMR1 is true) */
  42 +#define         IMR0_C2HCMD                    BIT(10) /* CPU to Host Command INT
  43 +                                                  Status, Write 1 to clear */
  44 +#define         IMR0_CPWM2                     BIT(9)  /* CPU power Mode exchange INT
  45 +                                                  Status, Write 1 to clear */
  46 +#define         IMR0_CPWM                      BIT(8)  /* CPU power Mode exchange INT
  47 +                                                  Status, Write 1 to clear */
  48 +#define         IMR0_HIGHDOK                   BIT(7)  /* High Queue DMA OK */
  49 +#define         IMR0_MGNTDOK                   BIT(6)  /* Management Queue DMA OK */
  50 +#define         IMR0_BKDOK                     BIT(5)  /* AC_BK DMA OK */
  51 +#define         IMR0_BEDOK                     BIT(4)  /* AC_BE DMA OK */
  52 +#define         IMR0_VIDOK                     BIT(3)  /* AC_VI DMA OK */
  53 +#define         IMR0_VODOK                     BIT(2)  /* AC_VO DMA OK */
  54 +#define         IMR0_RDU                       BIT(1)  /* Rx Descriptor Unavailable */
  55 +#define         IMR0_ROK                       BIT(0)  /* Receive DMA OK */
  56  #define REG_HISR0                      0x00b4
  57  #define REG_HIMR1                      0x00b8
  58 +#define         IMR1_BCNDMAINT7                BIT(27) /* Beacon DMA Interrupt 7 */
  59 +#define         IMR1_BCNDMAINT6                BIT(26) /* Beacon DMA Interrupt 6 */
  60 +#define         IMR1_BCNDMAINT5                BIT(25) /* Beacon DMA Interrupt 5 */
  61 +#define         IMR1_BCNDMAINT4                BIT(24) /* Beacon DMA Interrupt 4 */
  62 +#define         IMR1_BCNDMAINT3                BIT(23) /* Beacon DMA Interrupt 3 */
  63 +#define         IMR1_BCNDMAINT2                BIT(22) /* Beacon DMA Interrupt 2 */
  64 +#define         IMR1_BCNDMAINT1                BIT(21) /* Beacon DMA Interrupt 1 */
  65 +#define         IMR1_BCNDERR7                  BIT(20) /* Beacon Queue DMA Err Int 7 */
  66 +#define         IMR1_BCNDERR6                  BIT(19) /* Beacon Queue DMA Err Int 6 */
  67 +#define         IMR1_BCNDERR5                  BIT(18) /* Beacon Queue DMA Err Int 5 */
  68 +#define         IMR1_BCNDERR4                  BIT(17) /* Beacon Queue DMA Err Int 4 */
  69 +#define         IMR1_BCNDERR3                  BIT(16) /* Beacon Queue DMA Err Int 3 */
  70 +#define         IMR1_BCNDERR2                  BIT(15) /* Beacon Queue DMA Err Int 2 */
  71 +#define         IMR1_BCNDERR1                  BIT(14) /* Beacon Queue DMA Err Int 1 */
  72 +#define         IMR1_ATIMEND_E                 BIT(13) /* ATIM Window End Extension
  73 +                                                  for Win7 */
  74 +#define         IMR1_TXERR                     BIT(11) /* Tx Error Flag Int Status,
  75 +                                                  write 1 to clear */
  76 +#define         IMR1_RXERR                     BIT(10) /* Rx Error Flag Int Status,
  77 +                                                  write 1 to clear */
  78 +#define         IMR1_TXFOVW                    BIT(9)  /* Transmit FIFO Overflow */
  79 +#define         IMR1_RXFOVW                    BIT(8)  /* Receive FIFO Overflow */
  80  #define REG_HISR1                      0x00bc
  81
  82  /*  Host suspend counter on FPGA platform */