target/linux/sifiveu/patches-6.1/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch

   1 From d3cf2859a056273400fbdf9d389b75750ff6ca5e Mon Sep 17 00:00:00 2001
   2 From: David Abdurachmanov <david.abdurachmanov@sifive.com>
   3 Date: Fri, 14 May 2021 05:27:51 -0700
   4 Subject: [PATCH 6/7] riscv: sifive: unleashed: define opp table (cpufreq)
   5
   6 Source: https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4
   7
   8 Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
   9 ---
  10  arch/riscv/Kconfig                                 |  8 +++++
  11  arch/riscv/boot/dts/sifive/fu540-c000.dtsi         |  5 ++++
  12  .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 34 ++++++++++++++++++++++
  13  3 files changed, 47 insertions(+)
  14
  15 --- a/arch/riscv/Kconfig
  16 +++ b/arch/riscv/Kconfig
  17 @@ -711,6 +711,14 @@ config PORTABLE
  18         select OF
  19         select MMU
  20
  21 +menu "CPU Power Management"
  22 +
  23 +source "drivers/cpuidle/Kconfig"
  24 +
  25 +source "drivers/cpufreq/Kconfig"
  26 +
  27 +endmenu
  28 +
  29  menu "Power management options"
  30
  31  source "kernel/power/Kconfig"
  32 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
  33 +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
  34 @@ -30,6 +30,7 @@
  35                         i-cache-size = <16384>;
  36                         reg = <0>;
  37                         riscv,isa = "rv64imac";
  38 +                       clocks = <&prci FU540_PRCI_CLK_COREPLL>;
  39                         status = "disabled";
  40                         cpu0_intc: interrupt-controller {
  41                                 #interrupt-cells = <1>;
  42 @@ -54,6 +55,7 @@
  43                         reg = <1>;
  44                         riscv,isa = "rv64imafdc";
  45                         tlb-split;
  46 +                       clocks = <&prci FU540_PRCI_CLK_COREPLL>;
  47                         next-level-cache = <&l2cache>;
  48                         cpu1_intc: interrupt-controller {
  49                                 #interrupt-cells = <1>;
  50 @@ -78,6 +80,7 @@
  51                         reg = <2>;
  52                         riscv,isa = "rv64imafdc";
  53                         tlb-split;
  54 +                       clocks = <&prci FU540_PRCI_CLK_COREPLL>;
  55                         next-level-cache = <&l2cache>;
  56                         cpu2_intc: interrupt-controller {
  57                                 #interrupt-cells = <1>;
  58 @@ -102,6 +105,7 @@
  59                         reg = <3>;
  60                         riscv,isa = "rv64imafdc";
  61                         tlb-split;
  62 +                       clocks = <&prci FU540_PRCI_CLK_COREPLL>;
  63                         next-level-cache = <&l2cache>;
  64                         cpu3_intc: interrupt-controller {
  65                                 #interrupt-cells = <1>;
  66 @@ -126,6 +130,7 @@
  67                         reg = <4>;
  68                         riscv,isa = "rv64imafdc";
  69                         tlb-split;
  70 +                       clocks = <&prci FU540_PRCI_CLK_COREPLL>;
  71                         next-level-cache = <&l2cache>;
  72                         cpu4_intc: interrupt-controller {
  73                                 #interrupt-cells = <1>;
  74 --- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
  75 +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
  76 @@ -80,6 +80,40 @@
  77                         label = "d4";
  78                 };
  79         };
  80 +
  81 +       fu540_c000_opp_table: opp-table {
  82 +               compatible = "operating-points-v2";
  83 +               opp-shared;
  84 +
  85 +               opp-350000000 {
  86 +                       opp-hz = /bits/ 64 <350000000>;
  87 +               };
  88 +               opp-700000000 {
  89 +                       opp-hz = /bits/ 64 <700000000>;
  90 +               };
  91 +               opp-999999999 {
  92 +                       opp-hz = /bits/ 64 <999999999>;
  93 +               };
  94 +               opp-1400000000 {
  95 +                       opp-hz = /bits/ 64 <1400000000>;
  96 +               };
  97 +       };
  98 +};
  99 +
 100 +&cpu0 {
 101 +       operating-points-v2 = <&fu540_c000_opp_table>;
 102 +};
 103 +&cpu1 {
 104 +       operating-points-v2 = <&fu540_c000_opp_table>;
 105 +};
 106 +&cpu2 {
 107 +       operating-points-v2 = <&fu540_c000_opp_table>;
 108 +};
 109 +&cpu3 {
 110 +       operating-points-v2 = <&fu540_c000_opp_table>;
 111 +};
 112 +&cpu4 {
 113 +       operating-points-v2 = <&fu540_c000_opp_table>;
 114  };
 115
 116  &uart0 {