target/linux/sifiveu/patches-6.1/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch

   1 From ab5c8f5492cce16ff2104393e2f1fa64a3ff6e88 Mon Sep 17 00:00:00 2001
   2 From: David Abdurachmanov <david.abdurachmanov@sifive.com>
   3 Date: Wed, 17 Feb 2021 06:06:14 -0800
   4 Subject: [PATCH 1/7] riscv: sifive: fu740: cpu{1,2,3,4} set compatible to
   5  sifive,u74-mc
   6
   7 Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
   8 ---
   9  arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 8 ++++----
  10  1 file changed, 4 insertions(+), 4 deletions(-)
  11
  12 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
  13 +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
  14 @@ -39,7 +39,7 @@
  15                         };
  16                 };
  17                 cpu1: cpu@1 {
  18 -                       compatible = "sifive,bullet0", "riscv";
  19 +                       compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
  20                         d-cache-block-size = <64>;
  21                         d-cache-sets = <64>;
  22                         d-cache-size = <32768>;
  23 @@ -63,7 +63,7 @@
  24                         };
  25                 };
  26                 cpu2: cpu@2 {
  27 -                       compatible = "sifive,bullet0", "riscv";
  28 +                       compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
  29                         d-cache-block-size = <64>;
  30                         d-cache-sets = <64>;
  31                         d-cache-size = <32768>;
  32 @@ -87,7 +87,7 @@
  33                         };
  34                 };
  35                 cpu3: cpu@3 {
  36 -                       compatible = "sifive,bullet0", "riscv";
  37 +                       compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
  38                         d-cache-block-size = <64>;
  39                         d-cache-sets = <64>;
  40                         d-cache-size = <32768>;
  41 @@ -111,7 +111,7 @@
  42                         };
  43                 };
  44                 cpu4: cpu@4 {
  45 -                       compatible = "sifive,bullet0", "riscv";
  46 +                       compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
  47                         d-cache-block-size = <64>;
  48                         d-cache-sets = <64>;
  49                         d-cache-size = <32768>;