pistachio: default to kernel 6.1
[openwrt/staging/pepe2k.git] / target / linux / pistachio / patches-5.15 / 903-MIPS-DTS-img-marduk-Add-NXP-SC16IS752IPW.patch
1 From ad4eba0c36ce8af6ab9ea1bc163e4c1ac7c271c3 Mon Sep 17 00:00:00 2001
2 From: Hauke Mehrtens <hauke@hauke-m.de>
3 Date: Sat, 15 Aug 2020 16:09:02 +0200
4 Subject: [PATCH 903/904] MIPS: DTS: img: marduk: Add NXP SC16IS752IPW
5
6 Add NXP SC16IS752IPW SPI-UART controller to device tree.
7
8 This controller drives 2 UARTs and 7 LEDs on the board.
9
10 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
11 ---
12 arch/mips/boot/dts/img/pistachio_marduk.dts | 51 +++++++++++++++++++++
13 1 file changed, 51 insertions(+)
14
15 --- a/arch/mips/boot/dts/img/pistachio_marduk.dts
16 +++ b/arch/mips/boot/dts/img/pistachio_marduk.dts
17 @@ -46,6 +46,46 @@
18 regulator-max-microvolt = <1800000>;
19 };
20
21 + /* EXT clock from ca8210 is fed to sc16is752 */
22 + ca8210_ext_clk: ca8210-ext-clk {
23 + compatible = "fixed-clock";
24 + #clock-cells = <0>;
25 + clock-frequency = <16000000>;
26 + clock-output-names = "ca8210_ext_clock";
27 + };
28 +
29 + gpioleds {
30 + compatible = "gpio-leds";
31 + user1 {
32 + label = "marduk:red:user1";
33 + gpios = <&sc16is752 0 GPIO_ACTIVE_LOW>;
34 + };
35 + user2 {
36 + label = "marduk:red:user2";
37 + gpios = <&sc16is752 1 GPIO_ACTIVE_LOW>;
38 + };
39 + user3 {
40 + label = "marduk:red:user3";
41 + gpios = <&sc16is752 2 GPIO_ACTIVE_LOW>;
42 + };
43 + user4 {
44 + label = "marduk:red:user4";
45 + gpios = <&sc16is752 3 GPIO_ACTIVE_LOW>;
46 + };
47 + user5 {
48 + label = "marduk:red:user5";
49 + gpios = <&sc16is752 4 GPIO_ACTIVE_LOW>;
50 + };
51 + user6 {
52 + label = "marduk:red:user6";
53 + gpios = <&sc16is752 5 GPIO_ACTIVE_LOW>;
54 + };
55 + user7 {
56 + label = "marduk:red:user7";
57 + gpios = <&sc16is752 6 GPIO_ACTIVE_LOW>;
58 + };
59 + };
60 +
61 led-controller {
62 compatible = "pwm-leds";
63
64 @@ -96,6 +136,17 @@
65 extclock-freq = <16000000>;
66 extclock-gpio = <2>;
67 };
68 +
69 + sc16is752: sc16is752@1 {
70 + compatible = "nxp,sc16is752";
71 + reg = <1>;
72 + clocks = <&ca8210_ext_clk>;
73 + spi-max-frequency = <4000000>;
74 + interrupt-parent = <&gpio0>;
75 + interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
76 + gpio-controller;
77 + #gpio-cells = <2>;
78 + };
79 };
80
81 &spfi1 {