target/linux/generic/backport-6.1/789-STABLE-03-net-dsa-mt7530-fix-handling-of-all-link-local-frames.patch

   1 From 86c0c154a759f2af9612a04bdf29110f02dce956 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
   3 Date: Thu, 14 Mar 2024 12:33:42 +0300
   4 Subject: [PATCH 3/3] net: dsa: mt7530: fix handling of all link-local frames
   5 MIME-Version: 1.0
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   8
   9 [ Upstream commit 69ddba9d170bdaee1dc0eb4ced38d7e4bb7b92af ]
  10
  11 Currently, the MT753X switches treat frames with :01-0D and :0F MAC DAs as
  12 regular multicast frames, therefore flooding them to user ports.
  13
  14 On page 205, section "8.6.3 Frame filtering" of the active standard, IEEE
  15 Std 802.1Q™-2022, it is stated that frames with 01:80:C2:00:00:00-0F as MAC
  16 DA must only be propagated to C-VLAN and MAC Bridge components. That means
  17 VLAN-aware and VLAN-unaware bridges. On the switch designs with CPU ports,
  18 these frames are supposed to be processed by the CPU (software). So we make
  19 the switch only forward them to the CPU port. And if received from a CPU
  20 port, forward to a single port. The software is responsible of making the
  21 switch conform to the latter by setting a single port as destination port
  22 on the special tag.
  23
  24 This switch intellectual property cannot conform to this part of the
  25 standard fully. Whilst the REV_UN frame tag covers the remaining :04-0D and
  26 :0F MAC DAs, it also includes :22-FF which the scope of propagation is not
  27 supposed to be restricted for these MAC DAs.
  28
  29 Set frames with :01-03 MAC DAs to be trapped to the CPU port(s). Add a
  30 comment for the remaining MAC DAs.
  31
  32 Note that the ingress port must have a PVID assigned to it for the switch
  33 to forward untagged frames. A PVID is set by default on VLAN-aware and
  34 VLAN-unaware ports. However, when the network interface that pertains to
  35 the ingress port is attached to a vlan_filtering enabled bridge, the user
  36 can remove the PVID assignment from it which would prevent the link-local
  37 frames from being trapped to the CPU port. I am yet to see a way to forward
  38 link-local frames while preventing other untagged frames from being
  39 forwarded too.
  40
  41 Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
  42 Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
  43 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  44 Signed-off-by: Sasha Levin <sashal@kernel.org>
  45 ---
  46  drivers/net/dsa/mt7530.c | 37 +++++++++++++++++++++++++++++++++----
  47  drivers/net/dsa/mt7530.h | 13 +++++++++++++
  48  2 files changed, 46 insertions(+), 4 deletions(-)
  49
  50 --- a/drivers/net/dsa/mt7530.c
  51 +++ b/drivers/net/dsa/mt7530.c
  52 @@ -998,6 +998,21 @@ unlock_exit:
  53         mutex_unlock(&priv->reg_mutex);
  54  }
  55
  56 +/* On page 205, section "8.6.3 Frame filtering" of the active standard, IEEE Std
  57 + * 802.1Q™-2022, it is stated that frames with 01:80:C2:00:00:00-0F as MAC DA
  58 + * must only be propagated to C-VLAN and MAC Bridge components. That means
  59 + * VLAN-aware and VLAN-unaware bridges. On the switch designs with CPU ports,
  60 + * these frames are supposed to be processed by the CPU (software). So we make
  61 + * the switch only forward them to the CPU port. And if received from a CPU
  62 + * port, forward to a single port. The software is responsible of making the
  63 + * switch conform to the latter by setting a single port as destination port on
  64 + * the special tag.
  65 + *
  66 + * This switch intellectual property cannot conform to this part of the standard
  67 + * fully. Whilst the REV_UN frame tag covers the remaining :04-0D and :0F MAC
  68 + * DAs, it also includes :22-FF which the scope of propagation is not supposed
  69 + * to be restricted for these MAC DAs.
  70 + */
  71  static void
  72  mt753x_trap_frames(struct mt7530_priv *priv)
  73  {
  74 @@ -1012,13 +1027,27 @@ mt753x_trap_frames(struct mt7530_priv *p
  75                    MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
  76                    MT753X_BPDU_CPU_ONLY);
  77
  78 -       /* Trap LLDP frames with :0E MAC DA to the CPU port(s) and egress them
  79 -        * VLAN-untagged.
  80 +       /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress
  81 +        * them VLAN-untagged.
  82 +        */
  83 +       mt7530_rmw(priv, MT753X_RGAC1, MT753X_R02_EG_TAG_MASK |
  84 +                  MT753X_R02_PORT_FW_MASK | MT753X_R01_EG_TAG_MASK |
  85 +                  MT753X_R01_PORT_FW_MASK,
  86 +                  MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
  87 +                  MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
  88 +                  MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
  89 +                  MT753X_BPDU_CPU_ONLY);
  90 +
  91 +       /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress
  92 +        * them VLAN-untagged.
  93          */
  94         mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_EG_TAG_MASK |
  95 -                  MT753X_R0E_PORT_FW_MASK,
  96 +                  MT753X_R0E_PORT_FW_MASK | MT753X_R03_EG_TAG_MASK |
  97 +                  MT753X_R03_PORT_FW_MASK,
  98                    MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
  99 -                  MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY));
 100 +                  MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
 101 +                  MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
 102 +                  MT753X_BPDU_CPU_ONLY);
 103  }
 104
 105  static int
 106 --- a/drivers/net/dsa/mt7530.h
 107 +++ b/drivers/net/dsa/mt7530.h
 108 @@ -71,12 +71,25 @@ enum mt753x_id {
 109  #define  MT753X_BPDU_EG_TAG(x)         FIELD_PREP(MT753X_BPDU_EG_TAG_MASK, x)
 110  #define  MT753X_BPDU_PORT_FW_MASK      GENMASK(2, 0)
 111
 112 +/* Register for :01 and :02 MAC DA frame control */
 113 +#define MT753X_RGAC1                   0x28
 114 +#define  MT753X_R02_EG_TAG_MASK                GENMASK(24, 22)
 115 +#define  MT753X_R02_EG_TAG(x)          FIELD_PREP(MT753X_R02_EG_TAG_MASK, x)
 116 +#define  MT753X_R02_PORT_FW_MASK       GENMASK(18, 16)
 117 +#define  MT753X_R02_PORT_FW(x)         FIELD_PREP(MT753X_R02_PORT_FW_MASK, x)
 118 +#define  MT753X_R01_EG_TAG_MASK                GENMASK(8, 6)
 119 +#define  MT753X_R01_EG_TAG(x)          FIELD_PREP(MT753X_R01_EG_TAG_MASK, x)
 120 +#define  MT753X_R01_PORT_FW_MASK       GENMASK(2, 0)
 121 +
 122  /* Register for :03 and :0E MAC DA frame control */
 123  #define MT753X_RGAC2                   0x2c
 124  #define  MT753X_R0E_EG_TAG_MASK                GENMASK(24, 22)
 125  #define  MT753X_R0E_EG_TAG(x)          FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x)
 126  #define  MT753X_R0E_PORT_FW_MASK       GENMASK(18, 16)
 127  #define  MT753X_R0E_PORT_FW(x)         FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x)
 128 +#define  MT753X_R03_EG_TAG_MASK                GENMASK(8, 6)
 129 +#define  MT753X_R03_EG_TAG(x)          FIELD_PREP(MT753X_R03_EG_TAG_MASK, x)
 130 +#define  MT753X_R03_PORT_FW_MASK       GENMASK(2, 0)
 131
 132  enum mt753x_bpdu_port_fw {
 133         MT753X_BPDU_FOLLOW_MFC,