target/linux/x86/patches-5.15/103-pcengines_apu6_platform.patch

   1 From 970d9af9015a387bb81841faf05dcc1a171eb97a Mon Sep 17 00:00:00 2001
   2 From: Philip Prindeville <philipp@redfish-solutions.com>
   3 Date: Sun, 1 Jan 2023 15:25:04 -0700
   4 Subject: [PATCH v3 1/1] x86: Support APU5 in PCEngines platform driver
   5 To: platform-driver-x86@vger.kernel.org, linux-x86_64@vger.kernel.org
   6 Cc: Ed Wildgoose <lists@wildgooses.com>, Andres Salomon <dilinger@queued.net>, Andreas Eberlein <foodeas@aeberlein.de>, Paul Spooren <paul@spooren.de>
   7
   8 PCEngines make a number of SBC. APU5 has 5 mpcie slots + MSATA.
   9 It also has support for 3x LTE modems with 6x SIM slots (pairs with a
  10 SIM switch device). Each mpcie slot for modems has a reset GPIO
  11
  12 To ensure that the naming is sane between APU2-6 the GPIOS are
  13 renamed to be modem1-reset, modem2-reset, etc. This is significant
  14 because the slots that can be reset change between APU2 and APU3/4
  15
  16 GPIO for simswap is moved to the end of the list as it could be dropped
  17 for APU2 boards (but causes no harm to leave it in, hardware could be
  18 added to a future rev of the board).
  19
  20 Structure of the GPIOs for APU5 is extremely similar to APU2-4, but
  21 many lines are moved around and there are simply more
  22 modems/resets/sim-swap lines to breakout.
  23
  24 Also added APU6, which is essentially APU4 with a different ethernet
  25 interface and SFP cage on eth0.
  26
  27 Revision history:
  28
  29 v1: originally titled, "apu6: add apu6 variation to apu2 driver family"
  30 this dealt only with detecting the APUv6, which is otherwise identical
  31 to the v4 excepting the SFP cage on eth0.
  32
  33 v2: at Ed's request, merged with his previous pull-request titled
  34 "x86: Support APU5 in PCEngines platform driver", and some cleanup
  35 to that changeset (including dropping the table "apu5_driver_data"
  36 which did not have a defined type "struct apu_driver_data"), but got
  37 mistitled when the Subject of that commit got accidentally dropped.
  38
  39 v3: retitled to match Ed's previous pull-request.
  40
  41 Cc: platform-driver-x86@vger.kernel.org
  42 Cc: linux-x86_64@vger.kernel.org
  43 Reviewed-by: Andreas Eberlein <foodeas@aeberlein.de>
  44 Reviewed-by: Paul Spooren <paul@spooren.de>
  45 Signed-off-by: Ed Wildgoose <lists@wildgooses.com>
  46 Sighed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
  47 ---
  48  drivers/leds/leds-apu.c                |   2 +-
  49  drivers/platform/x86/Kconfig           |   4 +-
  50  drivers/platform/x86/pcengines-apuv2.c | 118 ++++++++++++++++++++++---
  51  3 files changed, 107 insertions(+), 17 deletions(-)
  52
  53 --- a/drivers/leds/leds-apu.c
  54 +++ b/drivers/leds/leds-apu.c
  55 @@ -183,7 +183,7 @@ static int __init apu_led_init(void)
  56
  57         if (!(dmi_match(DMI_SYS_VENDOR, "PC Engines") &&
  58               (dmi_match(DMI_PRODUCT_NAME, "APU") || dmi_match(DMI_PRODUCT_NAME, "apu1")))) {
  59 -               pr_err("No PC Engines APUv1 board detected. For APUv2,3 support, enable CONFIG_PCENGINES_APU2\n");
  60 +               pr_err("No PC Engines APUv1 board detected. For APUv2,3,4,5,6 support, enable CONFIG_PCENGINES_APU2\n");
  61                 return -ENODEV;
  62         }
  63
  64 --- a/drivers/platform/x86/Kconfig
  65 +++ b/drivers/platform/x86/Kconfig
  66 @@ -701,7 +701,7 @@ config XO1_RFKILL
  67           laptop.
  68
  69  config PCENGINES_APU2
  70 -       tristate "PC Engines APUv2/3 front button and LEDs driver"
  71 +       tristate "PC Engines APUv2/3/4/5/6 front button and LEDs driver"
  72         depends on INPUT && INPUT_KEYBOARD && GPIOLIB
  73         depends on LEDS_CLASS
  74         select GPIO_AMD_FCH
  75 @@ -709,7 +709,7 @@ config PCENGINES_APU2
  76         select LEDS_GPIO
  77         help
  78           This driver provides support for the front button and LEDs on
  79 -         PC Engines APUv2/APUv3 board.
  80 +         PC Engines APUv2/APUv3/APUv4/APUv5/APUv6 board.
  81
  82           To compile this driver as a module, choose M here: the module
  83           will be called pcengines-apuv2.
  84 --- a/drivers/platform/x86/pcengines-apuv2.c
  85 +++ b/drivers/platform/x86/pcengines-apuv2.c
  86 @@ -1,10 +1,12 @@
  87  // SPDX-License-Identifier: GPL-2.0+
  88
  89  /*
  90 - * PC-Engines APUv2/APUv3 board platform driver
  91 + * PC-Engines APUv2-6 board platform driver
  92   * for GPIO buttons and LEDs
  93   *
  94   * Copyright (C) 2018 metux IT consult
  95 + * Copyright (C) 2022 Ed Wildgoose <lists@wildgooses.com>
  96 + * Copyright (C) 2022 Philip Prindeville <philipp@redfish-solutions.com>
  97   * Author: Enrico Weigelt <info@metux.net>
  98   */
  99
 100 @@ -22,38 +24,70 @@
 101  #include <linux/platform_data/gpio/gpio-amd-fch.h>
 102
 103  /*
 104 - * NOTE: this driver only supports APUv2/3 - not APUv1, as this one
 105 + * NOTE: this driver only supports APUv2-6 - not APUv1, as this one
 106   * has completely different register layouts.
 107   */
 108
 109 +/*
 110 + * There are a number of APU variants, with differing features
 111 + * APU2 has SIM slots 1/2 mapping to mPCIe sockets 1/2
 112 + * APU3/4 moved SIM slot 1 to mPCIe socket 3, ie logically reversed
 113 + * However, most APU3/4 have a SIM switch which we default on to reverse
 114 + * the order and keep physical SIM order matching physical modem order
 115 + * APU6 is approximately the same as APU4 with different ethernet layout
 116 + *
 117 + * APU5 has 3x SIM sockets, all with a SIM switch
 118 + * several GPIOs are shuffled (see schematic), including MODESW
 119 + */
 120 +
 121  /* Register mappings */
 122  #define APU2_GPIO_REG_LED1             AMD_FCH_GPIO_REG_GPIO57
 123  #define APU2_GPIO_REG_LED2             AMD_FCH_GPIO_REG_GPIO58
 124  #define APU2_GPIO_REG_LED3             AMD_FCH_GPIO_REG_GPIO59_DEVSLP1
 125  #define APU2_GPIO_REG_MODESW           AMD_FCH_GPIO_REG_GPIO32_GE1
 126  #define APU2_GPIO_REG_SIMSWAP          AMD_FCH_GPIO_REG_GPIO33_GE2
 127 -#define APU2_GPIO_REG_MPCIE2           AMD_FCH_GPIO_REG_GPIO55_DEVSLP0
 128 -#define APU2_GPIO_REG_MPCIE3           AMD_FCH_GPIO_REG_GPIO51
 129 +#define APU2_GPIO_REG_RESETM1          AMD_FCH_GPIO_REG_GPIO51
 130 +#define APU2_GPIO_REG_RESETM2          AMD_FCH_GPIO_REG_GPIO55_DEVSLP0
 131 +
 132 +#define APU5_GPIO_REG_MODESW           AMT_FCH_GPIO_REG_GEVT22
 133 +#define APU5_GPIO_REG_SIMSWAP1         AMD_FCH_GPIO_REG_GPIO68
 134 +#define APU5_GPIO_REG_SIMSWAP2         AMD_FCH_GPIO_REG_GPIO32_GE1
 135 +#define APU5_GPIO_REG_SIMSWAP3         AMD_FCH_GPIO_REG_GPIO33_GE2
 136 +#define APU5_GPIO_REG_RESETM1          AMD_FCH_GPIO_REG_GPIO51
 137 +#define APU5_GPIO_REG_RESETM2          AMD_FCH_GPIO_REG_GPIO55_DEVSLP0
 138 +#define APU5_GPIO_REG_RESETM3          AMD_FCH_GPIO_REG_GPIO64
 139
 140  /* Order in which the GPIO lines are defined in the register list */
 141  #define APU2_GPIO_LINE_LED1            0
 142  #define APU2_GPIO_LINE_LED2            1
 143  #define APU2_GPIO_LINE_LED3            2
 144  #define APU2_GPIO_LINE_MODESW          3
 145 -#define APU2_GPIO_LINE_SIMSWAP         4
 146 -#define APU2_GPIO_LINE_MPCIE2          5
 147 -#define APU2_GPIO_LINE_MPCIE3          6
 148 +#define APU2_GPIO_LINE_RESETM1         4
 149 +#define APU2_GPIO_LINE_RESETM2         5
 150 +#define APU2_GPIO_LINE_SIMSWAP         6
 151 +
 152 +#define APU5_GPIO_LINE_LED1            0
 153 +#define APU5_GPIO_LINE_LED2            1
 154 +#define APU5_GPIO_LINE_LED3            2
 155 +#define APU5_GPIO_LINE_MODESW          3
 156 +#define APU5_GPIO_LINE_RESETM1         4
 157 +#define APU5_GPIO_LINE_RESETM2         5
 158 +#define APU5_GPIO_LINE_RESETM3         6
 159 +#define APU5_GPIO_LINE_SIMSWAP1                7
 160 +#define APU5_GPIO_LINE_SIMSWAP2                8
 161 +#define APU5_GPIO_LINE_SIMSWAP3                9
 162 +
 163
 164 -/* GPIO device */
 165 +/* GPIO device - APU2/3/4/6 */
 166
 167  static int apu2_gpio_regs[] = {
 168         [APU2_GPIO_LINE_LED1]           = APU2_GPIO_REG_LED1,
 169         [APU2_GPIO_LINE_LED2]           = APU2_GPIO_REG_LED2,
 170         [APU2_GPIO_LINE_LED3]           = APU2_GPIO_REG_LED3,
 171         [APU2_GPIO_LINE_MODESW]         = APU2_GPIO_REG_MODESW,
 172 +       [APU2_GPIO_LINE_RESETM1]        = APU2_GPIO_REG_RESETM1,
 173 +       [APU2_GPIO_LINE_RESETM2]        = APU2_GPIO_REG_RESETM2,
 174         [APU2_GPIO_LINE_SIMSWAP]        = APU2_GPIO_REG_SIMSWAP,
 175 -       [APU2_GPIO_LINE_MPCIE2]         = APU2_GPIO_REG_MPCIE2,
 176 -       [APU2_GPIO_LINE_MPCIE3]         = APU2_GPIO_REG_MPCIE3,
 177  };
 178
 179  static const char * const apu2_gpio_names[] = {
 180 @@ -61,9 +95,9 @@ static const char * const apu2_gpio_name
 181         [APU2_GPIO_LINE_LED2]           = "front-led2",
 182         [APU2_GPIO_LINE_LED3]           = "front-led3",
 183         [APU2_GPIO_LINE_MODESW]         = "front-button",
 184 +       [APU2_GPIO_LINE_RESETM1]        = "modem1-reset",
 185 +       [APU2_GPIO_LINE_RESETM2]        = "modem2-reset",
 186         [APU2_GPIO_LINE_SIMSWAP]        = "simswap",
 187 -       [APU2_GPIO_LINE_MPCIE2]         = "mpcie2_reset",
 188 -       [APU2_GPIO_LINE_MPCIE3]         = "mpcie3_reset",
 189  };
 190
 191  static const struct amd_fch_gpio_pdata board_apu2 = {
 192 @@ -72,6 +106,40 @@ static const struct amd_fch_gpio_pdata b
 193         .gpio_names     = apu2_gpio_names,
 194  };
 195
 196 +/* GPIO device - APU5 */
 197 +
 198 +static int apu5_gpio_regs[] = {
 199 +       [APU5_GPIO_LINE_LED1]           = APU2_GPIO_REG_LED1,
 200 +       [APU5_GPIO_LINE_LED2]           = APU2_GPIO_REG_LED2,
 201 +       [APU5_GPIO_LINE_LED3]           = APU2_GPIO_REG_LED3,
 202 +       [APU5_GPIO_LINE_MODESW]         = APU5_GPIO_REG_MODESW,
 203 +       [APU5_GPIO_LINE_RESETM1]        = APU5_GPIO_REG_RESETM1,
 204 +       [APU5_GPIO_LINE_RESETM2]        = APU5_GPIO_REG_RESETM2,
 205 +       [APU5_GPIO_LINE_RESETM3]        = APU5_GPIO_REG_RESETM3,
 206 +       [APU5_GPIO_LINE_SIMSWAP1]       = APU5_GPIO_REG_SIMSWAP1,
 207 +       [APU5_GPIO_LINE_SIMSWAP2]       = APU5_GPIO_REG_SIMSWAP2,
 208 +       [APU5_GPIO_LINE_SIMSWAP3]       = APU5_GPIO_REG_SIMSWAP3,
 209 +};
 210 +
 211 +static const char * const apu5_gpio_names[] = {
 212 +       [APU5_GPIO_LINE_LED1]           = "front-led1",
 213 +       [APU5_GPIO_LINE_LED2]           = "front-led2",
 214 +       [APU5_GPIO_LINE_LED3]           = "front-led3",
 215 +       [APU5_GPIO_LINE_MODESW]         = "front-button",
 216 +       [APU5_GPIO_LINE_RESETM1]        = "modem1-reset",
 217 +       [APU5_GPIO_LINE_RESETM2]        = "modem2-reset",
 218 +       [APU5_GPIO_LINE_RESETM3]        = "modem3-reset",
 219 +       [APU5_GPIO_LINE_SIMSWAP1]       = "simswap1",
 220 +       [APU5_GPIO_LINE_SIMSWAP2]       = "simswap2",
 221 +       [APU5_GPIO_LINE_SIMSWAP3]       = "simswap3",
 222 +};
 223 +
 224 +static const struct amd_fch_gpio_pdata board_apu5 = {
 225 +       .gpio_num       = ARRAY_SIZE(apu5_gpio_regs),
 226 +       .gpio_reg       = apu5_gpio_regs,
 227 +       .gpio_names     = apu5_gpio_names,
 228 +};
 229 +
 230  /* GPIO LEDs device */
 231
 232  static const struct gpio_led apu2_leds[] = {
 233 @@ -215,6 +283,24 @@ static const struct dmi_system_id apu_gp
 234                 },
 235                 .driver_data = (void *)&board_apu2,
 236         },
 237 +       /* APU5 w/ mainline BIOS */
 238 +       {
 239 +               .ident          = "apu5",
 240 +               .matches        = {
 241 +                       DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
 242 +                       DMI_MATCH(DMI_BOARD_NAME, "apu5")
 243 +               },
 244 +               .driver_data    = (void *)&board_apu5,
 245 +       },
 246 +       /* APU6 w/ mainline BIOS */
 247 +       {
 248 +               .ident          = "apu6",
 249 +               .matches        = {
 250 +                       DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
 251 +                       DMI_MATCH(DMI_BOARD_NAME, "apu6")
 252 +               },
 253 +               .driver_data    = (void *)&board_apu2,
 254 +       },
 255         {}
 256  };
 257
 258 @@ -249,7 +335,7 @@ static int __init apu_board_init(void)
 259
 260         id = dmi_first_match(apu_gpio_dmi_table);
 261         if (!id) {
 262 -               pr_err("failed to detect APU board via DMI\n");
 263 +               pr_err("No APU board detected via DMI\n");
 264                 return -ENODEV;
 265         }
 266
 267 @@ -288,8 +374,12 @@ module_init(apu_board_init);
 268  module_exit(apu_board_exit);
 269
 270  MODULE_AUTHOR("Enrico Weigelt, metux IT consult <info@metux.net>");
 271 -MODULE_DESCRIPTION("PC Engines APUv2/APUv3 board GPIO/LEDs/keys driver");
 272 +MODULE_DESCRIPTION("PC Engines APUv2-6 board GPIO/LEDs/keys driver");
 273  MODULE_LICENSE("GPL");
 274  MODULE_DEVICE_TABLE(dmi, apu_gpio_dmi_table);
 275  MODULE_ALIAS("platform:pcengines-apuv2");
 276 +MODULE_ALIAS("platform:pcengines-apuv3");
 277 +MODULE_ALIAS("platform:pcengines-apuv4");
 278 +MODULE_ALIAS("platform:pcengines-apuv5");
 279 +MODULE_ALIAS("platform:pcengines-apuv6");
 280  MODULE_SOFTDEP("pre: platform:" AMD_FCH_GPIO_DRIVER_NAME " platform:leds-gpio platform:gpio_keys_polled");