1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
7 #include <dt-bindings/clock/mt7986-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy.h>
11 #include <dt-bindings/reset/mt7986-resets.h>
14 interrupt-parent = <&gic>;
18 clk40m: oscillator@0 {
19 compatible = "fixed-clock";
20 clock-frequency = <40000000>;
22 clock-output-names = "clkxtal";
30 compatible = "arm,cortex-a53";
31 enable-method = "psci";
38 compatible = "arm,cortex-a53";
39 enable-method = "psci";
46 compatible = "arm,cortex-a53";
47 enable-method = "psci";
54 enable-method = "psci";
55 compatible = "arm,cortex-a53";
62 compatible = "arm,psci-0.2";
71 /* 64 KiB reserved for ramoops/pstore */
73 compatible = "ramoops";
74 reg = <0 0x42ff0000 0 0x10000>;
75 record-size = <0x1000>;
78 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
79 secmon_reserved: secmon@43000000 {
80 reg = <0 0x43000000 0 0x30000>;
84 wmcpu_emi: wmcpu-reserved@4fc00000 {
86 reg = <0 0x4fc00000 0 0x00100000>;
91 compatible = "arm,armv8-timer";
92 interrupt-parent = <&gic>;
93 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
94 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
95 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
96 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
100 #address-cells = <2>;
102 compatible = "simple-bus";
105 gic: interrupt-controller@c000000 {
106 compatible = "arm,gic-v3";
107 #interrupt-cells = <3>;
108 interrupt-parent = <&gic>;
109 interrupt-controller;
110 reg = <0 0x0c000000 0 0x10000>, /* GICD */
111 <0 0x0c080000 0 0x80000>, /* GICR */
112 <0 0x0c400000 0 0x2000>, /* GICC */
113 <0 0x0c410000 0 0x1000>, /* GICH */
114 <0 0x0c420000 0 0x2000>; /* GICV */
115 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
118 infracfg: infracfg@10001000 {
119 compatible = "mediatek,mt7986-infracfg", "syscon";
120 reg = <0 0x10001000 0 0x1000>;
124 topckgen: topckgen@1001b000 {
125 compatible = "mediatek,mt7986-topckgen", "syscon";
126 reg = <0 0x1001B000 0 0x1000>;
130 watchdog: watchdog@1001c000 {
131 compatible = "mediatek,mt7986-wdt",
132 "mediatek,mt6589-wdt";
133 reg = <0 0x1001c000 0 0x1000>;
134 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
138 pio: pinctrl@1001f000 {
139 compatible = "mediatek,mt7986a-pinctrl";
140 reg = <0 0x1001f000 0 0x1000>,
141 <0 0x11c30000 0 0x1000>,
142 <0 0x11c40000 0 0x1000>,
143 <0 0x11e20000 0 0x1000>,
144 <0 0x11e30000 0 0x1000>,
145 <0 0x11f00000 0 0x1000>,
146 <0 0x11f10000 0 0x1000>,
147 <0 0x1000b000 0 0x1000>;
148 reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
149 "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
152 gpio-ranges = <&pio 0 0 100>;
153 interrupt-controller;
154 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
155 interrupt-parent = <&gic>;
156 #interrupt-cells = <2>;
159 apmixedsys: apmixedsys@1001e000 {
160 compatible = "mediatek,mt7986-apmixedsys";
161 reg = <0 0x1001E000 0 0x1000>;
165 sgmiisys0: syscon@10060000 {
166 compatible = "mediatek,mt7986-sgmiisys_0",
168 reg = <0 0x10060000 0 0x1000>;
172 sgmiisys1: syscon@10070000 {
173 compatible = "mediatek,mt7986-sgmiisys_1",
175 reg = <0 0x10070000 0 0x1000>;
179 trng: trng@1020f000 {
180 compatible = "mediatek,mt7986-rng";
181 reg = <0 0x1020f000 0 0x100>;
182 clocks = <&infracfg CLK_INFRA_TRNG_CK>;
187 crypto: crypto@10320000 {
188 compatible = "inside-secure,safexcel-eip97";
189 reg = <0 0x10320000 0 0x40000>;
190 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
194 interrupt-names = "ring0", "ring1", "ring2", "ring3";
195 clocks = <&infracfg CLK_INFRA_EIP97_CK>;
196 clock-names = "infra_eip97_ck";
197 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
198 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
202 uart0: serial@11002000 {
203 compatible = "mediatek,mt7986-uart",
204 "mediatek,mt6577-uart";
205 reg = <0 0x11002000 0 0x400>;
206 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
208 <&infracfg CLK_INFRA_UART0_CK>;
209 clock-names = "baud", "bus";
210 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
211 <&infracfg CLK_INFRA_UART0_SEL>;
212 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
213 <&topckgen CLK_TOP_UART_SEL>;
217 uart1: serial@11003000 {
218 compatible = "mediatek,mt7986-uart",
219 "mediatek,mt6577-uart";
220 reg = <0 0x11003000 0 0x400>;
221 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
223 <&infracfg CLK_INFRA_UART1_CK>;
224 clock-names = "baud", "bus";
225 assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
226 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
230 uart2: serial@11004000 {
231 compatible = "mediatek,mt7986-uart",
232 "mediatek,mt6577-uart";
233 reg = <0 0x11004000 0 0x400>;
234 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
236 <&infracfg CLK_INFRA_UART2_CK>;
237 clock-names = "baud", "bus";
238 assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
239 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
244 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
245 reg = <0 0x1100a000 0 0x100>;
246 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&topckgen CLK_TOP_MPLL_D2>,
248 <&topckgen CLK_TOP_SPI_SEL>,
249 <&infracfg CLK_INFRA_SPI0_CK>,
250 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
251 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
256 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
257 reg = <0 0x1100b000 0 0x100>;
258 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&topckgen CLK_TOP_MPLL_D2>,
260 <&topckgen CLK_TOP_SPIM_MST_SEL>,
261 <&infracfg CLK_INFRA_SPI1_CK>,
262 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
263 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
267 ssusb: usb@11200000 {
268 compatible = "mediatek,mt7986-xhci",
270 reg = <0 0x11200000 0 0x2e00>,
271 <0 0x11203e00 0 0x0100>;
272 reg-names = "mac", "ippc";
273 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
275 <&topckgen CLK_TOP_U2U3_XHCI_SEL>,
276 <&infracfg CLK_INFRA_IUSB_CK>,
277 <&infracfg CLK_INFRA_IUSB_133_CK>,
278 <&infracfg CLK_INFRA_IUSB_66M_CK>;
279 clock-names = "sys_ck",
284 phys = <&u2port0 PHY_TYPE_USB2>,
285 <&u3port0 PHY_TYPE_USB3>,
286 <&u2port1 PHY_TYPE_USB2>;
291 compatible = "mediatek,mt7986-mmc";
292 reg = <0 0x11230000 0 0x1000>,
293 <0 0x11c20000 0 0x1000>;
294 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&infracfg CLK_INFRA_MSDC_CK>,
296 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
297 <&infracfg CLK_INFRA_MSDC_66M_CK>,
298 <&infracfg CLK_INFRA_MSDC_133M_CK>;
299 clock-names = "source", "hclk", "axi_cg", "ahb_cg";
300 assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
301 <&topckgen CLK_TOP_EMMC_250M_SEL>;
302 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MPLL>,
303 <&topckgen CLK_TOP_NET1PLL_D5_D2>;
307 pcie: pcie@11280000 {
308 compatible = "mediatek,mt7986-pcie",
309 "mediatek,mt8192-pcie";
311 #address-cells = <3>;
313 reg = <0x00 0x11280000 0x00 0x4000>;
314 reg-names = "pcie-mac";
315 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
316 bus-range = <0x00 0xff>;
317 ranges = <0x82000000 0x00 0x20000000 0x00
318 0x20000000 0x00 0x10000000>;
319 clocks = <&infracfg CLK_INFRA_PCIE_SEL>,
320 <&infracfg CLK_INFRA_IPCIE_CK>,
321 <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
322 <&infracfg CLK_INFRA_IPCIER_CK>,
323 <&infracfg CLK_INFRA_IPCIEB_CK>;
326 phys = <&pcie_port PHY_TYPE_PCIE>;
327 phy-names = "pcie-phy";
329 #interrupt-cells = <1>;
330 interrupt-map-mask = <0 0 0 0x7>;
331 interrupt-map = <0 0 0 1 &pcie_intc 0>,
332 <0 0 0 2 &pcie_intc 1>,
333 <0 0 0 3 &pcie_intc 2>,
334 <0 0 0 4 &pcie_intc 3>;
335 pcie_intc: interrupt-controller {
336 #address-cells = <0>;
337 #interrupt-cells = <1>;
338 interrupt-controller;
342 pcie_phy: t-phy@11c00000 {
343 compatible = "mediatek,mt7986-tphy",
344 "mediatek,generic-tphy-v2";
345 #address-cells = <2>;
350 pcie_port: pcie-phy@11c00000 {
351 reg = <0 0x11c00000 0 0x20000>;
358 usb_phy: t-phy@11e10000 {
359 compatible = "mediatek,mt7986-tphy",
360 "mediatek,generic-tphy-v2";
361 #address-cells = <2>;
366 u2port0: usb-phy@11e10000 {
367 reg = <0 0x11e10000 0 0x700>;
368 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
369 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
370 clock-names = "ref", "da_ref";
374 u3port0: usb-phy@11e10700 {
375 reg = <0 0x11e10700 0 0x900>;
376 clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
381 u2port1: usb-phy@11e11000 {
382 reg = <0 0x11e11000 0 0x700>;
383 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
384 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
385 clock-names = "ref", "da_ref";
390 ethsys: syscon@15000000 {
391 #address-cells = <1>;
393 compatible = "mediatek,mt7986-ethsys_ck",
395 reg = <0 0x15000000 0 0x1000>;
400 wed_pcie: wed-pcie@10003000 {
401 compatible = "mediatek,mt7986-wed-pcie",
403 reg = <0 0x10003000 0 0x10>;
407 compatible = "mediatek,mt7986-wed",
409 reg = <0 0x15010000 0 0x1000>;
410 interrupt-parent = <&gic>;
411 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
415 compatible = "mediatek,mt7986-wed",
417 reg = <0 0x15011000 0 0x1000>;
418 interrupt-parent = <&gic>;
419 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
422 eth: ethernet@15100000 {
423 compatible = "mediatek,mt7986-eth";
424 reg = <0 0x15100000 0 0x80000>;
425 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <ðsys CLK_ETH_FE_EN>,
430 <ðsys CLK_ETH_GP2_EN>,
431 <ðsys CLK_ETH_GP1_EN>,
432 <ðsys CLK_ETH_WOCPU1_EN>,
433 <ðsys CLK_ETH_WOCPU0_EN>,
434 <&sgmiisys0 CLK_SGMII0_TX250M_EN>,
435 <&sgmiisys0 CLK_SGMII0_RX250M_EN>,
436 <&sgmiisys0 CLK_SGMII0_CDR_REF>,
437 <&sgmiisys0 CLK_SGMII0_CDR_FB>,
438 <&sgmiisys1 CLK_SGMII1_TX250M_EN>,
439 <&sgmiisys1 CLK_SGMII1_RX250M_EN>,
440 <&sgmiisys1 CLK_SGMII1_CDR_REF>,
441 <&sgmiisys1 CLK_SGMII1_CDR_FB>,
442 <&topckgen CLK_TOP_NETSYS_SEL>,
443 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
444 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
445 "sgmii_tx250m", "sgmii_rx250m",
446 "sgmii_cdr_ref", "sgmii_cdr_fb",
447 "sgmii2_tx250m", "sgmii2_rx250m",
448 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
449 "netsys0", "netsys1";
450 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
451 <&topckgen CLK_TOP_SGM_325M_SEL>;
452 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
453 <&apmixedsys CLK_APMIXED_SGMPLL>;
454 mediatek,ethsys = <ðsys>;
455 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
456 mediatek,wed-pcie = <&wed_pcie>;
457 mediatek,wed = <&wed0>, <&wed1>;
459 #address-cells = <1>;
464 consys: consys@10000000 {
465 compatible = "mediatek,mt7986-consys";
466 reg = <0 0x10000000 0 0x8600000>;
467 memory-region = <&wmcpu_emi>;
470 wmac: wmac@18000000 {
471 compatible = "mediatek,mt7986-wmac", "mediatek,wbsys";
472 resets = <&watchdog MT7986_TOPRGU_CONSYS_RST>;
473 reset-names = "consys";
474 reg = <0 0x18000000 0 0x1000000>,
475 <0 0x10003000 0 0x1000>,
476 <0 0x11d10000 0 0x1000>;
477 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
482 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
483 clock-names = "mcu", "ap2conn";
484 memory-region = <&wmcpu_emi>;