target/linux/mediatek/dts/mt7622-netgear-wax206.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /* Copyright (c) 2022, Marcel Ziswiler <marcel@ziswiler.com> */
   3
   4 /dts-v1/;
   5 #include "mt7622.dtsi"
   6 #include "mt6380.dtsi"
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/input/input.h>
   9
  10 / {
  11         model = "Netgear WAX206";
  12         compatible = "netgear,wax206", "mediatek,mt7622";
  13
  14         aliases {
  15                 ethernet0 = &gmac0;
  16                 led-boot = &led_power_r;
  17                 led-failsafe = &led_power_r;
  18                 led-running = &led_power_g;
  19                 led-upgrade = &led_power_g;
  20                 serial0 = &uart0;
  21         };
  22
  23         chosen {
  24                 stdout-path = "serial0:115200n8";
  25                 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512";
  26         };
  27
  28         cpus {
  29                 cpu@0 {
  30                         proc-supply = <&mt6380_vcpu_reg>;
  31                         sram-supply = <&mt6380_vm_reg>;
  32                 };
  33
  34                 cpu@1 {
  35                         proc-supply = <&mt6380_vcpu_reg>;
  36                         sram-supply = <&mt6380_vm_reg>;
  37                 };
  38         };
  39
  40         gpio-keys {
  41                 compatible = "gpio-keys";
  42
  43                 reset {
  44                         gpios = <&pio 0 GPIO_ACTIVE_LOW>;
  45                         label = "reset";
  46                         linux,code = <KEY_RESTART>;
  47                 };
  48
  49                 wps {
  50                         gpios = <&pio 102 GPIO_ACTIVE_LOW>;
  51                         label = "wps";
  52                         linux,code = <KEY_WPS_BUTTON>;
  53                 };
  54         };
  55
  56         gpio-leds {
  57                 compatible = "gpio-leds";
  58
  59                 led_power_r: power_red {
  60                         default-state = "on";
  61                         gpios = <&pio 3 GPIO_ACTIVE_LOW>;
  62                         label = "power:red";
  63                 };
  64
  65                 led_power_g: power_green {
  66                         default-state = "off";
  67                         gpios = <&pio 4 GPIO_ACTIVE_LOW>;
  68                         label = "power:green";
  69                 };
  70
  71                 inet_green {
  72                         default-state = "off";
  73                         gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
  74                         label = "inet:green";
  75                 };
  76
  77                 inet_blue {
  78                         default-state = "off";
  79                         gpios = <&pio 17 GPIO_ACTIVE_LOW>;
  80                         label = "inet:blue";
  81                 };
  82
  83                 wifin_green {
  84                         default-state = "off";
  85                         gpios = <&pio 85 GPIO_ACTIVE_LOW>;
  86                         label = "wifin:green";
  87                 };
  88
  89                 wifin_blue {
  90                         default-state = "off";
  91                         gpios = <&pio 86 GPIO_ACTIVE_LOW>;
  92                         label = "wifin:blue";
  93                 };
  94
  95                 wifia_green {
  96                         default-state = "off";
  97                         gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
  98                         label = "wifia:green";
  99                 };
 100
 101                 wifia_blue {
 102                         default-state = "off";
 103                         gpios = <&pio 1 GPIO_ACTIVE_LOW>;
 104                         label = "wifia:blue";
 105                 };
 106         };
 107
 108         memory {
 109                 reg = <0 0x40000000 0 0x40000000>;
 110         };
 111 };
 112
 113 &bch {
 114         status = "okay";
 115 };
 116
 117 &btif {
 118         status = "okay";
 119 };
 120
 121 &cir {
 122         pinctrl-names = "default";
 123         pinctrl-0 = <&irrx_pins>;
 124         status = "okay";
 125 };
 126
 127 &eth {
 128         pinctrl-names = "default";
 129         pinctrl-0 = <&eth_pins>;
 130         status = "okay";
 131
 132         gmac0: mac@0 {
 133                 compatible = "mediatek,eth-mac";
 134                 nvmem-cells = <&macaddr_factory_7fff4>;
 135                 nvmem-cell-names = "mac-address";
 136                 phy-mode = "2500base-x";
 137                 reg = <0>;
 138
 139                 fixed-link {
 140                         full-duplex;
 141                         pause;
 142                         speed = <2500>;
 143                 };
 144         };
 145
 146         mdio-bus {
 147                 #address-cells = <1>;
 148                 #size-cells = <0>;
 149
 150                 switch@0 {
 151                         compatible = "mediatek,mt7531";
 152                         #interrupt-cells = <1>;
 153                         interrupt-controller;
 154                         interrupt-parent = <&pio>;
 155                         interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
 156                         reg = <0>;
 157                         reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
 158
 159                         ports {
 160                                 #address-cells = <1>;
 161                                 #size-cells = <0>;
 162
 163                                 port@1 {
 164                                         label = "lan1";
 165                                         reg = <1>;
 166                                 };
 167
 168                                 port@2 {
 169                                         label = "lan2";
 170                                         reg = <2>;
 171                                 };
 172
 173                                 port@3 {
 174                                         label = "lan3";
 175                                         reg = <3>;
 176                                 };
 177
 178                                 port@4 {
 179                                         label = "lan4";
 180                                         reg = <4>;
 181                                 };
 182
 183                                 wan: port@5 {
 184                                         label = "wan";
 185                                         nvmem-cells = <&macaddr_factory_7fffa>;
 186                                         nvmem-cell-names = "mac-address";
 187                                         phy-handle = <&rtl8221b_phy>;
 188                                         phy-mode = "sgmii";
 189                                         reg = <5>;
 190                                 };
 191
 192                                 port@6 {
 193                                         ethernet = <&gmac0>;
 194                                         phy-mode = "2500base-x";
 195                                         reg = <6>;
 196
 197                                         fixed-link {
 198                                                 full-duplex;
 199                                                 pause;
 200                                                 speed = <2500>;
 201                                         };
 202                                 };
 203                         };
 204                 };
 205
 206                 rtl8221b_phy: ethernet-phy@7 {
 207                         compatible = "ethernet-phy-id001c.c849";
 208                         reg = <7>;
 209                         reset-gpios = <&pio 101 GPIO_ACTIVE_LOW>;
 210                         interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
 211                         reset-assert-us = <100000>;
 212                         reset-deassert-us = <100000>;
 213                 };
 214         };
 215 };
 216
 217 &pcie0 {
 218         pinctrl-names = "default";
 219         pinctrl-0 = <&pcie0_pins>;
 220         status = "okay";
 221 };
 222
 223 &pcie1 {
 224         pinctrl-names = "default";
 225         pinctrl-0 = <&pcie1_pins>;
 226         status = "okay";
 227 };
 228
 229 &pio {
 230         eth_pins: eth-pins {
 231                 mux {
 232                         function = "eth";
 233                         groups = "mdc_mdio", "rgmii_via_gmac2";
 234                 };
 235         };
 236
 237         irrx_pins: irrx-pins {
 238                 mux {
 239                         function = "ir";
 240                         groups =  "ir_1_rx";
 241                 };
 242         };
 243
 244         irtx_pins: irtx-pins {
 245                 mux {
 246                         function = "ir";
 247                         groups =  "ir_1_tx";
 248                 };
 249         };
 250
 251         pcie0_pins: pcie0-pins {
 252                 mux {
 253                         function = "pcie";
 254                         groups = "pcie0_pad_perst",
 255                                  "pcie0_1_waken",
 256                                  "pcie0_1_clkreq";
 257                 };
 258         };
 259
 260         pcie1_pins: pcie1-pins {
 261                 mux {
 262                         function = "pcie";
 263                         groups = "pcie1_pad_perst",
 264                                  "pcie1_0_waken",
 265                                  "pcie1_0_clkreq";
 266                 };
 267         };
 268
 269         pmic_bus_pins: pmic-bus-pins {
 270                 mux {
 271                         function = "pmic";
 272                         groups = "pmic_bus";
 273                 };
 274         };
 275
 276         pwm7_pins: pwm1-2-pins {
 277                 mux {
 278                         function = "pwm";
 279                         groups = "pwm_ch7_2";
 280                 };
 281         };
 282
 283         wled_pins: wled-pins {
 284                 mux {
 285                         function = "led";
 286                         groups = "wled";
 287                 };
 288         };
 289
 290         /* Serial NAND is shared pin with SPI-NOR */
 291         serial_nand_pins: serial-nand-pins {
 292                 mux {
 293                         function = "flash";
 294                         groups = "snfi";
 295                 };
 296         };
 297
 298         spic0_pins: spic0-pins {
 299                 mux {
 300                         function = "spi";
 301                         groups = "spic0_0";
 302                 };
 303         };
 304
 305         spic1_pins: spic1-pins {
 306                 mux {
 307                         function = "spi";
 308                         groups = "spic1_0";
 309                 };
 310         };
 311
 312         uart0_pins: uart0-pins {
 313                 mux {
 314                         function = "uart";
 315                         groups = "uart0_0_tx_rx";
 316                 };
 317         };
 318
 319         uart2_pins: uart2-pins {
 320                 mux {
 321                         function = "uart";
 322                         groups = "uart2_1_tx_rx";
 323                 };
 324         };
 325
 326         watchdog_pins: watchdog-pins {
 327                 mux {
 328                         function = "watchdog";
 329                         groups = "watchdog";
 330                 };
 331         };
 332 };
 333
 334 &pwm {
 335         pinctrl-names = "default";
 336         pinctrl-0 = <&pwm7_pins>;
 337         status = "okay";
 338 };
 339
 340 &pwrap {
 341         pinctrl-names = "default";
 342         pinctrl-0 = <&pmic_bus_pins>;
 343         status = "okay";
 344 };
 345
 346 &rtc {
 347         status = "disabled";
 348 };
 349
 350 &sata {
 351         status = "disabled";
 352 };
 353
 354 &sata_phy {
 355         status = "disabled";
 356 };
 357
 358 &slot0 {
 359         wmac1: mt7915@0,0 {
 360                 reg = <0x0000 0 0 0 0>;
 361                 ieee80211-freq-limit = <5000000 6000000>;
 362         };
 363 };
 364
 365 &snfi {
 366         pinctrl-names = "default";
 367         pinctrl-0 = <&serial_nand_pins>;
 368         status = "okay";
 369
 370         snand: flash@0 {
 371                 compatible = "spi-nand";
 372                 mediatek,bmt-table-size = <0x1000>;
 373                 mediatek,bmt-v2;
 374                 nand-ecc-engine = <&snfi>;
 375                 reg = <0>;
 376                 spi-rx-bus-width = <4>;
 377                 spi-tx-bus-width = <4>;
 378
 379                 partitions {
 380                         compatible = "fixed-partitions";
 381                         #address-cells = <1>;
 382                         #size-cells = <1>;
 383
 384                         partition@0 {
 385                                 label = "Preloader";
 386                                 reg = <0x00000 0x0080000>;
 387                                 read-only;
 388                         };
 389
 390                         partition@80000 {
 391                                 label = "ATF";
 392                                 reg = <0x80000 0x0040000>;
 393                                 read-only;
 394                         };
 395
 396                         partition@c0000 {
 397                                 label = "Bootloader";
 398                                 reg = <0xc0000 0x0080000>;
 399                                 read-only;
 400                         };
 401
 402                         partition@140000 {
 403                                 label = "Config";
 404                                 reg = <0x140000 0x0080000>;
 405                         };
 406
 407                         factory: partition@1c0000 {
 408                                 compatible = "nvmem-cells";
 409                                 label = "Factory";
 410                                 reg = <0x1c0000 0x0100000>;
 411                                 #address-cells = <1>;
 412                                 #size-cells = <1>;
 413                                 read-only;
 414
 415                                 macaddr_factory_7fff4: macaddr@7fff4 {
 416                                         reg = <0x7fff4 0x6>;
 417                                 };
 418
 419                                 macaddr_factory_7fffa: macaddr@7fffa {
 420                                         reg = <0x7fffa 0x6>;
 421                                 };
 422                         };
 423
 424                         partition@2c0000 {
 425                                 label = "firmware";
 426                                 reg = <0x2c0000 0x2600000>;
 427
 428                                 compatible = "fixed-partitions";
 429                                 #address-cells = <1>;
 430                                 #size-cells = <1>;
 431
 432                                 partition@0 {
 433                                         label = "kernel";
 434                                         reg = <0x0 0x600000>;
 435                                 };
 436
 437                                 partition@600000 {
 438                                         label = "ubi";
 439                                         reg = <0x600000 0x2000000>;
 440                                 };
 441                         };
 442
 443                         partition@28c0000 {
 444                                 label = "firmware_backup";
 445                                 reg = <0x28c0000 0x2600000>;
 446                                 read-only;
 447                         };
 448
 449                         partition@4ec0000 {
 450                                 label = "CFG";
 451                                 reg = <0x4ec0000 0x800000>;
 452                                 read-only;
 453                         };
 454
 455                         partition@56c0000 {
 456                                 label = "RAE";
 457                                 reg = <0x56c0000 0x400000>;
 458                                 read-only;
 459                         };
 460
 461                         partition@5ac0000 {
 462                                 label = "POT";
 463                                 reg = <0x5ac0000 0x100000>;
 464                                 read-only;
 465                         };
 466
 467                         partition@5bc0000 {
 468                                 label = "Language";
 469                                 reg = <0x5bc0000 0x400000>;
 470                                 read-only;
 471                         };
 472
 473                         partition@5fc0000 {
 474                                 label = "Traffic";
 475                                 reg = <0x5fc0000 0x200000>;
 476                                 read-only;
 477                         };
 478
 479                         partition@61c0000 {
 480                                 label = "Cert";
 481                                 reg = <0x61c0000 0x100000>;
 482                                 read-only;
 483                         };
 484
 485                         partition@62c0000 {
 486                                 label = "NTGRcryptK";
 487                                 reg = <0x62c0000 0x100000>;
 488                                 read-only;
 489                         };
 490
 491                         partition@63c0000 {
 492                                 label = "NTGRcryptD";
 493                                 reg = <0x63c0000 0x500000>;
 494                                 read-only;
 495                         };
 496
 497                         partition@68c0000 {
 498                                 label = "LOG";
 499                                 reg = <0x68c0000 0x100000>;
 500                                 read-only;
 501                         };
 502
 503                         partition@69c0000 {
 504                                 label = "User_data";
 505                                 reg = <0x69c0000 0x640000>;
 506                                 read-only;
 507                         };
 508
 509                 };
 510         };
 511 };
 512
 513 &spi0 {
 514         pinctrl-names = "default";
 515         pinctrl-0 = <&spic0_pins>;
 516         status = "okay";
 517 };
 518
 519 &spi1 {
 520         pinctrl-names = "default";
 521         pinctrl-0 = <&spic1_pins>;
 522         status = "okay";
 523 };
 524
 525 &ssusb {
 526         status = "disabled";
 527 };
 528
 529 &u3phy {
 530         status = "disabled";
 531 };
 532
 533 &uart0 {
 534         pinctrl-names = "default";
 535         pinctrl-0 = <&uart0_pins>;
 536         status = "okay";
 537 };
 538
 539 &uart2 {
 540         pinctrl-names = "default";
 541         pinctrl-0 = <&uart2_pins>;
 542         status = "okay";
 543 };
 544
 545 &watchdog {
 546         pinctrl-names = "default";
 547         pinctrl-0 = <&watchdog_pins>;
 548         status = "okay";
 549 };
 550
 551 &wmac {
 552         mediatek,mtd-eeprom = <&factory 0x0000>;
 553         status = "okay";
 554 };
 555
 556 &wmac1 {
 557         mediatek,mtd-eeprom = <&factory 0x05000>;
 558 };