25ba71da00ef09ff0283174ffac35cdac220c58f
[openwrt/staging/noltari.git] / target / linux / ipq806x / files-5.15 / arch / arm / boot / dts / qcom-ipq8064-onhub.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2014 The ChromiumOS Authors
4 */
5
6 #include "qcom-ipq8064-smb208.dtsi"
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/soc/qcom,tcsr.h>
9
10 / {
11 aliases {
12 ethernet0 = &gmac0;
13 ethernet1 = &gmac2;
14 mdio-gpio0 = &mdio;
15 serial0 = &gsbi4_serial;
16 };
17
18 chosen {
19 stdout-path = "serial0:115200n8";
20 };
21
22 reserved-memory {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 ranges;
26
27 rsvd@41200000 {
28 reg = <0x41200000 0x300000>;
29 no-map;
30 };
31 };
32
33 mdio: mdio {
34 compatible = "virtual,mdio-gpio";
35 #address-cells = <1>;
36 #size-cells = <0>;
37 gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
38 <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
39 pinctrl-0 = <&mdio_pins>;
40 pinctrl-names = "default";
41
42 phy0: ethernet-phy@0 {
43 reg = <0>;
44 qca,ar8327-initvals = <
45 0x00004 0x7600000 /* PAD0_MODE */
46 0x00008 0x1000000 /* PAD5_MODE */
47 0x0000c 0x80 /* PAD6_MODE */
48 0x000e4 0xaa545 /* MAC_POWER_SEL */
49 0x000e0 0xc74164de /* SGMII_CTRL */
50 0x0007c 0x4e /* PORT0_STATUS */
51 0x00094 0x4e /* PORT6_STATUS */
52 >;
53 };
54
55 phy1: ethernet-phy@1 {
56 reg = <1>;
57 };
58 };
59
60 soc {
61 rng@1a500000 {
62 status = "disabled";
63 };
64
65 sound {
66 compatible = "google,storm-audio";
67 qcom,model = "ipq806x-storm";
68 cpu = <&lpass>;
69 codec = <&max98357a>;
70 };
71
72 lpass: lpass@28100000 {
73 status = "okay";
74 pinctrl-names = "default", "idle";
75 pinctrl-0 = <&mi2s_default>;
76 pinctrl-1 = <&mi2s_idle>;
77 };
78
79 max98357a: max98357a {
80 compatible = "maxim,max98357a";
81 #sound-dai-cells = <1>;
82 pinctrl-names = "default";
83 pinctrl-0 = <&sdmode_pins>;
84 sdmode-gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
85 };
86 };
87 };
88
89 &qcom_pinmux {
90 rgmii0_pins: rgmii0_pins {
91 mux {
92 pins = "gpio2", "gpio66";
93 drive-strength = <8>;
94 bias-disable;
95 };
96 };
97 mi2s_pins {
98 mi2s_default: mi2s_default {
99 dout {
100 pins = "gpio32";
101 function = "mi2s";
102 drive-strength = <16>;
103 bias-disable;
104 };
105 sync {
106 pins = "gpio27";
107 function = "mi2s";
108 drive-strength = <16>;
109 bias-disable;
110 };
111 clk {
112 pins = "gpio28";
113 function = "mi2s";
114 drive-strength = <16>;
115 bias-disable;
116 };
117 };
118 mi2s_idle: mi2s_idle {
119 dout {
120 pins = "gpio32";
121 function = "mi2s";
122 drive-strength = <2>;
123 bias-pull-down;
124 };
125 sync {
126 pins = "gpio27";
127 function = "mi2s";
128 drive-strength = <2>;
129 bias-pull-down;
130 };
131 clk {
132 pins = "gpio28";
133 function = "mi2s";
134 drive-strength = <2>;
135 bias-pull-down;
136 };
137 };
138 };
139
140 mdio_pins: mdio_pins {
141 mux {
142 pins = "gpio0", "gpio1";
143 function = "gpio";
144 drive-strength = <8>;
145 bias-disable;
146 };
147 rst {
148 pins = "gpio26";
149 output-low;
150 };
151 };
152
153 sdmode_pins: sdmode_pinmux {
154 pins = "gpio25";
155 function = "gpio";
156 drive-strength = <16>;
157 bias-disable;
158 };
159
160 sdcc1_pins: sdcc1_pinmux {
161 mux {
162 pins = "gpio38", "gpio39", "gpio40",
163 "gpio41", "gpio42", "gpio43",
164 "gpio44", "gpio45", "gpio46",
165 "gpio47";
166 function = "sdc1";
167 };
168 cmd {
169 pins = "gpio45";
170 drive-strength = <10>;
171 bias-pull-up;
172 };
173 data {
174 pins = "gpio38", "gpio39", "gpio40",
175 "gpio41", "gpio43", "gpio44",
176 "gpio46", "gpio47";
177 drive-strength = <10>;
178 bias-pull-up;
179 };
180 clk {
181 pins = "gpio42";
182 drive-strength = <16>;
183 bias-pull-down;
184 };
185 };
186
187 i2c1_pins: i2c1_pinmux {
188 pins = "gpio53", "gpio54";
189 function = "gsbi1";
190 bias-disable;
191 };
192
193 rpm_i2c_pinmux: rpm_i2c_pinmux {
194 mux {
195 pins = "gpio12", "gpio13";
196 function = "gsbi4";
197 drive-strength = <12>;
198 bias-disable;
199 };
200 };
201
202 spi_pins: spi_pins {
203 mux {
204 pins = "gpio18", "gpio19", "gpio21";
205 function = "gsbi5";
206 bias-pull-down;
207 /delete-property/ bias-none;
208 /delete-property/ drive-strength;
209 };
210 data {
211 pins = "gpio18", "gpio19";
212 drive-strength = <10>;
213 };
214 cs {
215 pins = "gpio20";
216 drive-strength = <10>;
217 bias-pull-up;
218 };
219 clk {
220 pins = "gpio21";
221 drive-strength = <12>;
222 };
223 };
224
225 fw_pinmux {
226 wp {
227 pins = "gpio17";
228 output-low;
229 };
230 recovery {
231 pins = "gpio16";
232 bias-none;
233 };
234 developer {
235 pins = "gpio15";
236 bias-none;
237 };
238 };
239
240 spi6_pins: spi6_pins {
241 mux {
242 pins = "gpio55", "gpio56", "gpio58";
243 function = "gsbi6";
244 bias-pull-down;
245 };
246 data {
247 pins = "gpio55", "gpio56";
248 drive-strength = <10>;
249 };
250 cs {
251 pins = "gpio57";
252 drive-strength = <10>;
253 bias-pull-up;
254 output-high;
255 };
256 clk {
257 pins = "gpio58";
258 drive-strength = <12>;
259 };
260 };
261 };
262
263 &gmac0 {
264 status = "okay";
265 phy-mode = "rgmii";
266 qcom,id = <0>;
267 phy-handle = <&phy1>;
268
269 pinctrl-0 = <&rgmii0_pins>;
270 pinctrl-names = "default";
271
272 fixed-link {
273 speed = <1000>;
274 full-duplex;
275 };
276 };
277
278 &gmac2 {
279 status = "okay";
280 phy-mode = "sgmii";
281 qcom,id = <2>;
282 phy-handle = <&phy0>;
283
284 fixed-link {
285 speed = <1000>;
286 full-duplex;
287 };
288 };
289
290 &gsbi1 {
291 status = "okay";
292 qcom,mode = <GSBI_PROT_I2C_UART>;
293 };
294
295 &gsbi1_i2c {
296 status = "okay";
297
298 clock-frequency = <100000>;
299
300 pinctrl-0 = <&i2c1_pins>;
301 pinctrl-names = "default";
302
303 tpm@20 {
304 compatible = "infineon,slb9645tt";
305 reg = <0x20>;
306 powered-while-suspended;
307 };
308 };
309
310 &gsbi4 {
311 status = "okay";
312 qcom,mode = <GSBI_PROT_I2C_UART>;
313 };
314
315 &gsbi4_serial {
316 status = "okay";
317 };
318
319 &gsbi5 {
320 status = "okay";
321 qcom,mode = <GSBI_PROT_SPI>;
322
323 spi4: spi@1a280000 {
324 status = "okay";
325 spi-max-frequency = <50000000>;
326 pinctrl-0 = <&spi_pins>;
327 pinctrl-names = "default";
328
329 cs-gpios = <&qcom_pinmux 20 0>;
330
331 flash: flash@0 {
332 compatible = "jedec,spi-nor";
333 spi-max-frequency = <50000000>;
334 reg = <0>;
335 };
336 };
337 };
338
339 &gsbi6 {
340 status = "okay";
341 qcom,mode = <GSBI_PROT_SPI>;
342 };
343
344 &gsbi6_spi {
345 status = "okay";
346 spi-max-frequency = <25000000>;
347
348 pinctrl-0 = <&spi6_pins>;
349 pinctrl-names = "default";
350
351 cs-gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
352
353 dmas = <&adm_dma 8 0xb>,
354 <&adm_dma 7 0x14>;
355 dma-names = "rx", "tx";
356
357 /*
358 * This "spidev" was included in the manufacturer device tree. I suspect
359 * it's the (unused) Zigbee radio -- SiliconLabs EM3581 Zigbee? There's
360 * no driver or binding for this at the moment.
361 */
362 spidev@0 {
363 compatible = "spidev";
364 reg = <0>;
365 spi-max-frequency = <25000000>;
366 };
367 };
368
369 &pcie0 {
370 status = "okay";
371
372 pcie@0 {
373 reg = <0 0 0 0 0>;
374 #interrupt-cells = <1>;
375 #size-cells = <2>;
376 #address-cells = <3>;
377 device_type = "pci";
378
379 ath10k@0,0 {
380 reg = <0 0 0 0 0>;
381 device_type = "pci";
382 qcom,ath10k-sa-gpio = <2 3 4 0>;
383 qcom,ath10k-sa-gpio-func = <5 5 5 0>;
384 };
385 };
386 };
387
388 &pcie1 {
389 status = "okay";
390
391 pcie@0 {
392 reg = <0 0 0 0 0>;
393 #interrupt-cells = <1>;
394 #size-cells = <2>;
395 #address-cells = <3>;
396 device_type = "pci";
397
398 ath10k@0,0 {
399 reg = <0 0 0 0 0>;
400 device_type = "pci";
401 qcom,ath10k-sa-gpio = <2 3 4 0>;
402 qcom,ath10k-sa-gpio-func = <5 5 5 0>;
403 };
404 };
405 };
406
407 &pcie2 {
408 status = "okay";
409
410 pcie@0 {
411 reg = <0 0 0 0 0>;
412 #interrupt-cells = <1>;
413 #size-cells = <2>;
414 #address-cells = <3>;
415 device_type = "pci";
416
417 ath10k@0,0 {
418 reg = <0 0 0 0 0>;
419 device_type = "pci";
420 };
421 };
422 };
423
424 &rpm {
425 pinctrl-0 = <&rpm_i2c_pinmux>;
426 pinctrl-names = "default";
427 };
428
429 &sdcc1 {
430 status = "okay";
431 pinctrl-0 = <&sdcc1_pins>;
432 pinctrl-names = "default";
433 /delete-property/ mmc-ddr-1_8v;
434 };
435
436 &tcsr {
437 compatible = "qcom,tcsr-ipq8064", "qcom,tcsr", "syscon";
438 qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
439 };
440
441 &hs_phy_0 {
442 status = "okay";
443 };
444
445 &ss_phy_0 {
446 status = "okay";
447 };
448
449 &usb3_0 {
450 status = "okay";
451 };
452
453 &hs_phy_1 {
454 status = "okay";
455 };
456
457 &ss_phy_1 {
458 status = "okay";
459 };
460
461 &usb3_1 {
462 status = "okay";
463 };