target/linux/generic/backport-5.15/733-v6.2-03-net-mediatek-sgmii-fix-duplex-configuration.patch

   1 From 9d32637122de88f1ef614c29703f0e050cad342e Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Bj=C3=B8rn=20Mork?= <bjorn@mork.no>
   3 Date: Wed, 1 Feb 2023 19:23:30 +0100
   4 Subject: [PATCH] net: mediatek: sgmii: fix duplex configuration
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 The logic of the duplex bit is inverted.  Setting it means half
  10 duplex, not full duplex.
  11
  12 Fix and rename macro to avoid confusion.
  13
  14 Fixes: 7e538372694b ("net: ethernet: mediatek: Re-add support SGMII")
  15 Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
  16 Signed-off-by: Bjørn Mork <bjorn@mork.no>
  17 Acked-by: Daniel Golle <daniel@makrotopia.org>
  18 Tested-by: Daniel Golle <daniel@makrotopia.org>
  19 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  20 ---
  21  drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 +-
  22  drivers/net/ethernet/mediatek/mtk_sgmii.c   | 6 +++---
  23  2 files changed, 4 insertions(+), 4 deletions(-)
  24
  25 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  26 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  27 @@ -496,7 +496,7 @@
  28  #define SGMII_SPEED_10                 FIELD_PREP(SGMII_SPEED_MASK, 0)
  29  #define SGMII_SPEED_100                        FIELD_PREP(SGMII_SPEED_MASK, 1)
  30  #define SGMII_SPEED_1000               FIELD_PREP(SGMII_SPEED_MASK, 2)
  31 -#define SGMII_DUPLEX_FULL              BIT(4)
  32 +#define SGMII_DUPLEX_HALF              BIT(4)
  33  #define SGMII_IF_MODE_BIT5             BIT(5)
  34  #define SGMII_REMOTE_FAULT_DIS         BIT(8)
  35  #define SGMII_CODE_SYNC_SET_VAL                BIT(9)
  36 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
  37 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
  38 @@ -66,7 +66,7 @@ static int mtk_pcs_setup_mode_force(stru
  39
  40         /* Set the speed etc but leave the duplex unchanged */
  41         regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
  42 -       val &= SGMII_DUPLEX_FULL | ~SGMII_IF_MODE_MASK;
  43 +       val &= SGMII_DUPLEX_HALF | ~SGMII_IF_MODE_MASK;
  44         val |= SGMII_SPEED_1000;
  45         regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
  46
  47 @@ -131,9 +131,10 @@ static void mtk_pcs_link_up(struct phyli
  48
  49         /* SGMII force duplex setting */
  50         regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
  51 -       val &= ~SGMII_DUPLEX_FULL;
  52 -       if (duplex == DUPLEX_FULL)
  53 -               val |= SGMII_DUPLEX_FULL;
  54 +
  55 +       val &= ~SGMII_DUPLEX_HALF;
  56 +       if (duplex != DUPLEX_FULL)
  57 +               val |= SGMII_DUPLEX_HALF;
  58
  59         regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
  60  }