1 From ea38222fd189a74710f733b7175eea314c0a34d2 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jonas.gorski@gmail.com>
3 Date: Fri, 24 Jun 2016 22:14:13 +0200
4 Subject: [PATCH] pinctrl: add a pincontrol driver for BCM6348
6 Add a pincotrol driver for BCM6348. BCM6348 allow muxing five groups of
7 up to eight gpios into fourteen potential functions. It does not allow
8 muxing individual pins. Some functions require more than one group to be
9 muxed to the same function.
11 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
13 drivers/pinctrl/bcm63xx/Kconfig | 7 +
14 drivers/pinctrl/bcm63xx/Makefile | 1 +
15 drivers/pinctrl/bcm63xx/pinctrl-bcm6348.c | 433 ++++++++++++++++++++++++++++++
16 3 files changed, 441 insertions(+)
17 create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm6348.c
19 --- a/drivers/pinctrl/bcm63xx/Kconfig
20 +++ b/drivers/pinctrl/bcm63xx/Kconfig
21 @@ -8,3 +8,10 @@ config PINCTRL_BCM6328
23 select PINCTRL_BCM63XX
24 select GENERIC_PINCONF
26 +config PINCTRL_BCM6348
27 + bool "BCM6348 pincontrol driver" if COMPILE_TEST
30 + select PINCTRL_BCM63XX
31 + select GENERIC_PINCONF
32 --- a/drivers/pinctrl/bcm63xx/Makefile
33 +++ b/drivers/pinctrl/bcm63xx/Makefile
35 obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o
36 obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o
37 +obj-$(CONFIG_PINCTRL_BCM6348) += pinctrl-bcm6348.o
39 +++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6348.c
42 + * This file is subject to the terms and conditions of the GNU General Public
43 + * License. See the file "COPYING" in the main directory of this archive
46 + * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>
49 +#include <linux/kernel.h>
50 +#include <linux/spinlock.h>
51 +#include <linux/bitops.h>
52 +#include <linux/gpio.h>
53 +#include <linux/of.h>
54 +#include <linux/of_gpio.h>
55 +#include <linux/slab.h>
56 +#include <linux/platform_device.h>
58 +#include <linux/pinctrl/machine.h>
59 +#include <linux/pinctrl/pinconf.h>
60 +#include <linux/pinctrl/pinconf-generic.h>
61 +#include <linux/pinctrl/pinmux.h>
64 +#include "../pinctrl-utils.h"
66 +#include "pinctrl-bcm63xx.h"
68 +#define BCM6348_NGPIO 37
71 +#define PINS_PER_GROUP 8
72 +#define PIN_TO_GROUP(pin) (MAX_GROUP - ((pin) / PINS_PER_GROUP))
73 +#define GROUP_SHIFT(pin) (PIN_TO_GROUP(pin) * 4)
74 +#define GROUP_MASK(pin) (0xf << GROUP_SHIFT(pin))
76 +struct bcm6348_pingroup {
78 + const unsigned * const pins;
79 + const unsigned num_pins;
82 +struct bcm6348_function {
84 + const char * const *groups;
85 + const unsigned num_groups;
89 +struct bcm6348_pinctrl {
91 + struct pinctrl_dev *pctldev;
92 + struct pinctrl_desc desc;
98 + unsigned long requested[2];
100 + struct gpio_chip gpio[2];
103 +static const struct pinctrl_pin_desc bcm6348_pins[] = {
105 + PINCTRL_PIN(0, "gpio0"),
106 + PINCTRL_PIN(1, "gpio1"),
107 + PINCTRL_PIN(2, "gpio2"),
108 + PINCTRL_PIN(3, "gpio3"),
109 + PINCTRL_PIN(4, "gpio4"),
110 + PINCTRL_PIN(5, "gpio5"),
111 + PINCTRL_PIN(6, "gpio6"),
112 + PINCTRL_PIN(7, "gpio7"),
114 + PINCTRL_PIN(8, "gpio8"),
115 + PINCTRL_PIN(9, "gpio9"),
116 + PINCTRL_PIN(10, "gpio10"),
117 + PINCTRL_PIN(11, "gpio11"),
118 + PINCTRL_PIN(12, "gpio12"),
119 + PINCTRL_PIN(13, "gpio13"),
120 + PINCTRL_PIN(14, "gpio14"),
121 + PINCTRL_PIN(15, "gpio15"),
123 + PINCTRL_PIN(16, "gpio16"),
124 + PINCTRL_PIN(17, "gpio17"),
125 + PINCTRL_PIN(18, "gpio18"),
126 + PINCTRL_PIN(19, "gpio19"),
127 + PINCTRL_PIN(20, "gpio20"),
128 + PINCTRL_PIN(21, "gpio21"),
129 + PINCTRL_PIN(22, "gpio22"),
130 + PINCTRL_PIN(23, "gpio23"),
132 + PINCTRL_PIN(24, "gpio24"),
133 + PINCTRL_PIN(25, "gpio25"),
134 + PINCTRL_PIN(26, "gpio26"),
135 + PINCTRL_PIN(27, "gpio27"),
136 + PINCTRL_PIN(28, "gpio28"),
137 + PINCTRL_PIN(29, "gpio29"),
138 + PINCTRL_PIN(30, "gpio30"),
139 + PINCTRL_PIN(31, "gpio31"),
141 + PINCTRL_PIN(32, "gpio32"),
142 + PINCTRL_PIN(33, "gpio33"),
143 + PINCTRL_PIN(34, "gpio34"),
144 + PINCTRL_PIN(35, "gpio35"),
145 + PINCTRL_PIN(36, "gpio36"),
148 +enum bcm6348_muxes {
149 + BCM6348_MUX_GPIO = 0,
150 + BCM6348_MUX_EXT_EPHY,
151 + BCM6348_MUX_MII_SNOOP,
152 + BCM6348_MUX_LEGACY_LED,
153 + BCM6348_MUX_MII_PCCARD,
155 + BCM6348_MUX_SPI_MASTER_UART,
156 + BCM6348_MUX_EXT_MII,
157 + BCM6348_MUX_UTOPIA,
161 +static unsigned group0_pins[] = {
162 + 32, 33, 34, 35, 36,
165 +static unsigned group1_pins[] = {
166 + 24, 25, 26, 27, 28, 29, 30, 31,
169 +static unsigned group2_pins[] = {
170 + 16, 17, 18, 19, 20, 21, 22, 23,
173 +static unsigned group3_pins[] = {
174 + 8, 9, 10, 11, 12, 13, 14, 15,
177 +static unsigned group4_pins[] = {
178 + 0, 1, 2, 3, 4, 5, 6, 7,
181 +#define BCM6348_GROUP(n) \
184 + .pins = n##_pins, \
185 + .num_pins = ARRAY_SIZE(n##_pins), \
188 +static struct bcm6348_pingroup bcm6348_groups[] = {
189 + BCM6348_GROUP(group0),
190 + BCM6348_GROUP(group1),
191 + BCM6348_GROUP(group2),
192 + BCM6348_GROUP(group3),
193 + BCM6348_GROUP(group4),
196 +static const char * const ext_mii_groups[] = {
201 +static const char * const ext_ephy_groups[] = {
206 +static const char * const mii_snoop_groups[] = {
211 +static const char * const legacy_led_groups[] = {
215 +static const char * const mii_pccard_groups[] = {
219 +static const char * const pci_groups[] = {
223 +static const char * const spi_master_uart_groups[] = {
227 +static const char * const utopia_groups[] = {
233 +static const char * const diag_groups[] = {
240 +#define BCM6348_FUN(n, f) \
243 + .groups = n##_groups, \
244 + .num_groups = ARRAY_SIZE(n##_groups), \
245 + .value = BCM6348_MUX_##f, \
248 +static const struct bcm6348_function bcm6348_funcs[] = {
249 + BCM6348_FUN(ext_mii, EXT_MII),
250 + BCM6348_FUN(ext_ephy, EXT_EPHY),
251 + BCM6348_FUN(mii_snoop, MII_SNOOP),
252 + BCM6348_FUN(legacy_led, LEGACY_LED),
253 + BCM6348_FUN(mii_pccard, MII_PCCARD),
254 + BCM6348_FUN(pci, PCI),
255 + BCM6348_FUN(spi_master_uart, SPI_MASTER_UART),
256 + BCM6348_FUN(utopia, UTOPIA),
257 + BCM6348_FUN(diag, DIAG),
260 +static int bcm6348_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
262 + return ARRAY_SIZE(bcm6348_groups);
265 +static const char *bcm6348_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
268 + return bcm6348_groups[group].name;
271 +static int bcm6348_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
272 + unsigned group, const unsigned **pins,
273 + unsigned *num_pins)
275 + *pins = bcm6348_groups[group].pins;
276 + *num_pins = bcm6348_groups[group].num_pins;
281 +static int bcm6348_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
283 + return ARRAY_SIZE(bcm6348_funcs);
286 +static const char *bcm6348_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
289 + return bcm6348_funcs[selector].name;
292 +static int bcm6348_pinctrl_get_groups(struct pinctrl_dev *pctldev,
294 + const char * const **groups,
295 + unsigned * const num_groups)
297 + *groups = bcm6348_funcs[selector].groups;
298 + *num_groups = bcm6348_funcs[selector].num_groups;
303 +static void bcm6348_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
304 + struct seq_file *s,
307 + seq_printf(s, " %s", dev_name(pctldev->dev));
310 +static void bcm6348_rmw_mux(struct bcm6348_pinctrl *pctl, u32 mask, u32 val)
312 + unsigned long flags;
315 + spin_lock_irqsave(&pctl->lock, flags);
317 + reg = __raw_readl(pctl->mode);
320 + __raw_writel(reg, pctl->mode);
322 + spin_unlock_irqrestore(&pctl->lock, flags);
325 +static int bcm6348_pinctrl_set_mux(struct pinctrl_dev *pctldev,
326 + unsigned selector, unsigned group)
328 + struct bcm6348_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
329 + const struct bcm6348_pingroup *grp = &bcm6348_groups[group];
330 + const struct bcm6348_function *f = &bcm6348_funcs[selector];
334 + * pins n..(n+7) share the same group, so we only need to look at
337 + mask = GROUP_MASK(grp->pins[0]);
338 + val = f->value << GROUP_SHIFT(grp->pins[0]);
340 + bcm6348_rmw_mux(pctl, mask, val);
345 +static int bcm6348_pinctrl_request(struct pinctrl_dev *pctldev,
348 + struct bcm6348_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
350 + if (test_and_set_bit(offset, pctl->requested))
356 +static int bcm6348_pinctrl_free(struct pinctrl_dev *pctldev,
359 + struct bcm6348_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
361 + clear_bit(offset, pctl->requested);
366 +static int bcm6348_gpio_request_enable(struct pinctrl_dev *pctldev,
367 + struct pinctrl_gpio_range *range,
370 + struct bcm6348_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
373 + /* gpio 22 is the ready gpio for pcmcia, always allow gpio on it */
377 + if (test_and_set_bit(offset, pctl->requested))
380 + mask = GROUP_MASK(offset);
382 + /* disable all functions using this pin */
383 + bcm6348_rmw_mux(pctl, mask, 0);
388 +static void bcm6348_gpio_disable_free(struct pinctrl_dev *pctldev,
389 + struct pinctrl_gpio_range *range,
392 + struct bcm6348_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
394 + clear_bit(offset, pctl->requested);
397 +static struct pinctrl_ops bcm6348_pctl_ops = {
398 + .get_groups_count = bcm6348_pinctrl_get_group_count,
399 + .get_group_name = bcm6348_pinctrl_get_group_name,
400 + .get_group_pins = bcm6348_pinctrl_get_group_pins,
402 + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
403 + .dt_free_map = pinctrl_utils_dt_free_map,
405 + .pin_dbg_show = bcm6348_pinctrl_pin_dbg_show,
408 +static struct pinmux_ops bcm6348_pmx_ops = {
409 + .request = bcm6348_pinctrl_request,
410 + .free = bcm6348_pinctrl_free,
411 + .get_functions_count = bcm6348_pinctrl_get_func_count,
412 + .get_function_name = bcm6348_pinctrl_get_func_name,
413 + .get_function_groups = bcm6348_pinctrl_get_groups,
414 + .set_mux = bcm6348_pinctrl_set_mux,
415 + .gpio_request_enable = bcm6348_gpio_request_enable,
416 + .gpio_disable_free = bcm6348_gpio_disable_free,
419 +static int bcm6348_pinctrl_probe(struct platform_device *pdev)
421 + struct bcm6348_pinctrl *pctl;
422 + struct resource *res;
423 + void __iomem *mode;
425 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mode");
426 + mode = devm_ioremap_resource(&pdev->dev, res);
428 + return PTR_ERR(mode);
430 + pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
434 + spin_lock_init(&pctl->lock);
438 + /* disable all muxes by default */
439 + __raw_writel(0, pctl->mode);
441 + pctl->desc.name = dev_name(&pdev->dev);
442 + pctl->desc.owner = THIS_MODULE;
443 + pctl->desc.pctlops = &bcm6348_pctl_ops;
444 + pctl->desc.pmxops = &bcm6348_pmx_ops;
445 + pctl->dev = &pdev->dev;
447 + pctl->desc.npins = ARRAY_SIZE(bcm6348_pins);
448 + pctl->desc.pins = bcm6348_pins;
450 + platform_set_drvdata(pdev, pctl);
452 + pctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl,
453 + pctl->gpio, BCM6348_NGPIO);
454 + if (IS_ERR(pctl->pctldev))
455 + return PTR_ERR(pctl->pctldev);
460 +static const struct of_device_id bcm6348_pinctrl_match[] = {
461 + { .compatible = "brcm,bcm6348-pinctrl", },
465 +static struct platform_driver bcm6348_pinctrl_driver = {
466 + .probe = bcm6348_pinctrl_probe,
468 + .name = "bcm6348-pinctrl",
469 + .of_match_table = bcm6348_pinctrl_match,
473 +builtin_platform_driver(bcm6348_pinctrl_driver);