1 From 8079cfba4c7b8cae900c27104b4512fa5ed1f021 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
3 Date: Wed, 17 Jun 2020 12:50:37 +0200
4 Subject: [PATCH 5/9] mips: bmips: dts: add BCM6358 reset controller support
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 BCM6358 SoCs have a reset controller for certain components.
11 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
12 Acked-by: Florian Fainelli <f.fainelli@gmail.com>
13 Reviewed-by: Rob Herring <robh@kernel.org>
14 Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
16 arch/mips/boot/dts/brcm/bcm6358.dtsi | 6 ++++++
17 include/dt-bindings/reset/bcm6358-reset.h | 15 +++++++++++++++
18 2 files changed, 21 insertions(+)
19 create mode 100644 include/dt-bindings/reset/bcm6358-reset.h
21 --- a/arch/mips/boot/dts/brcm/bcm6358.dtsi
22 +++ b/arch/mips/boot/dts/brcm/bcm6358.dtsi
24 interrupts = <2>, <3>;
27 + periph_rst: reset-controller@fffe0034 {
28 + compatible = "brcm,bcm6345-reset";
29 + reg = <0xfffe0034 0x4>;
33 leds0: led-controller@fffe00d0 {
37 +++ b/include/dt-bindings/reset/bcm6358-reset.h
39 +/* SPDX-License-Identifier: GPL-2.0+ */
41 +#ifndef __DT_BINDINGS_RESET_BCM6358_H
42 +#define __DT_BINDINGS_RESET_BCM6358_H
44 +#define BCM6358_RST_SPI 0
45 +#define BCM6358_RST_ENET 2
46 +#define BCM6358_RST_MPI 3
47 +#define BCM6358_RST_EPHY 6
48 +#define BCM6358_RST_SAR 7
49 +#define BCM6358_RST_USBH 12
50 +#define BCM6358_RST_PCM 13
51 +#define BCM6358_RST_ADSL 14
53 +#endif /* __DT_BINDINGS_RESET_BCM6358_H */