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bcm63xx: kernel: fix up bcm63268 roboswitch gpio registers
[openwrt/staging/noltari.git] / target / linux / bcm63xx / patches-5.15 / 339-MIPS-BCM63XX-add-support-for-BCM63268.patch
1 From 98f63141190ac02c58b78d58f771bd263c61d756 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jogo@openwrt.org>
3 Date: Sat, 7 Dec 2013 17:14:17 +0100
4 Subject: [PATCH 48/56] MIPS: BCM63XX: add support for BCM63268
5
6 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
7 ---
8 arch/mips/bcm63xx/Kconfig | 5 +
9 arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +-
10 arch/mips/bcm63xx/clk.c | 25 ++++-
11 arch/mips/bcm63xx/cpu.c | 59 +++++++++-
12 arch/mips/bcm63xx/dev-flash.c | 6 +
13 arch/mips/bcm63xx/dev-spi.c | 4 +-
14 arch/mips/bcm63xx/irq.c | 20 +++-
15 arch/mips/bcm63xx/reset.c | 21 ++++
16 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 130 ++++++++++++++++++++++
17 arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 2 +
18 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 79 +++++++++++++
19 arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 +
20 12 files changed, 342 insertions(+), 12 deletions(-)
21
22 --- a/arch/mips/bcm63xx/Kconfig
23 +++ b/arch/mips/bcm63xx/Kconfig
24 @@ -61,6 +61,11 @@ config BCM63XX_CPU_6368
25 select HAVE_PCI
26 select BCM63XX_OHCI
27 select BCM63XX_EHCI
28 +
29 +config BCM63XX_CPU_63268
30 + bool "support 63268 CPU"
31 + select SYS_HAS_CPU_BMIPS4350
32 + select HAVE_PCI
33 endmenu
34
35 source "arch/mips/bcm63xx/boards/Kconfig"
36 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
37 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
38 @@ -681,7 +681,7 @@ void __init board_prom_init(void)
39 /* read base address of boot chip select (0)
40 * 6328/6362 do not have MPI but boot from a fixed address
41 */
42 - if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
43 + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {
44 val = 0x18000000;
45 } else {
46 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
47 --- a/arch/mips/bcm63xx/clk.c
48 +++ b/arch/mips/bcm63xx/clk.c
49 @@ -52,6 +52,18 @@ static void bcm_hwclock_set(u32 mask, in
50 bcm_perf_writel(reg, PERF_CKCTL_REG);
51 }
52
53 +static void bcm_gpiorobosw_set(u32 mask, int enable)
54 +{
55 + u32 reg;
56 +
57 + reg = bcm_gpio_readl(GPIO_ROBOSW_SW_CTRL_REG);
58 + if (enable)
59 + reg |= mask;
60 + else
61 + reg &= ~mask;
62 + bcm_gpio_writel(reg, GPIO_ROBOSW_SW_CTRL_REG);
63 +}
64 +
65 /*
66 * Ethernet MAC "misc" clock: dma clocks and main clock on 6348
67 */
68 @@ -169,6 +181,10 @@ static void enetsw_set(struct clk *clk,
69 clk_disable_unlocked(&clk_swpkt_sar);
70 }
71 bcm_hwclock_set(CKCTL_6368_ROBOSW_EN, enable);
72 + } else if (BCMCPU_IS_63268()) {
73 + bcm_gpiorobosw_set(GPIO_ROBOSW_MII_DUMB_FWDG_EN |
74 + GPIO_ROBOSW_HW_FWDG_EN, enable);
75 + bcm_hwclock_set(CKCTL_63268_ROBOSW_EN, enable);
76 } else {
77 return;
78 }
79 @@ -214,6 +230,8 @@ static void usbh_set(struct clk *clk, in
80 bcm_hwclock_set(CKCTL_6362_USBH_EN, enable);
81 else if (BCMCPU_IS_6368())
82 bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
83 + else if (BCMCPU_IS_63268())
84 + bcm_hwclock_set(CKCTL_63268_USBH_EN, enable);
85 else
86 return;
87
88 @@ -236,6 +254,8 @@ static void usbd_set(struct clk *clk, in
89 bcm_hwclock_set(CKCTL_6362_USBD_EN, enable);
90 else if (BCMCPU_IS_6368())
91 bcm_hwclock_set(CKCTL_6368_USBD_EN, enable);
92 + else if (BCMCPU_IS_63268())
93 + bcm_hwclock_set(CKCTL_63268_USBD_EN, enable);
94 else
95 return;
96
97 @@ -262,9 +282,13 @@ static void spi_set(struct clk *clk, int
98 mask = CKCTL_6358_SPI_EN;
99 else if (BCMCPU_IS_6362())
100 mask = CKCTL_6362_SPI_EN;
101 - else
102 - /* BCMCPU_IS_6368 */
103 + else if (BCMCPU_IS_6368())
104 mask = CKCTL_6368_SPI_EN;
105 + else if (BCMCPU_IS_63268())
106 + mask = CKCTL_63268_SPI_EN;
107 + else
108 + return;
109 +
110 bcm_hwclock_set(mask, enable);
111 }
112
113 @@ -283,6 +307,8 @@ static void hsspi_set(struct clk *clk, i
114 mask = CKCTL_6328_HSSPI_EN;
115 else if (BCMCPU_IS_6362())
116 mask = CKCTL_6362_HSSPI_EN;
117 + else if (BCMCPU_IS_63268())
118 + mask = CKCTL_63268_HSSPI_EN;
119 else
120 return;
121
122 @@ -352,6 +378,8 @@ static void pcie_set(struct clk *clk, in
123 bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);
124 else if (BCMCPU_IS_6362())
125 bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable);
126 + else if (BCMCPU_IS_63268())
127 + bcm_hwclock_set(CKCTL_63268_PCIE_EN, enable);
128 }
129
130 static struct clk clk_pcie = {
131 @@ -550,6 +578,21 @@ static struct clk_lookup bcm6368_clks[]
132 CLKDEV_INIT(NULL, "ipsec", &clk_ipsec),
133 };
134
135 +static struct clk_lookup bcm63268_clks[] = {
136 + /* fixed rate clocks */
137 + CLKDEV_INIT(NULL, "periph", &clk_periph),
138 + CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
139 + CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
140 + CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
141 + /* gated clocks */
142 + CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
143 + CLKDEV_INIT(NULL, "usbh", &clk_usbh),
144 + CLKDEV_INIT(NULL, "usbd", &clk_usbd),
145 + CLKDEV_INIT(NULL, "spi", &clk_spi),
146 + CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
147 + CLKDEV_INIT(NULL, "pcie", &clk_pcie),
148 +};
149 +
150 #define HSSPI_PLL_HZ_6328 133333333
151 #define HSSPI_PLL_HZ_6362 400000000
152
153 @@ -582,6 +625,10 @@ static int __init bcm63xx_clk_init(void)
154 case BCM6368_CPU_ID:
155 clkdev_add_table(bcm6368_clks, ARRAY_SIZE(bcm6368_clks));
156 break;
157 + case BCM63268_CPU_ID:
158 + clk_hsspi_pll.rate = HSSPI_PLL_HZ_6362;
159 + clkdev_add_table(bcm63268_clks, ARRAY_SIZE(bcm63268_clks));
160 + break;
161 }
162
163 return 0;
164 --- a/arch/mips/bcm63xx/cpu.c
165 +++ b/arch/mips/bcm63xx/cpu.c
166 @@ -101,6 +101,15 @@ static const int bcm6368_irqs[] = {
167
168 };
169
170 +static const unsigned long bcm63268_regs_base[] = {
171 + __GEN_CPU_REGS_TABLE(63268)
172 +};
173 +
174 +static const int bcm63268_irqs[] = {
175 + __GEN_CPU_IRQ_TABLE(63268)
176 +
177 +};
178 +
179 u32 bcm63xx_get_cpu_variant(void)
180 {
181 return bcm63xx_cpu_variant;
182 @@ -253,6 +262,27 @@ static unsigned int detect_cpu_clock(voi
183
184 return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
185 }
186 + case BCM63268_CPU_ID:
187 + {
188 + unsigned int tmp, mips_pll_fcvo;
189 +
190 + tmp = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
191 + mips_pll_fcvo = (tmp & STRAPBUS_63268_FCVO_MASK) >>
192 + STRAPBUS_63268_FCVO_SHIFT;
193 + switch (mips_pll_fcvo) {
194 + case 0x3:
195 + case 0xe:
196 + return 320000000;
197 + case 0xa:
198 + return 333000000;
199 + case 0x2:
200 + case 0xb:
201 + case 0xf:
202 + return 400000000;
203 + default:
204 + return 0;
205 + }
206 + }
207
208 default:
209 panic("Failed to detect clock for CPU with id=%04X\n", cpu_id);
210 @@ -267,7 +297,7 @@ static unsigned int detect_memory_size(v
211 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
212 u32 val;
213
214 - if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
215 + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268())
216 return bcm_ddr_readl(DDR_CSEND_REG) << 24;
217
218 if (BCMCPU_IS_6345()) {
219 @@ -305,6 +335,7 @@ void __init bcm63xx_cpu_init(void)
220 unsigned int tmp;
221 unsigned int cpu = smp_processor_id();
222 u32 chipid_reg;
223 + bool long_chipid = false;
224 u8 __maybe_unused varid = 0;
225
226 /* soc registers location depends on cpu type */
227 @@ -326,6 +357,9 @@ void __init bcm63xx_cpu_init(void)
228 case 0x10:
229 chipid_reg = BCM_6345_PERF_BASE;
230 break;
231 + case 0x80:
232 + long_chipid = true;
233 + fallthrough;
234 default:
235 chipid_reg = BCM_6368_PERF_BASE;
236 break;
237 @@ -333,6 +367,7 @@ void __init bcm63xx_cpu_init(void)
238 break;
239 }
240
241 +
242 /*
243 * really early to panic, but delaying panic would not help since we
244 * will never get any working console
245 @@ -342,10 +377,17 @@ void __init bcm63xx_cpu_init(void)
246
247 /* read out CPU type */
248 tmp = bcm_readl(chipid_reg);
249 - bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
250 - bcm63xx_cpu_variant = bcm63xx_cpu_id;
251 +
252 + if (long_chipid) {
253 + bcm63xx_cpu_id = tmp & REV_LONG_CHIPID_MASK;
254 + bcm63xx_cpu_id >>= REV_LONG_CHIPID_SHIFT;
255 + } else {
256 + bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
257 + varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT;
258 + }
259 +
260 bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
261 - varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT;
262 + bcm63xx_cpu_variant = bcm63xx_cpu_id;
263
264 switch (bcm63xx_cpu_id) {
265 case BCM3368_CPU_ID:
266 @@ -400,6 +442,16 @@ void __init bcm63xx_cpu_init(void)
267 /* BCM6369 is a BCM6368 without xDSL, so treat it the same */
268 bcm63xx_cpu_id = BCM6368_CPU_ID;
269 break;
270 + case BCM63167_CPU_ID:
271 + case BCM63168_CPU_ID:
272 + case BCM63169_CPU_ID:
273 + case BCM63268_CPU_ID:
274 + case BCM63269_CPU_ID:
275 + bcm63xx_regs_base = bcm63268_regs_base;
276 + bcm63xx_irqs = bcm63268_irqs;
277 +
278 + bcm63xx_cpu_id = BCM63268_CPU_ID;
279 + break;
280 default:
281 panic("unsupported broadcom CPU %x", bcm63xx_cpu_id);
282 break;
283 --- a/arch/mips/bcm63xx/dev-flash.c
284 +++ b/arch/mips/bcm63xx/dev-flash.c
285 @@ -84,6 +84,12 @@ static int __init bcm63xx_detect_flash_t
286 return BCM63XX_FLASH_TYPE_SERIAL;
287 else
288 return BCM63XX_FLASH_TYPE_NAND;
289 + case BCM63268_CPU_ID:
290 + val = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
291 + if (val & STRAPBUS_63268_BOOT_SEL_SERIAL)
292 + return BCM63XX_FLASH_TYPE_SERIAL;
293 + else
294 + return BCM63XX_FLASH_TYPE_NAND;
295 case BCM6368_CPU_ID:
296 val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
297 switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
298 --- a/arch/mips/bcm63xx/dev-spi.c
299 +++ b/arch/mips/bcm63xx/dev-spi.c
300 @@ -51,7 +51,7 @@ int __init bcm63xx_spi_register(void)
301 }
302
303 if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() ||
304 - BCMCPU_IS_6368()) {
305 + BCMCPU_IS_6368() || BCMCPU_IS_63268()) {
306 bcm63xx_spi_device.name = "bcm6358-spi",
307 spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
308 }
309 --- a/arch/mips/bcm63xx/irq.c
310 +++ b/arch/mips/bcm63xx/irq.c
311 @@ -149,6 +149,20 @@ void __init arch_init_irq(void)
312 ext_irqs[5] = BCM_6368_EXT_IRQ5;
313 ext_shift = 4;
314 break;
315 + case BCM63268_CPU_ID:
316 + periph_bases[0] += PERF_IRQMASK_63268_REG(0);
317 + periph_bases[1] += PERF_IRQMASK_63268_REG(1);
318 + periph_irq_count = 2;
319 + periph_width = 4;
320 +
321 + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_63268;
322 + ext_irq_count = 4;
323 + ext_irqs[0] = BCM_63268_EXT_IRQ0;
324 + ext_irqs[1] = BCM_63268_EXT_IRQ1;
325 + ext_irqs[2] = BCM_63268_EXT_IRQ2;
326 + ext_irqs[3] = BCM_63268_EXT_IRQ3;
327 + ext_shift = 4;
328 + break;
329 default:
330 BUG();
331 }
332 --- a/arch/mips/bcm63xx/reset.c
333 +++ b/arch/mips/bcm63xx/reset.c
334 @@ -126,6 +126,20 @@
335 #define BCM6368_RESET_PCIE 0
336 #define BCM6368_RESET_PCIE_EXT 0
337
338 +#define BCM63268_RESET_SPI SOFTRESET_63268_SPI_MASK
339 +#define BCM63268_RESET_ENET 0
340 +#define BCM63268_RESET_USBH SOFTRESET_63268_USBH_MASK
341 +#define BCM63268_RESET_USBD SOFTRESET_63268_USBS_MASK
342 +#define BCM63268_RESET_DSL 0
343 +#define BCM63268_RESET_SAR SOFTRESET_63268_SAR_MASK
344 +#define BCM63268_RESET_EPHY 0
345 +#define BCM63268_RESET_ENETSW SOFTRESET_63268_ENETSW_MASK
346 +#define BCM63268_RESET_PCM SOFTRESET_63268_PCM_MASK
347 +#define BCM63268_RESET_MPI 0
348 +#define BCM63268_RESET_PCIE (SOFTRESET_63268_PCIE_MASK | \
349 + SOFTRESET_63268_PCIE_CORE_MASK)
350 +#define BCM63268_RESET_PCIE_EXT SOFTRESET_63268_PCIE_EXT_MASK
351 +
352 /*
353 * core reset bits
354 */
355 @@ -157,6 +171,10 @@ static const u32 bcm6368_reset_bits[] =
356 __GEN_RESET_BITS_TABLE(6368)
357 };
358
359 +static const u32 bcm63268_reset_bits[] = {
360 + __GEN_RESET_BITS_TABLE(63268)
361 +};
362 +
363 const u32 *bcm63xx_reset_bits;
364 static int reset_reg;
365
366 @@ -183,6 +201,9 @@ static int __init bcm63xx_reset_bits_ini
367 } else if (BCMCPU_IS_6368()) {
368 reset_reg = PERF_SOFTRESET_6368_REG;
369 bcm63xx_reset_bits = bcm6368_reset_bits;
370 + } else if (BCMCPU_IS_63268()) {
371 + reset_reg = PERF_SOFTRESET_63268_REG;
372 + bcm63xx_reset_bits = bcm63268_reset_bits;
373 }
374
375 return 0;
376 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
377 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
378 @@ -22,6 +22,11 @@
379 #define BCM6362_CPU_ID 0x6362
380 #define BCM6368_CPU_ID 0x6368
381 #define BCM6369_CPU_ID 0x6369
382 +#define BCM63167_CPU_ID 0x63167
383 +#define BCM63168_CPU_ID 0x63168
384 +#define BCM63169_CPU_ID 0x63169
385 +#define BCM63268_CPU_ID 0x63268
386 +#define BCM63269_CPU_ID 0x63269
387
388 void __init bcm63xx_cpu_init(void);
389 u32 bcm63xx_get_cpu_variant(void);
390 @@ -62,6 +67,10 @@ static inline u32 __pure __bcm63xx_get_c
391 #ifdef CONFIG_BCM63XX_CPU_6368
392 case BCM6368_CPU_ID:
393 #endif
394 +
395 +#ifdef CONFIG_BCM63XX_CPU_63268
396 + case BCM63268_CPU_ID:
397 +#endif
398 break;
399 default:
400 unreachable();
401 @@ -87,6 +96,7 @@ static inline u32 __pure bcm63xx_get_cpu
402 #define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
403 #define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
404 #define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
405 +#define BCMCPU_IS_63268() (bcm63xx_get_cpu_id() == BCM63268_CPU_ID)
406
407 #define BCMCPU_VARIANT_IS_3368() \
408 (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)
409 @@ -110,6 +120,16 @@ static inline u32 __pure bcm63xx_get_cpu
410 (bcm63xx_get_cpu_variant() == BCM6368_CPU_ID)
411 #define BCMCPU_VARIANT_IS_6369() \
412 (bcm63xx_get_cpu_variant() == BCM6369_CPU_ID)
413 +#define BCMCPU_VARIANT_IS_63167() \
414 + (bcm63xx_get_cpu_variant() == BCM63167_CPU_ID)
415 +#define BCMCPU_VARIANT_IS_63168() \
416 + (bcm63xx_get_cpu_variant() == BCM63168_CPU_ID)
417 +#define BCMCPU_VARIANT_IS_63169() \
418 + (bcm63xx_get_cpu_variant() == BCM63169_CPU_ID)
419 +#define BCMCPU_VARIANT_IS_63268() \
420 + (bcm63xx_get_cpu_variant() == BCM63268_CPU_ID)
421 +#define BCMCPU_VARIANT_IS_63269() \
422 + (bcm63xx_get_cpu_variant() == BCM63269_CPU_ID)
423
424 /*
425 * While registers sets are (mostly) the same across 63xx CPU, base
426 @@ -574,6 +594,52 @@ enum bcm63xx_regs_set {
427 #define BCM_6368_RNG_BASE (0xb0004180)
428 #define BCM_6368_MISC_BASE (0xdeadbeef)
429
430 +/*
431 + * 63268 register sets base address
432 + */
433 +#define BCM_63268_DSL_LMEM_BASE (0xdeadbeef)
434 +#define BCM_63268_PERF_BASE (0xb0000000)
435 +#define BCM_63268_TIMER_BASE (0xb0000080)
436 +#define BCM_63268_WDT_BASE (0xb000009c)
437 +#define BCM_63268_UART0_BASE (0xb0000180)
438 +#define BCM_63268_UART1_BASE (0xb00001a0)
439 +#define BCM_63268_GPIO_BASE (0xb00000c0)
440 +#define BCM_63268_SPI_BASE (0xb0000800)
441 +#define BCM_63268_HSSPI_BASE (0xb0001000)
442 +#define BCM_63268_UDC0_BASE (0xdeadbeef)
443 +#define BCM_63268_USBDMA_BASE (0xb000c800)
444 +#define BCM_63268_OHCI0_BASE (0xb0002600)
445 +#define BCM_63268_OHCI_PRIV_BASE (0xdeadbeef)
446 +#define BCM_63268_USBH_PRIV_BASE (0xb0002700)
447 +#define BCM_63268_USBD_BASE (0xb0002400)
448 +#define BCM_63268_MPI_BASE (0xdeadbeef)
449 +#define BCM_63268_PCMCIA_BASE (0xdeadbeef)
450 +#define BCM_63268_PCIE_BASE (0xb06e0000)
451 +#define BCM_63268_SDRAM_REGS_BASE (0xdeadbeef)
452 +#define BCM_63268_DSL_BASE (0xdeadbeef)
453 +#define BCM_63268_UBUS_BASE (0xdeadbeef)
454 +#define BCM_63268_ENET0_BASE (0xdeadbeef)
455 +#define BCM_63268_ENET1_BASE (0xdeadbeef)
456 +#define BCM_63268_ENETDMA_BASE (0xb000d800)
457 +#define BCM_63268_ENETDMAC_BASE (0xb000da00)
458 +#define BCM_63268_ENETDMAS_BASE (0xb000dc00)
459 +#define BCM_63268_ENETSW_BASE (0xb0700000)
460 +#define BCM_63268_EHCI0_BASE (0xb0002500)
461 +#define BCM_63268_SDRAM_BASE (0xdeadbeef)
462 +#define BCM_63268_MEMC_BASE (0xdeadbeef)
463 +#define BCM_63268_DDR_BASE (0xb0003000)
464 +#define BCM_63268_M2M_BASE (0xdeadbeef)
465 +#define BCM_63268_ATM_BASE (0xdeadbeef)
466 +#define BCM_63268_XTM_BASE (0xb0007000)
467 +#define BCM_63268_XTMDMA_BASE (0xb000b800)
468 +#define BCM_63268_XTMDMAC_BASE (0xdeadbeef)
469 +#define BCM_63268_XTMDMAS_BASE (0xdeadbeef)
470 +#define BCM_63268_PCM_BASE (0xb000b000)
471 +#define BCM_63268_PCMDMA_BASE (0xb000b800)
472 +#define BCM_63268_PCMDMAC_BASE (0xdeadbeef)
473 +#define BCM_63268_PCMDMAS_BASE (0xdeadbeef)
474 +#define BCM_63268_RNG_BASE (0xdeadbeef)
475 +#define BCM_63268_MISC_BASE (0xb0001800)
476
477 extern const unsigned long *bcm63xx_regs_base;
478
479 @@ -1042,6 +1108,73 @@ enum bcm63xx_irq {
480 #define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24)
481 #define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25)
482
483 +/*
484 + * 63268 irqs
485 + */
486 +#define BCM_63268_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
487 +#define BCM_63268_VERY_HIGH_IRQ_BASE (BCM_63268_HIGH_IRQ_BASE + 32)
488 +
489 +#define BCM_63268_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
490 +#define BCM_63268_SPI_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 16)
491 +#define BCM_63268_UART0_IRQ (IRQ_INTERNAL_BASE + 5)
492 +#define BCM_63268_UART1_IRQ (BCM_63268_HIGH_IRQ_BASE + 2)
493 +#define BCM_63268_DSL_IRQ (IRQ_INTERNAL_BASE + 23)
494 +#define BCM_63268_UDC0_IRQ 0
495 +#define BCM_63268_ENET0_IRQ 0
496 +#define BCM_63268_ENET1_IRQ 0
497 +#define BCM_63268_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 13)
498 +#define BCM_63268_HSSPI_IRQ (IRQ_INTERNAL_BASE + 6)
499 +#define BCM_63268_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
500 +#define BCM_63268_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
501 +#define BCM_63268_USBD_IRQ (IRQ_INTERNAL_BASE + 11)
502 +#define BCM_63268_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 19)
503 +#define BCM_63268_USBD_TXDMA0_IRQ (BCM_63268_HIGH_IRQ_BASE + 4)
504 +#define BCM_63268_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 20)
505 +#define BCM_63268_USBD_TXDMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 5)
506 +#define BCM_63268_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 21)
507 +#define BCM_63268_USBD_TXDMA2_IRQ (BCM_63268_HIGH_IRQ_BASE + 6)
508 +#define BCM_63268_PCMCIA_IRQ 0
509 +#define BCM_63268_ENET0_RXDMA_IRQ 0
510 +#define BCM_63268_ENET0_TXDMA_IRQ 0
511 +#define BCM_63268_ENET1_RXDMA_IRQ 0
512 +#define BCM_63268_ENET1_TXDMA_IRQ 0
513 +#define BCM_63268_PCI_IRQ (BCM_63268_HIGH_IRQ_BASE + 8)
514 +#define BCM_63268_ATM_IRQ 0
515 +#define BCM_63268_ENETSW_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 1)
516 +#define BCM_63268_ENETSW_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 2)
517 +#define BCM_63268_ENETSW_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 3)
518 +#define BCM_63268_ENETSW_RXDMA3_IRQ (IRQ_INTERNAL_BASE + 4)
519 +#define BCM_63268_ENETSW_TXDMA0_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 0)
520 +#define BCM_63268_ENETSW_TXDMA1_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 1)
521 +#define BCM_63268_ENETSW_TXDMA2_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 2)
522 +#define BCM_63268_ENETSW_TXDMA3_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 3)
523 +#define BCM_63268_XTM_IRQ (BCM_63268_HIGH_IRQ_BASE + 17)
524 +#define BCM_63268_XTM_DMA0_IRQ (IRQ_INTERNAL_BASE + 26)
525 +
526 +#define BCM_63268_RING_OSC_IRQ (BCM_63268_HIGH_IRQ_BASE + 20)
527 +#define BCM_63268_WLAN_GPIO_IRQ (BCM_63268_HIGH_IRQ_BASE + 3)
528 +#define BCM_63268_WLAN_IRQ (IRQ_INTERNAL_BASE + 7)
529 +#define BCM_63268_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8)
530 +#define BCM_63268_NAND_IRQ (BCM_63268_HIGH_IRQ_BASE + 18)
531 +#define BCM_63268_PCM_IRQ (IRQ_INTERNAL_BASE + 13)
532 +#define BCM_63268_DG_IRQ (IRQ_INTERNAL_BASE + 15)
533 +#define BCM_63268_EPHY_ENERGY0_IRQ (IRQ_INTERNAL_BASE + 16)
534 +#define BCM_63268_EPHY_ENERGY1_IRQ (IRQ_INTERNAL_BASE + 17)
535 +#define BCM_63268_EPHY_ENERGY2_IRQ (IRQ_INTERNAL_BASE + 18)
536 +#define BCM_63268_EPHY_ENERGY3_IRQ (IRQ_INTERNAL_BASE + 19)
537 +#define BCM_63268_IPSEC_DMA0_IRQ (IRQ_INTERNAL_BASE + 22)
538 +#define BCM_63268_IPSEC_DMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 7)
539 +#define BCM_63268_FAP0_IRQ (IRQ_INTERNAL_BASE + 24)
540 +#define BCM_63268_FAP1_IRQ (IRQ_INTERNAL_BASE + 25)
541 +#define BCM_63268_PCM_DMA0_IRQ (BCM_63268_HIGH_IRQ_BASE + 10)
542 +#define BCM_63268_PCM_DMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 11)
543 +#define BCM_63268_DECT0_IRQ (BCM_63268_HIGH_IRQ_BASE + 0)
544 +#define BCM_63268_DECT1_IRQ (BCM_63268_HIGH_IRQ_BASE + 1)
545 +#define BCM_63268_EXT_IRQ0 (BCM_63268_HIGH_IRQ_BASE + 12)
546 +#define BCM_63268_EXT_IRQ1 (BCM_63268_HIGH_IRQ_BASE + 13)
547 +#define BCM_63268_EXT_IRQ2 (BCM_63268_HIGH_IRQ_BASE + 14)
548 +#define BCM_63268_EXT_IRQ3 (BCM_63268_HIGH_IRQ_BASE + 15)
549 +
550 extern const int *bcm63xx_irqs;
551
552 #define __GEN_CPU_IRQ_TABLE(__cpu) \
553 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
554 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
555 @@ -23,6 +23,8 @@ static inline unsigned long bcm63xx_gpio
556 return 38;
557 case BCM6362_CPU_ID:
558 return 48;
559 + case BCM63268_CPU_ID:
560 + return 52;
561 case BCM6348_CPU_ID:
562 default:
563 return 37;
564 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
565 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
566 @@ -10,6 +10,8 @@
567 #define PERF_REV_REG 0x0
568 #define REV_CHIPID_SHIFT 16
569 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
570 +#define REV_LONG_CHIPID_SHIFT 12
571 +#define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT)
572 #define REV_VARID_SHIFT 12
573 #define REV_VARID_MASK (0xf << REV_VARID_SHIFT)
574 #define REV_REVID_SHIFT 0
575 @@ -212,6 +214,52 @@
576 CKCTL_6368_NAND_EN | \
577 CKCTL_6368_IPSEC_EN)
578
579 +#define CKCTL_63268_DISABLE_GLESS (1 << 0)
580 +#define CKCTL_63268_VDSL_QPROC_EN (1 << 1)
581 +#define CKCTL_63268_VDSL_AFE_EN (1 << 2)
582 +#define CKCTL_63268_VDSL_EN (1 << 3)
583 +#define CKCTL_63268_MIPS_EN (1 << 4)
584 +#define CKCTL_63268_WLAN_OCP_EN (1 << 5)
585 +#define CKCTL_63268_DECT_EN (1 << 6)
586 +#define CKCTL_63268_FAP0_EN (1 << 7)
587 +#define CKCTL_63268_FAP1_EN (1 << 8)
588 +#define CKCTL_63268_SAR_EN (1 << 9)
589 +#define CKCTL_63268_ROBOSW_EN (1 << 10)
590 +#define CKCTL_63268_PCM_EN (1 << 11)
591 +#define CKCTL_63268_USBD_EN (1 << 12)
592 +#define CKCTL_63268_USBH_EN (1 << 13)
593 +#define CKCTL_63268_IPSEC_EN (1 << 14)
594 +#define CKCTL_63268_SPI_EN (1 << 15)
595 +#define CKCTL_63268_HSSPI_EN (1 << 16)
596 +#define CKCTL_63268_PCIE_EN (1 << 17)
597 +#define CKCTL_63268_PHYMIPS_EN (1 << 18)
598 +#define CKCTL_63268_GMAC_EN (1 << 19)
599 +#define CKCTL_63268_NAND_EN (1 << 20)
600 +#define CKCTL_63268_TBUS_EN (1 << 27)
601 +#define CKCTL_63268_ROBOSW250_EN (1 << 31)
602 +
603 +#define CKCTL_63268_ALL_SAFE_EN (CKCTL_63268_VDSL_QPROC_EN | \
604 + CKCTL_63268_VDSL_AFE_EN | \
605 + CKCTL_63268_VDSL_EN | \
606 + CKCTL_63268_WLAN_OCP_EN | \
607 + CKCTL_63268_DECT_EN | \
608 + CKCTL_63268_FAP0_EN | \
609 + CKCTL_63268_FAP1_EN | \
610 + CKCTL_63268_SAR_EN | \
611 + CKCTL_63268_ROBOSW_EN | \
612 + CKCTL_63268_PCM_EN | \
613 + CKCTL_63268_USBD_EN | \
614 + CKCTL_63268_USBH_EN | \
615 + CKCTL_63268_IPSEC_EN | \
616 + CKCTL_63268_SPI_EN | \
617 + CKCTL_63268_HSSPI_EN | \
618 + CKCTL_63268_PCIE_EN | \
619 + CKCTL_63268_PHYMIPS_EN | \
620 + CKCTL_63268_GMAC_EN | \
621 + CKCTL_63268_NAND_EN | \
622 + CKCTL_63268_TBUS_EN | \
623 + CKCTL_63268_ROBOSW250_EN)
624 +
625 /* System PLL Control register */
626 #define PERF_SYS_PLL_CTL_REG 0x8
627 #define SYS_PLL_SOFT_RESET 0x1
628 @@ -225,6 +273,7 @@
629 #define PERF_IRQMASK_6358_REG(x) (0xc + (x) * 0x2c)
630 #define PERF_IRQMASK_6362_REG(x) (0x20 + (x) * 0x10)
631 #define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10)
632 +#define PERF_IRQMASK_63268_REG(x) (0x20 + (x) * 0x20)
633
634 /* Interrupt Status register */
635 #define PERF_IRQSTAT_3368_REG 0x10
636 @@ -235,6 +284,7 @@
637 #define PERF_IRQSTAT_6358_REG(x) (0x10 + (x) * 0x2c)
638 #define PERF_IRQSTAT_6362_REG(x) (0x28 + (x) * 0x10)
639 #define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10)
640 +#define PERF_IRQSTAT_63268_REG(x) (0x30 + (x) * 0x20)
641
642 /* External Interrupt Configuration register */
643 #define PERF_EXTIRQ_CFG_REG_3368 0x14
644 @@ -245,6 +295,7 @@
645 #define PERF_EXTIRQ_CFG_REG_6358 0x14
646 #define PERF_EXTIRQ_CFG_REG_6362 0x18
647 #define PERF_EXTIRQ_CFG_REG_6368 0x18
648 +#define PERF_EXTIRQ_CFG_REG_63268 0x18
649
650 #define PERF_EXTIRQ_CFG_REG2_6358 0x1c
651 #define PERF_EXTIRQ_CFG_REG2_6368 0x1c
652 @@ -275,6 +326,7 @@
653 #define PERF_SOFTRESET_6358_REG 0x34
654 #define PERF_SOFTRESET_6362_REG 0x10
655 #define PERF_SOFTRESET_6368_REG 0x10
656 +#define PERF_SOFTRESET_63268_REG 0x10
657
658 #define SOFTRESET_3368_SPI_MASK (1 << 0)
659 #define SOFTRESET_3368_ENET_MASK (1 << 2)
660 @@ -368,6 +420,26 @@
661 #define SOFTRESET_6368_USBH_MASK (1 << 12)
662 #define SOFTRESET_6368_PCM_MASK (1 << 13)
663
664 +#define SOFTRESET_63268_SPI_MASK (1 << 0)
665 +#define SOFTRESET_63268_IPSEC_MASK (1 << 1)
666 +#define SOFTRESET_63268_EPHY_MASK (1 << 2)
667 +#define SOFTRESET_63268_SAR_MASK (1 << 3)
668 +#define SOFTRESET_63268_ENETSW_MASK (1 << 4)
669 +#define SOFTRESET_63268_USBS_MASK (1 << 5)
670 +#define SOFTRESET_63268_USBH_MASK (1 << 6)
671 +#define SOFTRESET_63268_PCM_MASK (1 << 7)
672 +#define SOFTRESET_63268_PCIE_CORE_MASK (1 << 8)
673 +#define SOFTRESET_63268_PCIE_MASK (1 << 9)
674 +#define SOFTRESET_63268_PCIE_EXT_MASK (1 << 10)
675 +#define SOFTRESET_63268_WLAN_SHIM_MASK (1 << 11)
676 +#define SOFTRESET_63268_DDR_PHY_MASK (1 << 12)
677 +#define SOFTRESET_63268_FAP0_MASK (1 << 13)
678 +#define SOFTRESET_63268_WLAN_UBUS_MASK (1 << 14)
679 +#define SOFTRESET_63268_DECT_MASK (1 << 15)
680 +#define SOFTRESET_63268_FAP1_MASK (1 << 16)
681 +#define SOFTRESET_63268_PCIE_HARD_MASK (1 << 17)
682 +#define SOFTRESET_63268_GPHY_MASK (1 << 18)
683 +
684 /* MIPS PLL control register */
685 #define PERF_MIPSPLLCTL_REG 0x34
686 #define MIPSPLLCTL_N1_SHIFT 20
687 @@ -559,6 +631,11 @@
688 #define STRAPBUS_6368_BOOT_SEL_SERIAL 1
689 #define STRAPBUS_6368_BOOT_SEL_PARALLEL 3
690
691 +/* BCM6318 BCM6328 BCM6362 BCM63268 */
692 +#define GPIO_ROBOSW_SW_CTRL_REG 0x40
693 +#define GPIO_ROBOSW_MII_DUMB_FWDG_EN (1 << 0)
694 +#define GPIO_ROBOSW_HW_FWDG_EN (1 << 3)
695 +
696
697 /*************************************************************************
698 * _REG relative to RSET_ENET
699 @@ -1367,6 +1444,13 @@
700 #define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15)
701 #define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15)
702
703 +#define MISC_STRAPBUS_63268_REG 0x14
704 +#define STRAPBUS_63268_HSSPI_CLK_FAST (1 << 9)
705 +#define STRAPBUS_63268_BOOT_SEL_SERIAL (1 << 11)
706 +#define STRAPBUS_63268_BOOT_SEL_NAND (0 << 11)
707 +#define STRAPBUS_63268_FCVO_SHIFT 21
708 +#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
709 +
710 #define MISC_STRAPBUS_6328_REG 0x240
711 #define STRAPBUS_6328_FCVO_SHIFT 7
712 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
713 --- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
714 +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
715 @@ -21,6 +21,7 @@ static inline int is_bcm63xx_internal_re
716 case BCM6328_CPU_ID:
717 case BCM6362_CPU_ID:
718 case BCM6368_CPU_ID:
719 + case BCM63268_CPU_ID:
720 if (offset >= 0xb0000000 && offset < 0xb1000000)
721 return 1;
722 break;
723 --- a/arch/mips/bcm63xx/dev-hsspi.c
724 +++ b/arch/mips/bcm63xx/dev-hsspi.c
725 @@ -35,7 +35,7 @@ static struct platform_device bcm63xx_hs
726
727 int __init bcm63xx_hsspi_register(void)
728 {
729 - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362())
730 + if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268())
731 return -ENODEV;
732
733 spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI);
734 --- a/arch/mips/bcm63xx/dev-enet.c
735 +++ b/arch/mips/bcm63xx/dev-enet.c
736 @@ -184,7 +184,8 @@ static int __init register_shared(void)
737 else
738 shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
739
740 - if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
741 + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() ||
742 + BCMCPU_IS_63268())
743 chan_count = 32;
744 else if (BCMCPU_IS_6345())
745 chan_count = 8;
746 @@ -292,7 +293,8 @@ bcm63xx_enetsw_register(const struct bcm
747 {
748 int ret;
749
750 - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
751 + if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() &&
752 + !BCMCPU_IS_63268())
753 return -ENODEV;
754
755 ret = register_shared();
756 @@ -313,6 +315,8 @@ bcm63xx_enetsw_register(const struct bcm
757 enetsw_pd.num_ports = ENETSW_PORTS_6328;
758 else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
759 enetsw_pd.num_ports = ENETSW_PORTS_6368;
760 + else if (BCMCPU_IS_63268())
761 + enetsw_pd.num_ports = ENETSW_PORTS_63268;
762
763 enetsw_pd.dma_has_sram = true;
764 enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH;
765 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
766 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
767 @@ -67,6 +67,7 @@ struct bcm63xx_enet_platform_data {
768 #define ENETSW_MAX_PORT 8
769 #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
770 #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
771 +#define ENETSW_PORTS_63268 8 /* 3 FE PHY + 1 GE PHY + 4 RGMII */
772
773 #define ENETSW_RGMII_PORT0 4
774
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