target/linux/bcm27xx/patches-5.10/950-0538-drm-vc4-hdmi-Convert-to-the-new-clock-request-API.patch

   1 From fe77a92b9018f9a2dbab0e2a600e368d55c667b0 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Tue, 13 Apr 2021 11:55:55 +0200
   4 Subject: [PATCH] drm/vc4: hdmi: Convert to the new clock request API
   5
   6 The new clock request API allows us to increase the rate of the HSM
   7 clock to match our pixel rate requirements while decreasing it when
   8 we're done, resulting in a better power-efficiency.
   9
  10 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  11 ---
  12  drivers/gpu/drm/vc4/vc4_hdmi.c | 22 +++++++++++++++-------
  13  drivers/gpu/drm/vc4/vc4_hdmi.h |  3 +++
  14  2 files changed, 18 insertions(+), 7 deletions(-)
  15
  16 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
  17 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
  18 @@ -546,6 +546,9 @@ static void vc4_hdmi_encoder_post_crtc_p
  19                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
  20
  21         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
  22 +       clk_request_done(vc4_hdmi->bvb_req);
  23 +       clk_disable_unprepare(vc4_hdmi->hsm_clock);
  24 +       clk_request_done(vc4_hdmi->hsm_req);
  25         clk_disable_unprepare(vc4_hdmi->pixel_clock);
  26
  27         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
  28 @@ -850,9 +853,9 @@ static void vc4_hdmi_encoder_pre_crtc_co
  29          * pixel clock, but HSM ends up being the limiting factor.
  30          */
  31         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
  32 -       ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
  33 -       if (ret) {
  34 -               DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
  35 +       vc4_hdmi->hsm_req = clk_request_start(vc4_hdmi->hsm_clock, hsm_rate);
  36 +       if (IS_ERR(vc4_hdmi->hsm_req)) {
  37 +               DRM_ERROR("Failed to set HSM clock rate: %ld\n", PTR_ERR(vc4_hdmi->hsm_req));
  38                 return;
  39         }
  40
  41 @@ -864,10 +867,12 @@ static void vc4_hdmi_encoder_pre_crtc_co
  42          * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup
  43          * at 300MHz.
  44          */
  45 -       ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock,
  46 -                              (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));
  47 -       if (ret) {
  48 -               DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
  49 +       vc4_hdmi->bvb_req = clk_request_start(vc4_hdmi->pixel_bvb_clock,
  50 +                                             (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));
  51 +       if (IS_ERR(vc4_hdmi->bvb_req)) {
  52 +               DRM_ERROR("Failed to set pixel bvb clock rate: %ld\n", PTR_ERR(vc4_hdmi->bvb_req));
  53 +               clk_request_done(vc4_hdmi->hsm_req);
  54 +               clk_disable_unprepare(vc4_hdmi->hsm_clock);
  55                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
  56                 return;
  57         }
  58 @@ -875,6 +880,9 @@ static void vc4_hdmi_encoder_pre_crtc_co
  59         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
  60         if (ret) {
  61                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
  62 +               clk_request_done(vc4_hdmi->bvb_req);
  63 +               clk_request_done(vc4_hdmi->hsm_req);
  64 +               clk_disable_unprepare(vc4_hdmi->hsm_clock);
  65                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
  66                 return;
  67         }
  68 --- a/drivers/gpu/drm/vc4/vc4_hdmi.h
  69 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
  70 @@ -172,6 +172,9 @@ struct vc4_hdmi {
  71
  72         struct reset_control *reset;
  73
  74 +       struct clk_request *bvb_req;
  75 +       struct clk_request *hsm_req;
  76 +
  77         /* Common debugfs regset */
  78         struct debugfs_regset32 hdmi_regset;
  79         struct debugfs_regset32 hd_regset;