target/linux/bcm27xx/patches-5.10/950-0435-overlays-Add-overlay-for-Seeed-Studio-CAN-BUS-FD-HAT.patch

   1 From a58855e02a8a0a0de898efcfb0e4790076a0d640 Mon Sep 17 00:00:00 2001
   2 From: Marc Kleine-Budde <mkl@pengutronix.de>
   3 Date: Sat, 2 Jan 2021 21:38:58 +0100
   4 Subject: [PATCH] overlays: Add overlay for Seeed Studio CAN BUS FD HAT
   5  v1 (based on mcp2517fd)
   6
   7 This patch adds the overlay for the Seeed Studio CAN BUS FD HAT v1 with two CAN
   8 FD Channels (based on mcp2517fd).
   9
  10 https://www.seeedstudio.com/2-Channel-CAN-BUS-FD-Shield-for-Raspberry-Pi-p-4072.html
  11
  12 The overlay was generated by:
  13 ovmerge -c spi1-1cs-overlay.dts,cs0_pin=18,cs0_spidev=false \
  14            mcp251xfd-overlay.dts,spi0-0,interrupt=25 \
  15            mcp251xfd-overlay.dts,spi1-0,interrupt=24
  16
  17 Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
  18 ---
  19  arch/arm/boot/dts/overlays/Makefile           |   1 +
  20  arch/arm/boot/dts/overlays/README             |   8 +
  21  .../overlays/seeed-can-fd-hat-v1-overlay.dts  | 138 ++++++++++++++++++
  22  3 files changed, 147 insertions(+)
  23  create mode 100644 arch/arm/boot/dts/overlays/seeed-can-fd-hat-v1-overlay.dts
  24
  25 --- a/arch/arm/boot/dts/overlays/Makefile
  26 +++ b/arch/arm/boot/dts/overlays/Makefile
  27 @@ -161,6 +161,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
  28         sc16is752-spi1.dtbo \
  29         sdhost.dtbo \
  30         sdio.dtbo \
  31 +       seeed-can-fd-hat-v1.dtbo \
  32         seeed-can-fd-hat-v2.dtbo \
  33         sh1106-spi.dtbo \
  34         smi.dtbo \
  35 --- a/arch/arm/boot/dts/overlays/README
  36 +++ b/arch/arm/boot/dts/overlays/README
  37 @@ -2504,6 +2504,14 @@ Info:   This overlay is now deprecated.
  38  Load:   <Deprecated>
  39
  40
  41 +Name:   seeed-can-fd-hat-v1
  42 +Info:   Overlay for Seeed Studio CAN BUS FD HAT with two CAN FD channels
  43 +        (based on the mcp2517fd).
  44 +        https://www.seeedstudio.com/2-Channel-CAN-BUS-FD-Shield-for-Raspberry-Pi-p-4072.html
  45 +Load:   dtoverlay=seeed-can-fd-hat-v1
  46 +Params: <None>
  47 +
  48 +
  49  Name:   seeed-can-fd-hat-v2
  50  Info:   Overlay for Seeed Studio CAN BUS FD HAT with two CAN FD channels
  51          (based on the mcp2518fd) and an RTC.
  52 --- /dev/null
  53 +++ b/arch/arm/boot/dts/overlays/seeed-can-fd-hat-v1-overlay.dts
  54 @@ -0,0 +1,138 @@
  55 +// redo: ovmerge -c spi1-1cs-overlay.dts,cs0_pin=18,cs0_spidev=false mcp251xfd-overlay.dts,spi0-0,interrupt=25 mcp251xfd-overlay.dts,spi1-0,interrupt=24
  56 +
  57 +// Device tree overlay for https://www.seeedstudio.com/2-Channel-CAN-BUS-FD-Shield-for-Raspberry-Pi-p-4072.html
  58 +
  59 +/dts-v1/;
  60 +/plugin/;
  61 +
  62 +#include <dt-bindings/gpio/gpio.h>
  63 +#include <dt-bindings/interrupt-controller/irq.h>
  64 +#include <dt-bindings/pinctrl/bcm2835.h>
  65 +
  66 +/ {
  67 +       compatible = "brcm,bcm2835";
  68 +       fragment@0 {
  69 +               target = <&gpio>;
  70 +               __overlay__ {
  71 +                       spi1_pins: spi1_pins {
  72 +                               brcm,pins = <19 20 21>;
  73 +                               brcm,function = <3>;
  74 +                       };
  75 +                       spi1_cs_pins: spi1_cs_pins {
  76 +                               brcm,pins = <18>;
  77 +                               brcm,function = <1>;
  78 +                       };
  79 +               };
  80 +       };
  81 +       fragment@1 {
  82 +               target = <&spi1>;
  83 +               __overlay__ {
  84 +                       #address-cells = <1>;
  85 +                       #size-cells = <0>;
  86 +                       pinctrl-names = "default";
  87 +                       pinctrl-0 = <&spi1_pins &spi1_cs_pins>;
  88 +                       cs-gpios = <&gpio 18 1>;
  89 +                       status = "okay";
  90 +                       spidev@0 {
  91 +                               compatible = "spidev";
  92 +                               reg = <0>;
  93 +                               #address-cells = <1>;
  94 +                               #size-cells = <0>;
  95 +                               spi-max-frequency = <125000000>;
  96 +                               status = "disabled";
  97 +                       };
  98 +               };
  99 +       };
 100 +       fragment@2 {
 101 +               target = <&aux>;
 102 +               __overlay__ {
 103 +                       status = "okay";
 104 +               };
 105 +       };
 106 +       fragment@3 {
 107 +               target = <&spidev0>;
 108 +               __overlay__ {
 109 +                       status = "disabled";
 110 +               };
 111 +       };
 112 +       fragment@4 {
 113 +               target = <&gpio>;
 114 +               __overlay__ {
 115 +                       mcp251xfd_pins: mcp251xfd_spi0_0_pins {
 116 +                               brcm,pins = <25>;
 117 +                               brcm,function = <BCM2835_FSEL_GPIO_IN>;
 118 +                       };
 119 +               };
 120 +       };
 121 +       fragment@5 {
 122 +               target-path = "/clocks";
 123 +               __overlay__ {
 124 +                       clk_mcp251xfd_osc: mcp251xfd-spi0-0-osc {
 125 +                               #clock-cells = <0>;
 126 +                               compatible = "fixed-clock";
 127 +                               clock-frequency = <40000000>;
 128 +                       };
 129 +               };
 130 +       };
 131 +       fragment@6 {
 132 +               target = <&spi0>;
 133 +               __overlay__ {
 134 +                       status = "okay";
 135 +                       #address-cells = <1>;
 136 +                       #size-cells = <0>;
 137 +                       mcp251xfd@0 {
 138 +                               compatible = "microchip,mcp251xfd";
 139 +                               reg = <0>;
 140 +                               pinctrl-names = "default";
 141 +                               pinctrl-0 = <&mcp251xfd_pins>;
 142 +                               spi-max-frequency = <20000000>;
 143 +                               interrupt-parent = <&gpio>;
 144 +                               interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
 145 +                               clocks = <&clk_mcp251xfd_osc>;
 146 +                       };
 147 +               };
 148 +       };
 149 +       fragment@7 {
 150 +               target-path = "spi1/spidev@0";
 151 +               __overlay__ {
 152 +                       status = "disabled";
 153 +               };
 154 +       };
 155 +       fragment@8 {
 156 +               target = <&gpio>;
 157 +               __overlay__ {
 158 +                       mcp251xfd_pins_1: mcp251xfd_spi1_0_pins {
 159 +                               brcm,pins = <24>;
 160 +                               brcm,function = <BCM2835_FSEL_GPIO_IN>;
 161 +                       };
 162 +               };
 163 +       };
 164 +       fragment@9 {
 165 +               target-path = "/clocks";
 166 +               __overlay__ {
 167 +                       clk_mcp251xfd_osc_1: mcp251xfd-spi1-0-osc {
 168 +                               #clock-cells = <0>;
 169 +                               compatible = "fixed-clock";
 170 +                               clock-frequency = <40000000>;
 171 +                       };
 172 +               };
 173 +       };
 174 +       fragment@10 {
 175 +               target = <&spi1>;
 176 +               __overlay__ {
 177 +                       status = "okay";
 178 +                       #address-cells = <1>;
 179 +                       #size-cells = <0>;
 180 +                       mcp251xfd@0 {
 181 +                               compatible = "microchip,mcp251xfd";
 182 +                               reg = <0>;
 183 +                               pinctrl-names = "default";
 184 +                               pinctrl-0 = <&mcp251xfd_pins_1>;
 185 +                               spi-max-frequency = <20000000>;
 186 +                               interrupt-parent = <&gpio>;
 187 +                               interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
 188 +                               clocks = <&clk_mcp251xfd_osc_1>;
 189 +                       };
 190 +               };
 191 +       };
 192 +};