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[openwrt/staging/noltari.git] / package / boot / uboot-mediatek / patches / 001-mtk-0020-nand-raw-add-support-for-MediaTek-MT7621-SoC.patch
1 From 8d94833f13ccd7e1dfea605cfdf9a8eb53505515 Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Fri, 20 May 2022 11:23:47 +0800
4 Subject: [PATCH 20/25] nand: raw: add support for MediaTek MT7621 SoC
5
6 This patch adds NAND flash controller driver for MediaTek MT7621 SoC.
7 The NAND flash controller of MT7621 supports only SLC NAND flashes.
8 It supports 4~12 bits correction with maximum 4KB page size.
9
10 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
11 ---
12 drivers/mtd/nand/raw/Kconfig | 17 +-
13 drivers/mtd/nand/raw/Makefile | 2 +
14 drivers/mtd/nand/raw/mt7621_nand.c | 1205 ++++++++++++++++++++++++
15 drivers/mtd/nand/raw/mt7621_nand.h | 29 +
16 drivers/mtd/nand/raw/mt7621_nand_spl.c | 237 +++++
17 5 files changed, 1488 insertions(+), 2 deletions(-)
18 create mode 100644 drivers/mtd/nand/raw/mt7621_nand.c
19 create mode 100644 drivers/mtd/nand/raw/mt7621_nand.h
20 create mode 100644 drivers/mtd/nand/raw/mt7621_nand_spl.c
21
22 --- a/drivers/mtd/nand/raw/Kconfig
23 +++ b/drivers/mtd/nand/raw/Kconfig
24 @@ -521,12 +521,25 @@ config TEGRA_NAND
25 help
26 Enables support for NAND Flash chips on Tegra SoCs platforms.
27
28 +config NAND_MT7621
29 + bool "Support for MediaTek MT7621 NAND flash controller"
30 + depends on SOC_MT7621
31 + select SYS_NAND_SELF_INIT
32 + select SPL_SYS_NAND_SELF_INIT
33 + imply CMD_NAND
34 + help
35 + This enables NAND driver for the NAND flash controller on MediaTek
36 + MT7621 platform.
37 + The controller supports 4~12 bits correction per 512 bytes with a
38 + maximum 4KB page size.
39 +
40 comment "Generic NAND options"
41
42 config SYS_NAND_BLOCK_SIZE
43 hex "NAND chip eraseblock size"
44 depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
45 - depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_FSL_IFC
46 + depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && \
47 + !NAND_FSL_IFC && !NAND_MT7621
48 help
49 Number of data bytes in one eraseblock for the NAND chip on the
50 board. This is the multiple of NAND_PAGE_SIZE and the number of
51 @@ -551,7 +564,7 @@ config SYS_NAND_PAGE_SIZE
52 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
53 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
54 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
55 - depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
56 + depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621
57 help
58 Number of data bytes in one page for the NAND chip on the
59 board, not including the OOB area.
60 --- a/drivers/mtd/nand/raw/Makefile
61 +++ b/drivers/mtd/nand/raw/Makefile
62 @@ -72,6 +72,7 @@ obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o
63 obj-$(CONFIG_NAND_STM32_FMC2) += stm32_fmc2_nand.o
64 obj-$(CONFIG_CORTINA_NAND) += cortina_nand.o
65 obj-$(CONFIG_ROCKCHIP_NAND) += rockchip_nfc.o
66 +obj-$(CONFIG_NAND_MT7621) += mt7621_nand.o
67
68 else # minimal SPL drivers
69
70 @@ -80,5 +81,6 @@ obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_sp
71 obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
72 obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o
73 obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o
74 +obj-$(CONFIG_NAND_MT7621) += mt7621_nand_spl.o mt7621_nand.o
75
76 endif # drivers
77 --- /dev/null
78 +++ b/drivers/mtd/nand/raw/mt7621_nand.c
79 @@ -0,0 +1,1205 @@
80 +// SPDX-License-Identifier: GPL-2.0
81 +/*
82 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
83 + *
84 + * Author: Weijie Gao <weijie.gao@mediatek.com>
85 + */
86 +
87 +#include <log.h>
88 +#include <nand.h>
89 +#include <malloc.h>
90 +#include <asm/addrspace.h>
91 +#include <linux/io.h>
92 +#include <linux/iopoll.h>
93 +#include <linux/sizes.h>
94 +#include <linux/bitops.h>
95 +#include <linux/bitfield.h>
96 +#include "mt7621_nand.h"
97 +
98 +/* NFI core registers */
99 +#define NFI_CNFG 0x000
100 +#define CNFG_OP_MODE GENMASK(14, 12)
101 +#define CNFG_OP_CUSTOM 6
102 +#define CNFG_AUTO_FMT_EN BIT(9)
103 +#define CNFG_HW_ECC_EN BIT(8)
104 +#define CNFG_BYTE_RW BIT(6)
105 +#define CNFG_READ_MODE BIT(1)
106 +
107 +#define NFI_PAGEFMT 0x004
108 +#define PAGEFMT_FDM_ECC GENMASK(15, 12)
109 +#define PAGEFMT_FDM GENMASK(11, 8)
110 +#define PAGEFMT_SPARE GENMASK(5, 4)
111 +#define PAGEFMT_PAGE GENMASK(1, 0)
112 +
113 +#define NFI_CON 0x008
114 +#define CON_NFI_SEC GENMASK(15, 12)
115 +#define CON_NFI_BWR BIT(9)
116 +#define CON_NFI_BRD BIT(8)
117 +#define CON_NFI_RST BIT(1)
118 +#define CON_FIFO_FLUSH BIT(0)
119 +
120 +#define NFI_ACCCON 0x00c
121 +#define ACCCON_POECS GENMASK(31, 28)
122 +#define ACCCON_POECS_DEF 3
123 +#define ACCCON_PRECS GENMASK(27, 22)
124 +#define ACCCON_PRECS_DEF 3
125 +#define ACCCON_C2R GENMASK(21, 16)
126 +#define ACCCON_C2R_DEF 7
127 +#define ACCCON_W2R GENMASK(15, 12)
128 +#define ACCCON_W2R_DEF 7
129 +#define ACCCON_WH GENMASK(11, 8)
130 +#define ACCCON_WH_DEF 15
131 +#define ACCCON_WST GENMASK(7, 4)
132 +#define ACCCON_WST_DEF 15
133 +#define ACCCON_WST_MIN 3
134 +#define ACCCON_RLT GENMASK(3, 0)
135 +#define ACCCON_RLT_DEF 15
136 +#define ACCCON_RLT_MIN 3
137 +
138 +#define NFI_CMD 0x020
139 +
140 +#define NFI_ADDRNOB 0x030
141 +#define ADDR_ROW_NOB GENMASK(6, 4)
142 +#define ADDR_COL_NOB GENMASK(2, 0)
143 +
144 +#define NFI_COLADDR 0x034
145 +#define NFI_ROWADDR 0x038
146 +
147 +#define NFI_STRDATA 0x040
148 +#define STR_DATA BIT(0)
149 +
150 +#define NFI_CNRNB 0x044
151 +#define CB2R_TIME GENMASK(7, 4)
152 +#define STR_CNRNB BIT(0)
153 +
154 +#define NFI_DATAW 0x050
155 +#define NFI_DATAR 0x054
156 +
157 +#define NFI_PIO_DIRDY 0x058
158 +#define PIO_DIRDY BIT(0)
159 +
160 +#define NFI_STA 0x060
161 +#define STA_NFI_FSM GENMASK(19, 16)
162 +#define STA_FSM_CUSTOM_DATA 14
163 +#define STA_BUSY BIT(8)
164 +#define STA_ADDR BIT(1)
165 +#define STA_CMD BIT(0)
166 +
167 +#define NFI_ADDRCNTR 0x070
168 +#define SEC_CNTR GENMASK(15, 12)
169 +#define SEC_ADDR GENMASK(9, 0)
170 +
171 +#define NFI_CSEL 0x090
172 +#define CSEL GENMASK(1, 0)
173 +
174 +#define NFI_FDM0L 0x0a0
175 +#define NFI_FDML(n) (0x0a0 + ((n) << 3))
176 +
177 +#define NFI_FDM0M 0x0a4
178 +#define NFI_FDMM(n) (0x0a4 + ((n) << 3))
179 +
180 +#define NFI_MASTER_STA 0x210
181 +#define MAS_ADDR GENMASK(11, 9)
182 +#define MAS_RD GENMASK(8, 6)
183 +#define MAS_WR GENMASK(5, 3)
184 +#define MAS_RDDLY GENMASK(2, 0)
185 +
186 +/* ECC engine registers */
187 +#define ECC_ENCCON 0x000
188 +#define ENC_EN BIT(0)
189 +
190 +#define ECC_ENCCNFG 0x004
191 +#define ENC_CNFG_MSG GENMASK(28, 16)
192 +#define ENC_MODE GENMASK(5, 4)
193 +#define ENC_MODE_NFI 1
194 +#define ENC_TNUM GENMASK(2, 0)
195 +
196 +#define ECC_ENCIDLE 0x00c
197 +#define ENC_IDLE BIT(0)
198 +
199 +#define ECC_DECCON 0x100
200 +#define DEC_EN BIT(0)
201 +
202 +#define ECC_DECCNFG 0x104
203 +#define DEC_EMPTY_EN BIT(31)
204 +#define DEC_CS GENMASK(28, 16)
205 +#define DEC_CON GENMASK(13, 12)
206 +#define DEC_CON_EL 2
207 +#define DEC_MODE GENMASK(5, 4)
208 +#define DEC_MODE_NFI 1
209 +#define DEC_TNUM GENMASK(2, 0)
210 +
211 +#define ECC_DECIDLE 0x10c
212 +#define DEC_IDLE BIT(1)
213 +
214 +#define ECC_DECENUM 0x114
215 +#define ERRNUM_S 2
216 +#define ERRNUM_M GENMASK(3, 0)
217 +
218 +#define ECC_DECDONE 0x118
219 +#define DEC_DONE7 BIT(7)
220 +#define DEC_DONE6 BIT(6)
221 +#define DEC_DONE5 BIT(5)
222 +#define DEC_DONE4 BIT(4)
223 +#define DEC_DONE3 BIT(3)
224 +#define DEC_DONE2 BIT(2)
225 +#define DEC_DONE1 BIT(1)
226 +#define DEC_DONE0 BIT(0)
227 +
228 +#define ECC_DECEL(n) (0x11c + (n) * 4)
229 +#define DEC_EL_ODD_S 16
230 +#define DEC_EL_M 0x1fff
231 +#define DEC_EL_BYTE_POS_S 3
232 +#define DEC_EL_BIT_POS_M GENMASK(2, 0)
233 +
234 +#define ECC_FDMADDR 0x13c
235 +
236 +/* ENCIDLE and DECIDLE */
237 +#define ECC_IDLE BIT(0)
238 +
239 +#define ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt) \
240 + (FIELD_PREP(ACCCON_POECS, tpoecs) | \
241 + FIELD_PREP(ACCCON_PRECS, tprecs) | \
242 + FIELD_PREP(ACCCON_C2R, tc2r) | \
243 + FIELD_PREP(ACCCON_W2R, tw2r) | \
244 + FIELD_PREP(ACCCON_WH, twh) | \
245 + FIELD_PREP(ACCCON_WST, twst) | \
246 + FIELD_PREP(ACCCON_RLT, trlt))
247 +
248 +#define MASTER_STA_MASK (MAS_ADDR | MAS_RD | MAS_WR | \
249 + MAS_RDDLY)
250 +#define NFI_RESET_TIMEOUT 1000000
251 +#define NFI_CORE_TIMEOUT 500000
252 +#define ECC_ENGINE_TIMEOUT 500000
253 +
254 +#define ECC_SECTOR_SIZE 512
255 +#define ECC_PARITY_BITS 13
256 +
257 +#define NFI_FDM_SIZE 8
258 +
259 +/* Register base */
260 +#define NFI_BASE 0x1e003000
261 +#define NFI_ECC_BASE 0x1e003800
262 +
263 +static struct mt7621_nfc nfc_dev;
264 +
265 +static const u16 mt7621_nfi_page_size[] = { SZ_512, SZ_2K, SZ_4K };
266 +static const u8 mt7621_nfi_spare_size[] = { 16, 26, 27, 28 };
267 +static const u8 mt7621_ecc_strength[] = { 4, 6, 8, 10, 12 };
268 +
269 +static inline u32 nfi_read32(struct mt7621_nfc *nfc, u32 reg)
270 +{
271 + return readl(nfc->nfi_regs + reg);
272 +}
273 +
274 +static inline void nfi_write32(struct mt7621_nfc *nfc, u32 reg, u32 val)
275 +{
276 + writel(val, nfc->nfi_regs + reg);
277 +}
278 +
279 +static inline u16 nfi_read16(struct mt7621_nfc *nfc, u32 reg)
280 +{
281 + return readw(nfc->nfi_regs + reg);
282 +}
283 +
284 +static inline void nfi_write16(struct mt7621_nfc *nfc, u32 reg, u16 val)
285 +{
286 + writew(val, nfc->nfi_regs + reg);
287 +}
288 +
289 +static inline void ecc_write16(struct mt7621_nfc *nfc, u32 reg, u16 val)
290 +{
291 + writew(val, nfc->ecc_regs + reg);
292 +}
293 +
294 +static inline u32 ecc_read32(struct mt7621_nfc *nfc, u32 reg)
295 +{
296 + return readl(nfc->ecc_regs + reg);
297 +}
298 +
299 +static inline void ecc_write32(struct mt7621_nfc *nfc, u32 reg, u32 val)
300 +{
301 + return writel(val, nfc->ecc_regs + reg);
302 +}
303 +
304 +static inline u8 *oob_fdm_ptr(struct nand_chip *nand, int sect)
305 +{
306 + return nand->oob_poi + sect * NFI_FDM_SIZE;
307 +}
308 +
309 +static inline u8 *oob_ecc_ptr(struct mt7621_nfc *nfc, int sect)
310 +{
311 + struct nand_chip *nand = &nfc->nand;
312 +
313 + return nand->oob_poi + nand->ecc.steps * NFI_FDM_SIZE +
314 + sect * (nfc->spare_per_sector - NFI_FDM_SIZE);
315 +}
316 +
317 +static inline u8 *page_data_ptr(struct nand_chip *nand, const u8 *buf,
318 + int sect)
319 +{
320 + return (u8 *)buf + sect * nand->ecc.size;
321 +}
322 +
323 +static int mt7621_ecc_wait_idle(struct mt7621_nfc *nfc, u32 reg)
324 +{
325 + u32 val;
326 + int ret;
327 +
328 + ret = readw_poll_timeout(nfc->ecc_regs + reg, val, val & ECC_IDLE,
329 + ECC_ENGINE_TIMEOUT);
330 + if (ret) {
331 + pr_warn("ECC engine timed out entering idle mode\n");
332 + return -EIO;
333 + }
334 +
335 + return 0;
336 +}
337 +
338 +static int mt7621_ecc_decoder_wait_done(struct mt7621_nfc *nfc, u32 sect)
339 +{
340 + u32 val;
341 + int ret;
342 +
343 + ret = readw_poll_timeout(nfc->ecc_regs + ECC_DECDONE, val,
344 + val & (1 << sect), ECC_ENGINE_TIMEOUT);
345 + if (ret) {
346 + pr_warn("ECC decoder for sector %d timed out\n", sect);
347 + return -ETIMEDOUT;
348 + }
349 +
350 + return 0;
351 +}
352 +
353 +static void mt7621_ecc_encoder_op(struct mt7621_nfc *nfc, bool enable)
354 +{
355 + mt7621_ecc_wait_idle(nfc, ECC_ENCIDLE);
356 + ecc_write16(nfc, ECC_ENCCON, enable ? ENC_EN : 0);
357 +}
358 +
359 +static void mt7621_ecc_decoder_op(struct mt7621_nfc *nfc, bool enable)
360 +{
361 + mt7621_ecc_wait_idle(nfc, ECC_DECIDLE);
362 + ecc_write16(nfc, ECC_DECCON, enable ? DEC_EN : 0);
363 +}
364 +
365 +static int mt7621_ecc_correct_check(struct mt7621_nfc *nfc, u8 *sector_buf,
366 + u8 *fdm_buf, u32 sect)
367 +{
368 + struct nand_chip *nand = &nfc->nand;
369 + u32 decnum, num_error_bits, fdm_end_bits;
370 + u32 error_locations, error_bit_loc;
371 + u32 error_byte_pos, error_bit_pos;
372 + int bitflips = 0;
373 + u32 i;
374 +
375 + decnum = ecc_read32(nfc, ECC_DECENUM);
376 + num_error_bits = (decnum >> (sect << ERRNUM_S)) & ERRNUM_M;
377 + fdm_end_bits = (nand->ecc.size + NFI_FDM_SIZE) << 3;
378 +
379 + if (!num_error_bits)
380 + return 0;
381 +
382 + if (num_error_bits == ERRNUM_M)
383 + return -1;
384 +
385 + for (i = 0; i < num_error_bits; i++) {
386 + error_locations = ecc_read32(nfc, ECC_DECEL(i / 2));
387 + error_bit_loc = (error_locations >> ((i % 2) * DEC_EL_ODD_S)) &
388 + DEC_EL_M;
389 + error_byte_pos = error_bit_loc >> DEC_EL_BYTE_POS_S;
390 + error_bit_pos = error_bit_loc & DEC_EL_BIT_POS_M;
391 +
392 + if (error_bit_loc < (nand->ecc.size << 3)) {
393 + if (sector_buf) {
394 + sector_buf[error_byte_pos] ^=
395 + (1 << error_bit_pos);
396 + }
397 + } else if (error_bit_loc < fdm_end_bits) {
398 + if (fdm_buf) {
399 + fdm_buf[error_byte_pos - nand->ecc.size] ^=
400 + (1 << error_bit_pos);
401 + }
402 + }
403 +
404 + bitflips++;
405 + }
406 +
407 + return bitflips;
408 +}
409 +
410 +static int mt7621_nfc_wait_write_completion(struct mt7621_nfc *nfc,
411 + struct nand_chip *nand)
412 +{
413 + u16 val;
414 + int ret;
415 +
416 + ret = readw_poll_timeout(nfc->nfi_regs + NFI_ADDRCNTR, val,
417 + FIELD_GET(SEC_CNTR, val) >= nand->ecc.steps,
418 + NFI_CORE_TIMEOUT);
419 +
420 + if (ret) {
421 + pr_warn("NFI core write operation timed out\n");
422 + return -ETIMEDOUT;
423 + }
424 +
425 + return ret;
426 +}
427 +
428 +static void mt7621_nfc_hw_reset(struct mt7621_nfc *nfc)
429 +{
430 + u32 val;
431 + int ret;
432 +
433 + /* reset all registers and force the NFI master to terminate */
434 + nfi_write16(nfc, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST);
435 +
436 + /* wait for the master to finish the last transaction */
437 + ret = readw_poll_timeout(nfc->nfi_regs + NFI_MASTER_STA, val,
438 + !(val & MASTER_STA_MASK), NFI_RESET_TIMEOUT);
439 + if (ret) {
440 + pr_warn("Failed to reset NFI master in %dms\n",
441 + NFI_RESET_TIMEOUT);
442 + }
443 +
444 + /* ensure any status register affected by the NFI master is reset */
445 + nfi_write16(nfc, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST);
446 + nfi_write16(nfc, NFI_STRDATA, 0);
447 +}
448 +
449 +static inline void mt7621_nfc_hw_init(struct mt7621_nfc *nfc)
450 +{
451 + u32 acccon;
452 +
453 + /*
454 + * CNRNB: nand ready/busy register
455 + * -------------------------------
456 + * 7:4: timeout register for polling the NAND busy/ready signal
457 + * 0 : poll the status of the busy/ready signal after [7:4]*16 cycles.
458 + */
459 + nfi_write16(nfc, NFI_CNRNB, CB2R_TIME | STR_CNRNB);
460 +
461 + mt7621_nfc_hw_reset(nfc);
462 +
463 + /* Apply default access timing */
464 + acccon = ACCTIMING(ACCCON_POECS_DEF, ACCCON_PRECS_DEF, ACCCON_C2R_DEF,
465 + ACCCON_W2R_DEF, ACCCON_WH_DEF, ACCCON_WST_DEF,
466 + ACCCON_RLT_DEF);
467 +
468 + nfi_write32(nfc, NFI_ACCCON, acccon);
469 +}
470 +
471 +static int mt7621_nfc_send_command(struct mt7621_nfc *nfc, u8 command)
472 +{
473 + u32 val;
474 + int ret;
475 +
476 + nfi_write32(nfc, NFI_CMD, command);
477 +
478 + ret = readl_poll_timeout(nfc->nfi_regs + NFI_STA, val, !(val & STA_CMD),
479 + NFI_CORE_TIMEOUT);
480 + if (ret) {
481 + pr_warn("NFI core timed out entering command mode\n");
482 + return -EIO;
483 + }
484 +
485 + return 0;
486 +}
487 +
488 +static int mt7621_nfc_send_address_byte(struct mt7621_nfc *nfc, int addr)
489 +{
490 + u32 val;
491 + int ret;
492 +
493 + nfi_write32(nfc, NFI_COLADDR, addr);
494 + nfi_write32(nfc, NFI_ROWADDR, 0);
495 + nfi_write16(nfc, NFI_ADDRNOB, 1);
496 +
497 + ret = readl_poll_timeout(nfc->nfi_regs + NFI_STA, val,
498 + !(val & STA_ADDR), NFI_CORE_TIMEOUT);
499 + if (ret) {
500 + pr_warn("NFI core timed out entering address mode\n");
501 + return -EIO;
502 + }
503 +
504 + return 0;
505 +}
506 +
507 +static void mt7621_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
508 + unsigned int ctrl)
509 +{
510 + struct mt7621_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
511 +
512 + if (ctrl & NAND_ALE) {
513 + mt7621_nfc_send_address_byte(nfc, dat & 0xff);
514 + } else if (ctrl & NAND_CLE) {
515 + mt7621_nfc_hw_reset(nfc);
516 + nfi_write16(nfc, NFI_CNFG,
517 + FIELD_PREP(CNFG_OP_MODE, CNFG_OP_CUSTOM));
518 + mt7621_nfc_send_command(nfc, dat);
519 + }
520 +}
521 +
522 +static int mt7621_nfc_dev_ready(struct mtd_info *mtd)
523 +{
524 + struct mt7621_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
525 +
526 + if (nfi_read32(nfc, NFI_STA) & STA_BUSY)
527 + return 0;
528 +
529 + return 1;
530 +}
531 +
532 +static void mt7621_nfc_select_chip(struct mtd_info *mtd, int chipnr)
533 +{
534 + struct mt7621_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
535 +
536 + nfi_write16(nfc, NFI_CSEL, 0);
537 +}
538 +
539 +static void mt7621_nfc_wait_pio_ready(struct mt7621_nfc *nfc)
540 +{
541 + int ret;
542 + u16 val;
543 +
544 + ret = readw_poll_timeout(nfc->nfi_regs + NFI_PIO_DIRDY, val,
545 + val & PIO_DIRDY, NFI_CORE_TIMEOUT);
546 + if (ret < 0)
547 + pr_err("NFI core PIO mode not ready\n");
548 +}
549 +
550 +static u32 mt7621_nfc_pio_read(struct mt7621_nfc *nfc, bool br)
551 +{
552 + u32 reg, fsm;
553 +
554 + /* after each byte read, the NFI_STA reg is reset by the hardware */
555 + reg = nfi_read32(nfc, NFI_STA);
556 + fsm = FIELD_GET(STA_NFI_FSM, reg);
557 +
558 + if (fsm != STA_FSM_CUSTOM_DATA) {
559 + reg = nfi_read16(nfc, NFI_CNFG);
560 + reg |= CNFG_READ_MODE | CNFG_BYTE_RW;
561 + if (!br)
562 + reg &= ~CNFG_BYTE_RW;
563 + nfi_write16(nfc, NFI_CNFG, reg);
564 +
565 + /*
566 + * set to max sector to allow the HW to continue reading over
567 + * unaligned accesses
568 + */
569 + nfi_write16(nfc, NFI_CON, CON_NFI_SEC | CON_NFI_BRD);
570 +
571 + /* trigger to fetch data */
572 + nfi_write16(nfc, NFI_STRDATA, STR_DATA);
573 + }
574 +
575 + mt7621_nfc_wait_pio_ready(nfc);
576 +
577 + return nfi_read32(nfc, NFI_DATAR);
578 +}
579 +
580 +static void mt7621_nfc_read_data(struct mt7621_nfc *nfc, u8 *buf, u32 len)
581 +{
582 + while (((uintptr_t)buf & 3) && len) {
583 + *buf = mt7621_nfc_pio_read(nfc, true);
584 + buf++;
585 + len--;
586 + }
587 +
588 + while (len >= 4) {
589 + *(u32 *)buf = mt7621_nfc_pio_read(nfc, false);
590 + buf += 4;
591 + len -= 4;
592 + }
593 +
594 + while (len) {
595 + *buf = mt7621_nfc_pio_read(nfc, true);
596 + buf++;
597 + len--;
598 + }
599 +}
600 +
601 +static void mt7621_nfc_read_data_discard(struct mt7621_nfc *nfc, u32 len)
602 +{
603 + while (len >= 4) {
604 + mt7621_nfc_pio_read(nfc, false);
605 + len -= 4;
606 + }
607 +
608 + while (len) {
609 + mt7621_nfc_pio_read(nfc, true);
610 + len--;
611 + }
612 +}
613 +
614 +static void mt7621_nfc_pio_write(struct mt7621_nfc *nfc, u32 val, bool bw)
615 +{
616 + u32 reg, fsm;
617 +
618 + reg = nfi_read32(nfc, NFI_STA);
619 + fsm = FIELD_GET(STA_NFI_FSM, reg);
620 +
621 + if (fsm != STA_FSM_CUSTOM_DATA) {
622 + reg = nfi_read16(nfc, NFI_CNFG);
623 + reg &= ~(CNFG_READ_MODE | CNFG_BYTE_RW);
624 + if (bw)
625 + reg |= CNFG_BYTE_RW;
626 + nfi_write16(nfc, NFI_CNFG, reg);
627 +
628 + nfi_write16(nfc, NFI_CON, CON_NFI_SEC | CON_NFI_BWR);
629 + nfi_write16(nfc, NFI_STRDATA, STR_DATA);
630 + }
631 +
632 + mt7621_nfc_wait_pio_ready(nfc);
633 + nfi_write32(nfc, NFI_DATAW, val);
634 +}
635 +
636 +static void mt7621_nfc_write_data(struct mt7621_nfc *nfc, const u8 *buf,
637 + u32 len)
638 +{
639 + while (((uintptr_t)buf & 3) && len) {
640 + mt7621_nfc_pio_write(nfc, *buf, true);
641 + buf++;
642 + len--;
643 + }
644 +
645 + while (len >= 4) {
646 + mt7621_nfc_pio_write(nfc, *(const u32 *)buf, false);
647 + buf += 4;
648 + len -= 4;
649 + }
650 +
651 + while (len) {
652 + mt7621_nfc_pio_write(nfc, *buf, true);
653 + buf++;
654 + len--;
655 + }
656 +}
657 +
658 +static void mt7621_nfc_write_data_empty(struct mt7621_nfc *nfc, u32 len)
659 +{
660 + while (len >= 4) {
661 + mt7621_nfc_pio_write(nfc, 0xffffffff, false);
662 + len -= 4;
663 + }
664 +
665 + while (len) {
666 + mt7621_nfc_pio_write(nfc, 0xff, true);
667 + len--;
668 + }
669 +}
670 +
671 +static void mt7621_nfc_write_byte(struct mtd_info *mtd, u8 byte)
672 +{
673 + struct mt7621_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
674 +
675 + mt7621_nfc_pio_write(nfc, byte, true);
676 +}
677 +
678 +static void mt7621_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
679 +{
680 + struct mt7621_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
681 +
682 + return mt7621_nfc_write_data(nfc, buf, len);
683 +}
684 +
685 +static u8 mt7621_nfc_read_byte(struct mtd_info *mtd)
686 +{
687 + struct mt7621_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
688 +
689 + return mt7621_nfc_pio_read(nfc, true);
690 +}
691 +
692 +static void mt7621_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
693 +{
694 + struct mt7621_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
695 +
696 + mt7621_nfc_read_data(nfc, buf, len);
697 +}
698 +
699 +static int mt7621_nfc_calc_ecc_strength(struct mt7621_nfc *nfc,
700 + u32 avail_ecc_bytes)
701 +{
702 + struct nand_chip *nand = &nfc->nand;
703 + struct mtd_info *mtd = nand_to_mtd(nand);
704 + u32 strength;
705 + int i;
706 +
707 + strength = avail_ecc_bytes * 8 / ECC_PARITY_BITS;
708 +
709 + /* Find the closest supported ecc strength */
710 + for (i = ARRAY_SIZE(mt7621_ecc_strength) - 1; i >= 0; i--) {
711 + if (mt7621_ecc_strength[i] <= strength)
712 + break;
713 + }
714 +
715 + if (unlikely(i < 0)) {
716 + pr_err("OOB size (%u) is not supported\n", mtd->oobsize);
717 + return -EINVAL;
718 + }
719 +
720 + nand->ecc.strength = mt7621_ecc_strength[i];
721 + nand->ecc.bytes = DIV_ROUND_UP(nand->ecc.strength * ECC_PARITY_BITS, 8);
722 +
723 + pr_debug("ECC strength adjusted to %u bits\n", nand->ecc.strength);
724 +
725 + return i;
726 +}
727 +
728 +static int mt7621_nfc_set_spare_per_sector(struct mt7621_nfc *nfc)
729 +{
730 + struct nand_chip *nand = &nfc->nand;
731 + struct mtd_info *mtd = nand_to_mtd(nand);
732 + u32 size;
733 + int i;
734 +
735 + size = nand->ecc.bytes + NFI_FDM_SIZE;
736 +
737 + /* Find the closest supported spare size */
738 + for (i = 0; i < ARRAY_SIZE(mt7621_nfi_spare_size); i++) {
739 + if (mt7621_nfi_spare_size[i] >= size)
740 + break;
741 + }
742 +
743 + if (unlikely(i >= ARRAY_SIZE(mt7621_nfi_spare_size))) {
744 + pr_err("OOB size (%u) is not supported\n", mtd->oobsize);
745 + return -EINVAL;
746 + }
747 +
748 + nfc->spare_per_sector = mt7621_nfi_spare_size[i];
749 +
750 + return i;
751 +}
752 +
753 +static int mt7621_nfc_ecc_init(struct mt7621_nfc *nfc)
754 +{
755 + struct nand_chip *nand = &nfc->nand;
756 + struct mtd_info *mtd = nand_to_mtd(nand);
757 + u32 avail_ecc_bytes, encode_block_size, decode_block_size;
758 + u32 ecc_enccfg, ecc_deccfg;
759 + int ecc_cap;
760 +
761 + nand->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
762 +
763 + nand->ecc.size = ECC_SECTOR_SIZE;
764 + nand->ecc.steps = mtd->writesize / nand->ecc.size;
765 +
766 + avail_ecc_bytes = mtd->oobsize / nand->ecc.steps - NFI_FDM_SIZE;
767 +
768 + ecc_cap = mt7621_nfc_calc_ecc_strength(nfc, avail_ecc_bytes);
769 + if (ecc_cap < 0)
770 + return ecc_cap;
771 +
772 + /* Sector + FDM */
773 + encode_block_size = (nand->ecc.size + NFI_FDM_SIZE) * 8;
774 + ecc_enccfg = ecc_cap | FIELD_PREP(ENC_MODE, ENC_MODE_NFI) |
775 + FIELD_PREP(ENC_CNFG_MSG, encode_block_size);
776 +
777 + /* Sector + FDM + ECC parity bits */
778 + decode_block_size = ((nand->ecc.size + NFI_FDM_SIZE) * 8) +
779 + nand->ecc.strength * ECC_PARITY_BITS;
780 + ecc_deccfg = ecc_cap | FIELD_PREP(DEC_MODE, DEC_MODE_NFI) |
781 + FIELD_PREP(DEC_CS, decode_block_size) |
782 + FIELD_PREP(DEC_CON, DEC_CON_EL) | DEC_EMPTY_EN;
783 +
784 + mt7621_ecc_encoder_op(nfc, false);
785 + ecc_write32(nfc, ECC_ENCCNFG, ecc_enccfg);
786 +
787 + mt7621_ecc_decoder_op(nfc, false);
788 + ecc_write32(nfc, ECC_DECCNFG, ecc_deccfg);
789 +
790 + return 0;
791 +}
792 +
793 +static int mt7621_nfc_set_page_format(struct mt7621_nfc *nfc)
794 +{
795 + struct nand_chip *nand = &nfc->nand;
796 + struct mtd_info *mtd = nand_to_mtd(nand);
797 + int i, spare_size;
798 + u32 pagefmt;
799 +
800 + spare_size = mt7621_nfc_set_spare_per_sector(nfc);
801 + if (spare_size < 0)
802 + return spare_size;
803 +
804 + for (i = 0; i < ARRAY_SIZE(mt7621_nfi_page_size); i++) {
805 + if (mt7621_nfi_page_size[i] == mtd->writesize)
806 + break;
807 + }
808 +
809 + if (unlikely(i >= ARRAY_SIZE(mt7621_nfi_page_size))) {
810 + pr_err("Page size (%u) is not supported\n", mtd->writesize);
811 + return -EINVAL;
812 + }
813 +
814 + pagefmt = FIELD_PREP(PAGEFMT_PAGE, i) |
815 + FIELD_PREP(PAGEFMT_SPARE, spare_size) |
816 + FIELD_PREP(PAGEFMT_FDM, NFI_FDM_SIZE) |
817 + FIELD_PREP(PAGEFMT_FDM_ECC, NFI_FDM_SIZE);
818 +
819 + nfi_write16(nfc, NFI_PAGEFMT, pagefmt);
820 +
821 + return 0;
822 +}
823 +
824 +static int mt7621_nfc_attach_chip(struct nand_chip *nand)
825 +{
826 + struct mt7621_nfc *nfc = nand_get_controller_data(nand);
827 + int ret;
828 +
829 + if (nand->options & NAND_BUSWIDTH_16) {
830 + pr_err("16-bit buswidth is not supported");
831 + return -EINVAL;
832 + }
833 +
834 + ret = mt7621_nfc_ecc_init(nfc);
835 + if (ret)
836 + return ret;
837 +
838 + return mt7621_nfc_set_page_format(nfc);
839 +}
840 +
841 +static void mt7621_nfc_write_fdm(struct mt7621_nfc *nfc)
842 +{
843 + struct nand_chip *nand = &nfc->nand;
844 + u32 vall, valm;
845 + u8 *oobptr;
846 + int i, j;
847 +
848 + for (i = 0; i < nand->ecc.steps; i++) {
849 + vall = 0;
850 + valm = 0;
851 + oobptr = oob_fdm_ptr(nand, i);
852 +
853 + for (j = 0; j < 4; j++)
854 + vall |= (u32)oobptr[j] << (j * 8);
855 +
856 + for (j = 0; j < 4; j++)
857 + valm |= (u32)oobptr[j + 4] << (j * 8);
858 +
859 + nfi_write32(nfc, NFI_FDML(i), vall);
860 + nfi_write32(nfc, NFI_FDMM(i), valm);
861 + }
862 +}
863 +
864 +static void mt7621_nfc_read_sector_fdm(struct mt7621_nfc *nfc, u32 sect)
865 +{
866 + struct nand_chip *nand = &nfc->nand;
867 + u32 vall, valm;
868 + u8 *oobptr;
869 + int i;
870 +
871 + vall = nfi_read32(nfc, NFI_FDML(sect));
872 + valm = nfi_read32(nfc, NFI_FDMM(sect));
873 + oobptr = oob_fdm_ptr(nand, sect);
874 +
875 + for (i = 0; i < 4; i++)
876 + oobptr[i] = (vall >> (i * 8)) & 0xff;
877 +
878 + for (i = 0; i < 4; i++)
879 + oobptr[i + 4] = (valm >> (i * 8)) & 0xff;
880 +}
881 +
882 +static int mt7621_nfc_read_page_hwecc(struct mtd_info *mtd,
883 + struct nand_chip *nand, uint8_t *buf,
884 + int oob_required, int page)
885 +{
886 + struct mt7621_nfc *nfc = nand_get_controller_data(nand);
887 + int bitflips = 0, ret = 0;
888 + int rc, i;
889 +
890 + nand_read_page_op(nand, page, 0, NULL, 0);
891 +
892 + nfi_write16(nfc, NFI_CNFG, FIELD_PREP(CNFG_OP_MODE, CNFG_OP_CUSTOM) |
893 + CNFG_READ_MODE | CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN);
894 +
895 + mt7621_ecc_decoder_op(nfc, true);
896 +
897 + nfi_write16(nfc, NFI_CON, FIELD_PREP(CON_NFI_SEC, nand->ecc.steps) |
898 + CON_NFI_BRD);
899 +
900 + for (i = 0; i < nand->ecc.steps; i++) {
901 + if (buf)
902 + mt7621_nfc_read_data(nfc, page_data_ptr(nand, buf, i),
903 + nand->ecc.size);
904 + else
905 + mt7621_nfc_read_data_discard(nfc, nand->ecc.size);
906 +
907 + rc = mt7621_ecc_decoder_wait_done(nfc, i);
908 +
909 + mt7621_nfc_read_sector_fdm(nfc, i);
910 +
911 + if (rc < 0) {
912 + ret = -EIO;
913 + continue;
914 + }
915 +
916 + rc = mt7621_ecc_correct_check(nfc,
917 + buf ? page_data_ptr(nand, buf, i) : NULL,
918 + oob_fdm_ptr(nand, i), i);
919 +
920 + if (rc < 0) {
921 + pr_warn("Uncorrectable ECC error at page %d step %d\n",
922 + page, i);
923 + bitflips = nand->ecc.strength + 1;
924 + mtd->ecc_stats.failed++;
925 + } else {
926 + if (rc > bitflips)
927 + bitflips = rc;
928 + mtd->ecc_stats.corrected += rc;
929 + }
930 + }
931 +
932 + mt7621_ecc_decoder_op(nfc, false);
933 +
934 + nfi_write16(nfc, NFI_CON, 0);
935 +
936 + if (ret < 0)
937 + return ret;
938 +
939 + return bitflips;
940 +}
941 +
942 +static int mt7621_nfc_read_page_raw(struct mtd_info *mtd,
943 + struct nand_chip *nand, uint8_t *buf,
944 + int oob_required, int page)
945 +{
946 + struct mt7621_nfc *nfc = nand_get_controller_data(nand);
947 + int i;
948 +
949 + nand_read_page_op(nand, page, 0, NULL, 0);
950 +
951 + nfi_write16(nfc, NFI_CNFG, FIELD_PREP(CNFG_OP_MODE, CNFG_OP_CUSTOM) |
952 + CNFG_READ_MODE);
953 +
954 + nfi_write16(nfc, NFI_CON, FIELD_PREP(CON_NFI_SEC, nand->ecc.steps) |
955 + CON_NFI_BRD);
956 +
957 + for (i = 0; i < nand->ecc.steps; i++) {
958 + /* Read data */
959 + if (buf)
960 + mt7621_nfc_read_data(nfc, page_data_ptr(nand, buf, i),
961 + nand->ecc.size);
962 + else
963 + mt7621_nfc_read_data_discard(nfc, nand->ecc.size);
964 +
965 + /* Read FDM */
966 + mt7621_nfc_read_data(nfc, oob_fdm_ptr(nand, i), NFI_FDM_SIZE);
967 +
968 + /* Read ECC parity data */
969 + mt7621_nfc_read_data(nfc, oob_ecc_ptr(nfc, i),
970 + nfc->spare_per_sector - NFI_FDM_SIZE);
971 + }
972 +
973 + nfi_write16(nfc, NFI_CON, 0);
974 +
975 + return 0;
976 +}
977 +
978 +static int mt7621_nfc_read_oob_hwecc(struct mtd_info *mtd,
979 + struct nand_chip *nand, int page)
980 +{
981 + return mt7621_nfc_read_page_hwecc(mtd, nand, NULL, 1, page);
982 +}
983 +
984 +static int mt7621_nfc_read_oob_raw(struct mtd_info *mtd,
985 + struct nand_chip *nand, int page)
986 +{
987 + return mt7621_nfc_read_page_raw(mtd, nand, NULL, 1, page);
988 +}
989 +
990 +static int mt7621_nfc_check_empty_page(struct nand_chip *nand, const u8 *buf)
991 +{
992 + struct mtd_info *mtd = nand_to_mtd(nand);
993 + u8 *oobptr;
994 + u32 i, j;
995 +
996 + if (buf) {
997 + for (i = 0; i < mtd->writesize; i++)
998 + if (buf[i] != 0xff)
999 + return 0;
1000 + }
1001 +
1002 + for (i = 0; i < nand->ecc.steps; i++) {
1003 + oobptr = oob_fdm_ptr(nand, i);
1004 + for (j = 0; j < NFI_FDM_SIZE; j++)
1005 + if (oobptr[j] != 0xff)
1006 + return 0;
1007 + }
1008 +
1009 + return 1;
1010 +}
1011 +
1012 +static int mt7621_nfc_write_page_hwecc(struct mtd_info *mtd,
1013 + struct nand_chip *nand,
1014 + const u8 *buf, int oob_required,
1015 + int page)
1016 +{
1017 + struct mt7621_nfc *nfc = nand_get_controller_data(nand);
1018 +
1019 + if (mt7621_nfc_check_empty_page(nand, buf)) {
1020 + /*
1021 + * MT7621 ECC engine always generates parity code for input
1022 + * pages, even for empty pages. Doing so will write back ECC
1023 + * parity code to the oob region, which means such pages will
1024 + * no longer be empty pages.
1025 + *
1026 + * To avoid this, stop write operation if current page is an
1027 + * empty page.
1028 + */
1029 + return 0;
1030 + }
1031 +
1032 + nand_prog_page_begin_op(nand, page, 0, NULL, 0);
1033 +
1034 + nfi_write16(nfc, NFI_CNFG, FIELD_PREP(CNFG_OP_MODE, CNFG_OP_CUSTOM) |
1035 + CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN);
1036 +
1037 + mt7621_ecc_encoder_op(nfc, true);
1038 +
1039 + mt7621_nfc_write_fdm(nfc);
1040 +
1041 + nfi_write16(nfc, NFI_CON, FIELD_PREP(CON_NFI_SEC, nand->ecc.steps) |
1042 + CON_NFI_BWR);
1043 +
1044 + if (buf)
1045 + mt7621_nfc_write_data(nfc, buf, mtd->writesize);
1046 + else
1047 + mt7621_nfc_write_data_empty(nfc, mtd->writesize);
1048 +
1049 + mt7621_nfc_wait_write_completion(nfc, nand);
1050 +
1051 + mt7621_ecc_encoder_op(nfc, false);
1052 +
1053 + nfi_write16(nfc, NFI_CON, 0);
1054 +
1055 + return nand_prog_page_end_op(nand);
1056 +}
1057 +
1058 +static int mt7621_nfc_write_page_raw(struct mtd_info *mtd,
1059 + struct nand_chip *nand,
1060 + const u8 *buf, int oob_required,
1061 + int page)
1062 +{
1063 + struct mt7621_nfc *nfc = nand_get_controller_data(nand);
1064 + int i;
1065 +
1066 + nand_prog_page_begin_op(nand, page, 0, NULL, 0);
1067 +
1068 + nfi_write16(nfc, NFI_CNFG, FIELD_PREP(CNFG_OP_MODE, CNFG_OP_CUSTOM));
1069 +
1070 + nfi_write16(nfc, NFI_CON, FIELD_PREP(CON_NFI_SEC, nand->ecc.steps) |
1071 + CON_NFI_BWR);
1072 +
1073 + for (i = 0; i < nand->ecc.steps; i++) {
1074 + /* Write data */
1075 + if (buf)
1076 + mt7621_nfc_write_data(nfc, page_data_ptr(nand, buf, i),
1077 + nand->ecc.size);
1078 + else
1079 + mt7621_nfc_write_data_empty(nfc, nand->ecc.size);
1080 +
1081 + /* Write FDM */
1082 + mt7621_nfc_write_data(nfc, oob_fdm_ptr(nand, i),
1083 + NFI_FDM_SIZE);
1084 +
1085 + /* Write dummy ECC parity data */
1086 + mt7621_nfc_write_data_empty(nfc, nfc->spare_per_sector -
1087 + NFI_FDM_SIZE);
1088 + }
1089 +
1090 + mt7621_nfc_wait_write_completion(nfc, nand);
1091 +
1092 + nfi_write16(nfc, NFI_CON, 0);
1093 +
1094 + return nand_prog_page_end_op(nand);
1095 +}
1096 +
1097 +static int mt7621_nfc_write_oob_hwecc(struct mtd_info *mtd,
1098 + struct nand_chip *nand, int page)
1099 +{
1100 + return mt7621_nfc_write_page_hwecc(mtd, nand, NULL, 1, page);
1101 +}
1102 +
1103 +static int mt7621_nfc_write_oob_raw(struct mtd_info *mtd,
1104 + struct nand_chip *nand, int page)
1105 +{
1106 + return mt7621_nfc_write_page_raw(mtd, nand, NULL, 1, page);
1107 +}
1108 +
1109 +static int mt7621_nfc_ooblayout_free(struct mtd_info *mtd, int section,
1110 + struct mtd_oob_region *oob_region)
1111 +{
1112 + struct nand_chip *nand = mtd_to_nand(mtd);
1113 +
1114 + if (section >= nand->ecc.steps)
1115 + return -ERANGE;
1116 +
1117 + oob_region->length = NFI_FDM_SIZE - 1;
1118 + oob_region->offset = section * NFI_FDM_SIZE + 1;
1119 +
1120 + return 0;
1121 +}
1122 +
1123 +static int mt7621_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
1124 + struct mtd_oob_region *oob_region)
1125 +{
1126 + struct nand_chip *nand = mtd_to_nand(mtd);
1127 +
1128 + if (section)
1129 + return -ERANGE;
1130 +
1131 + oob_region->offset = NFI_FDM_SIZE * nand->ecc.steps;
1132 + oob_region->length = mtd->oobsize - oob_region->offset;
1133 +
1134 + return 0;
1135 +}
1136 +
1137 +static const struct mtd_ooblayout_ops mt7621_nfc_ooblayout_ops = {
1138 + .rfree = mt7621_nfc_ooblayout_free,
1139 + .ecc = mt7621_nfc_ooblayout_ecc,
1140 +};
1141 +
1142 +/*
1143 + * This function will override the default one which is not supposed to be
1144 + * used for ECC syndrome based pages.
1145 + */
1146 +static int mt7621_nfc_block_bad(struct mtd_info *mtd, loff_t ofs)
1147 +{
1148 + struct nand_chip *nand = mtd_to_nand(mtd);
1149 + struct mtd_oob_ops ops;
1150 + int ret, i = 0;
1151 + u16 bad;
1152 +
1153 + memset(&ops, 0, sizeof(ops));
1154 + ops.oobbuf = (uint8_t *)&bad;
1155 + ops.ooboffs = nand->badblockpos;
1156 + if (nand->options & NAND_BUSWIDTH_16) {
1157 + ops.ooboffs &= ~0x01;
1158 + ops.ooblen = 2;
1159 + } else {
1160 + ops.ooblen = 1;
1161 + }
1162 + ops.mode = MTD_OPS_RAW;
1163 +
1164 + /* Read from first/last page(s) if necessary */
1165 + if (nand->bbt_options & NAND_BBT_SCANLASTPAGE)
1166 + ofs += mtd->erasesize - mtd->writesize;
1167 +
1168 + do {
1169 + ret = mtd_read_oob(mtd, ofs, &ops);
1170 + if (ret)
1171 + return ret;
1172 +
1173 + if (likely(nand->badblockbits == 8))
1174 + ret = bad != 0xFF;
1175 + else
1176 + ret = hweight8(bad) < nand->badblockbits;
1177 +
1178 + i++;
1179 + ofs += mtd->writesize;
1180 + } while (!ret && (nand->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
1181 +
1182 + return ret;
1183 +}
1184 +
1185 +static void mt7621_nfc_init_chip(struct mt7621_nfc *nfc)
1186 +{
1187 + struct nand_chip *nand = &nfc->nand;
1188 + struct mtd_info *mtd;
1189 + int ret;
1190 +
1191 + nand_set_controller_data(nand, nfc);
1192 +
1193 + nand->options |= NAND_NO_SUBPAGE_WRITE;
1194 +
1195 + nand->ecc.mode = NAND_ECC_HW_SYNDROME;
1196 + nand->ecc.read_page = mt7621_nfc_read_page_hwecc;
1197 + nand->ecc.read_page_raw = mt7621_nfc_read_page_raw;
1198 + nand->ecc.write_page = mt7621_nfc_write_page_hwecc;
1199 + nand->ecc.write_page_raw = mt7621_nfc_write_page_raw;
1200 + nand->ecc.read_oob = mt7621_nfc_read_oob_hwecc;
1201 + nand->ecc.read_oob_raw = mt7621_nfc_read_oob_raw;
1202 + nand->ecc.write_oob = mt7621_nfc_write_oob_hwecc;
1203 + nand->ecc.write_oob_raw = mt7621_nfc_write_oob_raw;
1204 +
1205 + nand->dev_ready = mt7621_nfc_dev_ready;
1206 + nand->select_chip = mt7621_nfc_select_chip;
1207 + nand->write_byte = mt7621_nfc_write_byte;
1208 + nand->write_buf = mt7621_nfc_write_buf;
1209 + nand->read_byte = mt7621_nfc_read_byte;
1210 + nand->read_buf = mt7621_nfc_read_buf;
1211 + nand->cmd_ctrl = mt7621_nfc_cmd_ctrl;
1212 + nand->block_bad = mt7621_nfc_block_bad;
1213 +
1214 + mtd = nand_to_mtd(nand);
1215 + mtd_set_ooblayout(mtd, &mt7621_nfc_ooblayout_ops);
1216 +
1217 + /* Reset NFI master */
1218 + mt7621_nfc_hw_init(nfc);
1219 +
1220 + ret = nand_scan_ident(mtd, 1, NULL);
1221 + if (ret)
1222 + return;
1223 +
1224 + mt7621_nfc_attach_chip(nand);
1225 +
1226 + ret = nand_scan_tail(mtd);
1227 + if (ret)
1228 + return;
1229 +
1230 + nand_register(0, mtd);
1231 +}
1232 +
1233 +static void mt7621_nfc_set_regs(struct mt7621_nfc *nfc)
1234 +{
1235 + nfc->nfi_regs = (void __iomem *)CKSEG1ADDR(NFI_BASE);
1236 + nfc->ecc_regs = (void __iomem *)CKSEG1ADDR(NFI_ECC_BASE);
1237 +}
1238 +
1239 +void mt7621_nfc_spl_init(struct mt7621_nfc *nfc)
1240 +{
1241 + struct nand_chip *nand = &nfc->nand;
1242 +
1243 + mt7621_nfc_set_regs(nfc);
1244 +
1245 + nand_set_controller_data(nand, nfc);
1246 +
1247 + nand->options |= NAND_NO_SUBPAGE_WRITE;
1248 +
1249 + nand->ecc.mode = NAND_ECC_HW_SYNDROME;
1250 + nand->ecc.read_page = mt7621_nfc_read_page_hwecc;
1251 +
1252 + nand->dev_ready = mt7621_nfc_dev_ready;
1253 + nand->select_chip = mt7621_nfc_select_chip;
1254 + nand->read_byte = mt7621_nfc_read_byte;
1255 + nand->read_buf = mt7621_nfc_read_buf;
1256 + nand->cmd_ctrl = mt7621_nfc_cmd_ctrl;
1257 +
1258 + /* Reset NFI master */
1259 + mt7621_nfc_hw_init(nfc);
1260 +}
1261 +
1262 +int mt7621_nfc_spl_post_init(struct mt7621_nfc *nfc)
1263 +{
1264 + struct nand_chip *nand = &nfc->nand;
1265 + int nand_maf_id, nand_dev_id;
1266 + struct nand_flash_dev *type;
1267 +
1268 + type = nand_get_flash_type(&nand->mtd, nand, &nand_maf_id,
1269 + &nand_dev_id, NULL);
1270 +
1271 + if (IS_ERR(type))
1272 + return PTR_ERR(type);
1273 +
1274 + nand->numchips = 1;
1275 + nand->mtd.size = nand->chipsize;
1276 +
1277 + return mt7621_nfc_attach_chip(nand);
1278 +}
1279 +
1280 +void board_nand_init(void)
1281 +{
1282 + mt7621_nfc_set_regs(&nfc_dev);
1283 + mt7621_nfc_init_chip(&nfc_dev);
1284 +}
1285 --- /dev/null
1286 +++ b/drivers/mtd/nand/raw/mt7621_nand.h
1287 @@ -0,0 +1,29 @@
1288 +/* SPDX-License-Identifier: GPL-2.0 */
1289 +/*
1290 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
1291 + *
1292 + * Author: Weijie Gao <weijie.gao@mediatek.com>
1293 + */
1294 +
1295 +#ifndef _MT7621_NAND_H_
1296 +#define _MT7621_NAND_H_
1297 +
1298 +#include <linux/types.h>
1299 +#include <linux/mtd/mtd.h>
1300 +#include <linux/compiler.h>
1301 +#include <linux/mtd/rawnand.h>
1302 +
1303 +struct mt7621_nfc {
1304 + struct nand_chip nand;
1305 +
1306 + void __iomem *nfi_regs;
1307 + void __iomem *ecc_regs;
1308 +
1309 + u32 spare_per_sector;
1310 +};
1311 +
1312 +/* for SPL */
1313 +void mt7621_nfc_spl_init(struct mt7621_nfc *nfc);
1314 +int mt7621_nfc_spl_post_init(struct mt7621_nfc *nfc);
1315 +
1316 +#endif /* _MT7621_NAND_H_ */
1317 --- /dev/null
1318 +++ b/drivers/mtd/nand/raw/mt7621_nand_spl.c
1319 @@ -0,0 +1,237 @@
1320 +// SPDX-License-Identifier: GPL-2.0
1321 +/*
1322 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
1323 + *
1324 + * Author: Weijie Gao <weijie.gao@mediatek.com>
1325 + */
1326 +
1327 +#include <image.h>
1328 +#include <malloc.h>
1329 +#include <linux/sizes.h>
1330 +#include <linux/delay.h>
1331 +#include <linux/mtd/rawnand.h>
1332 +#include "mt7621_nand.h"
1333 +
1334 +static struct mt7621_nfc nfc_dev;
1335 +static u8 *buffer;
1336 +static int nand_valid;
1337 +
1338 +static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
1339 + int column, int page_addr)
1340 +{
1341 + register struct nand_chip *chip = mtd_to_nand(mtd);
1342 +
1343 + /* Command latch cycle */
1344 + chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1345 +
1346 + if (column != -1 || page_addr != -1) {
1347 + int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1348 +
1349 + /* Serially input address */
1350 + if (column != -1) {
1351 + chip->cmd_ctrl(mtd, column, ctrl);
1352 + ctrl &= ~NAND_CTRL_CHANGE;
1353 + if (command != NAND_CMD_READID)
1354 + chip->cmd_ctrl(mtd, column >> 8, ctrl);
1355 + }
1356 + if (page_addr != -1) {
1357 + chip->cmd_ctrl(mtd, page_addr, ctrl);
1358 + chip->cmd_ctrl(mtd, page_addr >> 8,
1359 + NAND_NCE | NAND_ALE);
1360 + if (chip->options & NAND_ROW_ADDR_3)
1361 + chip->cmd_ctrl(mtd, page_addr >> 16,
1362 + NAND_NCE | NAND_ALE);
1363 + }
1364 + }
1365 + chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1366 +
1367 + /*
1368 + * Program and erase have their own busy handlers status, sequential
1369 + * in and status need no delay.
1370 + */
1371 + switch (command) {
1372 + case NAND_CMD_STATUS:
1373 + case NAND_CMD_READID:
1374 + case NAND_CMD_SET_FEATURES:
1375 + return;
1376 +
1377 + case NAND_CMD_READ0:
1378 + chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
1379 + NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1380 + chip->cmd_ctrl(mtd, NAND_CMD_NONE,
1381 + NAND_NCE | NAND_CTRL_CHANGE);
1382 + }
1383 +
1384 + /*
1385 + * Apply this short delay always to ensure that we do wait tWB in
1386 + * any case on any machine.
1387 + */
1388 + ndelay(100);
1389 +
1390 + nand_wait_ready(mtd);
1391 +}
1392 +
1393 +static int nfc_read_page_hwecc(struct mtd_info *mtd, void *buf,
1394 + unsigned int page)
1395 +{
1396 + struct nand_chip *chip = mtd_to_nand(mtd);
1397 + int ret;
1398 +
1399 + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page);
1400 +
1401 + ret = chip->ecc.read_page(mtd, chip, buf, 1, page);
1402 + if (ret < 0 || ret > chip->ecc.strength)
1403 + return -1;
1404 +
1405 + return 0;
1406 +}
1407 +
1408 +static int nfc_read_oob_hwecc(struct mtd_info *mtd, void *buf, u32 len,
1409 + unsigned int page)
1410 +{
1411 + struct nand_chip *chip = mtd_to_nand(mtd);
1412 + int ret;
1413 +
1414 + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page);
1415 +
1416 + ret = chip->ecc.read_page(mtd, chip, NULL, 1, page);
1417 + if (ret < 0)
1418 + return -1;
1419 +
1420 + if (len > mtd->oobsize)
1421 + len = mtd->oobsize;
1422 +
1423 + memcpy(buf, chip->oob_poi, len);
1424 +
1425 + return 0;
1426 +}
1427 +
1428 +static int nfc_check_bad_block(struct mtd_info *mtd, unsigned int page)
1429 +{
1430 + struct nand_chip *chip = mtd_to_nand(mtd);
1431 + u32 pages_per_block, i = 0;
1432 + int ret;
1433 + u8 bad;
1434 +
1435 + pages_per_block = 1 << (mtd->erasesize_shift - mtd->writesize_shift);
1436 +
1437 + /* Read from first/last page(s) if necessary */
1438 + if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) {
1439 + page += pages_per_block - 1;
1440 + if (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)
1441 + page--;
1442 + }
1443 +
1444 + do {
1445 + ret = nfc_read_oob_hwecc(mtd, &bad, 1, page);
1446 + if (ret)
1447 + return ret;
1448 +
1449 + ret = bad != 0xFF;
1450 +
1451 + i++;
1452 + page++;
1453 + } while (!ret && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
1454 +
1455 + return ret;
1456 +}
1457 +
1458 +int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
1459 +{
1460 + struct mt7621_nfc *nfc = &nfc_dev;
1461 + struct nand_chip *chip = &nfc->nand;
1462 + struct mtd_info *mtd = &chip->mtd;
1463 + u32 addr, col, page, chksz;
1464 + bool check_bad = true;
1465 +
1466 + if (!nand_valid)
1467 + return -ENODEV;
1468 +
1469 + while (size) {
1470 + if (check_bad || !(offs & mtd->erasesize_mask)) {
1471 + addr = offs & (~mtd->erasesize_mask);
1472 + page = addr >> mtd->writesize_shift;
1473 + if (nfc_check_bad_block(mtd, page)) {
1474 + /* Skip bad block */
1475 + if (addr >= mtd->size - mtd->erasesize)
1476 + return -1;
1477 +
1478 + offs += mtd->erasesize;
1479 + continue;
1480 + }
1481 +
1482 + check_bad = false;
1483 + }
1484 +
1485 + col = offs & mtd->writesize_mask;
1486 + page = offs >> mtd->writesize_shift;
1487 + chksz = min(mtd->writesize - col, (uint32_t)size);
1488 +
1489 + if (unlikely(chksz < mtd->writesize)) {
1490 + /* Not reading a full page */
1491 + if (nfc_read_page_hwecc(mtd, buffer, page))
1492 + return -1;
1493 +
1494 + memcpy(dest, buffer + col, chksz);
1495 + } else {
1496 + if (nfc_read_page_hwecc(mtd, dest, page))
1497 + return -1;
1498 + }
1499 +
1500 + dest += chksz;
1501 + offs += chksz;
1502 + size -= chksz;
1503 + }
1504 +
1505 + return 0;
1506 +}
1507 +
1508 +int nand_default_bbt(struct mtd_info *mtd)
1509 +{
1510 + return 0;
1511 +}
1512 +
1513 +unsigned long nand_size(void)
1514 +{
1515 + if (!nand_valid)
1516 + return 0;
1517 +
1518 + /* Unlikely that NAND size > 2GBytes */
1519 + if (nfc_dev.nand.chipsize <= SZ_2G)
1520 + return nfc_dev.nand.chipsize;
1521 +
1522 + return SZ_2G;
1523 +}
1524 +
1525 +void nand_deselect(void)
1526 +{
1527 +}
1528 +
1529 +void nand_init(void)
1530 +{
1531 + struct mtd_info *mtd;
1532 + struct nand_chip *chip;
1533 +
1534 + if (nand_valid)
1535 + return;
1536 +
1537 + mt7621_nfc_spl_init(&nfc_dev);
1538 +
1539 + chip = &nfc_dev.nand;
1540 + mtd = &chip->mtd;
1541 + chip->cmdfunc = nand_command_lp;
1542 +
1543 + if (mt7621_nfc_spl_post_init(&nfc_dev))
1544 + return;
1545 +
1546 + mtd->erasesize_shift = ffs(mtd->erasesize) - 1;
1547 + mtd->writesize_shift = ffs(mtd->writesize) - 1;
1548 + mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1;
1549 + mtd->writesize_mask = (1 << mtd->writesize_shift) - 1;
1550 +
1551 + buffer = malloc(mtd->writesize);
1552 + if (!buffer)
1553 + return;
1554 +
1555 + nand_valid = 1;
1556 +}
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