package/boot/uboot-mediatek/patches/001-mtk-0001-mips-add-asm-mipsmtregs.h-for-MIPS-multi-threading.patch

   1 From 65a4a80157bacde3cf86ce8cbc9a08f5f05ad9bb Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Fri, 20 May 2022 11:21:34 +0800
   4 Subject: [PATCH 01/25] mips: add asm/mipsmtregs.h for MIPS multi-threading
   5
   6 To be compatible with old u-boot used by lots of MT7621 devices, the u-boot
   7 needs to boot-up MT7621's all cores, and all VPES of each core.
   8
   9 This patch adds asm/mipsmtregs.h from linux kernel which is need for
  10 boot-up VPEs.
  11
  12 Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
  13 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  14 ---
  15  arch/mips/include/asm/mipsmtregs.h | 142 +++++++++++++++++++++++++++++
  16  1 file changed, 142 insertions(+)
  17  create mode 100644 arch/mips/include/asm/mipsmtregs.h
  18
  19 --- /dev/null
  20 +++ b/arch/mips/include/asm/mipsmtregs.h
  21 @@ -0,0 +1,142 @@
  22 +/* SPDX-License-Identifier: GPL-2.0 */
  23 +/*
  24 + * MT regs definitions, follows on from mipsregs.h
  25 + * Copyright (C) 2004 - 2005 MIPS Technologies, Inc.  All rights reserved.
  26 + * Elizabeth Clarke et. al.
  27 + *
  28 + */
  29 +#ifndef _ASM_MIPSMTREGS_H
  30 +#define _ASM_MIPSMTREGS_H
  31 +
  32 +#include <asm/mipsregs.h>
  33 +
  34 +/*
  35 + * Macros for use in assembly language code
  36 + */
  37 +
  38 +#define CP0_MVPCONTROL         $0, 1
  39 +#define CP0_MVPCONF0           $0, 2
  40 +#define CP0_MVPCONF1           $0, 3
  41 +#define CP0_VPECONTROL         $1, 1
  42 +#define CP0_VPECONF0           $1, 2
  43 +#define CP0_VPECONF1           $1, 3
  44 +#define CP0_YQMASK             $1, 4
  45 +#define CP0_VPESCHEDULE                $1, 5
  46 +#define CP0_VPESCHEFBK         $1, 6
  47 +#define CP0_TCSTATUS           $2, 1
  48 +#define CP0_TCBIND             $2, 2
  49 +#define CP0_TCRESTART          $2, 3
  50 +#define CP0_TCHALT             $2, 4
  51 +#define CP0_TCCONTEXT          $2, 5
  52 +#define CP0_TCSCHEDULE         $2, 6
  53 +#define CP0_TCSCHEFBK          $2, 7
  54 +#define CP0_SRSCONF0           $6, 1
  55 +#define CP0_SRSCONF1           $6, 2
  56 +#define CP0_SRSCONF2           $6, 3
  57 +#define CP0_SRSCONF3           $6, 4
  58 +#define CP0_SRSCONF4           $6, 5
  59 +
  60 +/* MVPControl fields */
  61 +#define MVPCONTROL_EVP         (_ULCAST_(1))
  62 +
  63 +#define MVPCONTROL_VPC_SHIFT   1
  64 +#define MVPCONTROL_VPC         (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT)
  65 +
  66 +#define MVPCONTROL_STLB_SHIFT  2
  67 +#define MVPCONTROL_STLB                (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)
  68 +
  69 +/* MVPConf0 fields */
  70 +#define MVPCONF0_PTC_SHIFT     0
  71 +#define MVPCONF0_PTC           (_ULCAST_(0xff))
  72 +#define MVPCONF0_PVPE_SHIFT    10
  73 +#define MVPCONF0_PVPE          (_ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
  74 +#define MVPCONF0_TCA_SHIFT     15
  75 +#define MVPCONF0_TCA           (_ULCAST_(1) << MVPCONF0_TCA_SHIFT)
  76 +#define MVPCONF0_PTLBE_SHIFT   16
  77 +#define MVPCONF0_PTLBE         (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT)
  78 +#define MVPCONF0_TLBS_SHIFT    29
  79 +#define MVPCONF0_TLBS          (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT)
  80 +#define MVPCONF0_M_SHIFT       31
  81 +#define MVPCONF0_M             (_ULCAST_(0x1) << MVPCONF0_M_SHIFT)
  82 +
  83 +/* config3 fields */
  84 +#define CONFIG3_MT_SHIFT       2
  85 +#define CONFIG3_MT             (_ULCAST_(1) << CONFIG3_MT_SHIFT)
  86 +
  87 +/* VPEControl fields (per VPE) */
  88 +#define VPECONTROL_TARGTC      (_ULCAST_(0xff))
  89 +
  90 +#define VPECONTROL_TE_SHIFT    15
  91 +#define VPECONTROL_TE          (_ULCAST_(1) << VPECONTROL_TE_SHIFT)
  92 +#define VPECONTROL_EXCPT_SHIFT 16
  93 +#define VPECONTROL_EXCPT       (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT)
  94 +
  95 +/* Thread Exception Codes for EXCPT field */
  96 +#define THREX_TU               0
  97 +#define THREX_TO               1
  98 +#define THREX_IYQ              2
  99 +#define THREX_GSX              3
 100 +#define THREX_YSCH             4
 101 +#define THREX_GSSCH            5
 102 +
 103 +#define VPECONTROL_GSI_SHIFT   20
 104 +#define VPECONTROL_GSI         (_ULCAST_(1) << VPECONTROL_GSI_SHIFT)
 105 +#define VPECONTROL_YSI_SHIFT   21
 106 +#define VPECONTROL_YSI         (_ULCAST_(1) << VPECONTROL_YSI_SHIFT)
 107 +
 108 +/* VPEConf0 fields (per VPE) */
 109 +#define VPECONF0_VPA_SHIFT     0
 110 +#define VPECONF0_VPA           (_ULCAST_(1) << VPECONF0_VPA_SHIFT)
 111 +#define VPECONF0_MVP_SHIFT     1
 112 +#define VPECONF0_MVP           (_ULCAST_(1) << VPECONF0_MVP_SHIFT)
 113 +#define VPECONF0_XTC_SHIFT     21
 114 +#define VPECONF0_XTC           (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
 115 +
 116 +/* VPEConf1 fields (per VPE) */
 117 +#define VPECONF1_NCP1_SHIFT    0
 118 +#define VPECONF1_NCP1          (_ULCAST_(0xff) << VPECONF1_NCP1_SHIFT)
 119 +#define VPECONF1_NCP2_SHIFT    10
 120 +#define VPECONF1_NCP2          (_ULCAST_(0xff) << VPECONF1_NCP2_SHIFT)
 121 +#define VPECONF1_NCX_SHIFT     20
 122 +#define VPECONF1_NCX           (_ULCAST_(0xff) << VPECONF1_NCX_SHIFT)
 123 +
 124 +/* TCStatus fields (per TC) */
 125 +#define TCSTATUS_TASID         (_ULCAST_(0xff))
 126 +#define TCSTATUS_IXMT_SHIFT    10
 127 +#define TCSTATUS_IXMT          (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT)
 128 +#define TCSTATUS_TKSU_SHIFT    11
 129 +#define TCSTATUS_TKSU          (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT)
 130 +#define TCSTATUS_A_SHIFT       13
 131 +#define TCSTATUS_A             (_ULCAST_(1) << TCSTATUS_A_SHIFT)
 132 +#define TCSTATUS_DA_SHIFT      15
 133 +#define TCSTATUS_DA            (_ULCAST_(1) << TCSTATUS_DA_SHIFT)
 134 +#define TCSTATUS_DT_SHIFT      20
 135 +#define TCSTATUS_DT            (_ULCAST_(1) << TCSTATUS_DT_SHIFT)
 136 +#define TCSTATUS_TDS_SHIFT     21
 137 +#define TCSTATUS_TDS           (_ULCAST_(1) << TCSTATUS_TDS_SHIFT)
 138 +#define TCSTATUS_TSST_SHIFT    22
 139 +#define TCSTATUS_TSST          (_ULCAST_(1) << TCSTATUS_TSST_SHIFT)
 140 +#define TCSTATUS_RNST_SHIFT    23
 141 +#define TCSTATUS_RNST          (_ULCAST_(3) << TCSTATUS_RNST_SHIFT)
 142 +/* Codes for RNST */
 143 +#define TC_RUNNING             0
 144 +#define TC_WAITING             1
 145 +#define TC_YIELDING            2
 146 +#define TC_GATED               3
 147 +
 148 +#define TCSTATUS_TMX_SHIFT     27
 149 +#define TCSTATUS_TMX           (_ULCAST_(1) << TCSTATUS_TMX_SHIFT)
 150 +/* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */
 151 +
 152 +/* TCBind */
 153 +#define TCBIND_CURVPE_SHIFT    0
 154 +#define TCBIND_CURVPE          (_ULCAST_(0xf))
 155 +
 156 +#define TCBIND_CURTC_SHIFT     21
 157 +
 158 +#define TCBIND_CURTC           (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT)
 159 +
 160 +/* TCHalt */
 161 +#define TCHALT_H               (_ULCAST_(1))
 162 +
 163 +#endif