toolchain/binutils/patches/2.40/026-RISC-V-make-C-extension-JAL-available-again-for-32-b.patch

   1 From 27f59ec47a18277b6ea3548f405263ef558f5217 Mon Sep 17 00:00:00 2001
   2 From: Jan Beulich <jbeulich@suse.com>
   3 Date: Tue, 31 Jan 2023 09:47:22 +0100
   4 Subject: [PATCH 26/50] RISC-V: make C-extension JAL available again for
   5  (32-bit) assembly
   6
   7 Along with the normal JAL alias, the C-extension one should have been
   8 moved as well by 839189bc932e ("RISC-V: re-arrange opcode table for
   9 consistent alias handling"), for the assembler to actually be able to
  10 use it where/when possible.
  11
  12 Since neither this nor any other compressed branch insn was being tested
  13 so far, take the opportunity and introduce a new testcase covering those.
  14 ---
  15  gas/config/tc-riscv.c                 |  3 +++
  16  gas/testsuite/gas/riscv/c-branch-na.d | 20 ++++++++++++++++++++
  17  gas/testsuite/gas/riscv/c-branch.d    | 19 +++++++++++++++++++
  18  gas/testsuite/gas/riscv/c-branch.s    | 11 +++++++++++
  19  opcodes/riscv-opc.c                   |  2 +-
  20  5 files changed, 54 insertions(+), 1 deletion(-)
  21  create mode 100644 gas/testsuite/gas/riscv/c-branch-na.d
  22  create mode 100644 gas/testsuite/gas/riscv/c-branch.d
  23  create mode 100644 gas/testsuite/gas/riscv/c-branch.s
  24
  25 --- a/gas/config/tc-riscv.c
  26 +++ b/gas/config/tc-riscv.c
  27 @@ -2762,6 +2762,8 @@ riscv_ip (char *str, struct riscv_cl_ins
  28                 case 'p':
  29                   goto branch;
  30                 case 'a':
  31 +                 if (oparg == insn->args + 1)
  32 +                   goto jump_check_gpr;
  33                   goto jump;
  34                 case 'S': /* Floating-point RS1 x8-x15.  */
  35                   if (!reg_lookup (&asarg, RCLASS_FPR, &regno)
  36 @@ -3271,6 +3273,7 @@ riscv_ip (char *str, struct riscv_cl_ins
  37                  but the 2nd (with 2 operands) might.  */
  38               if (oparg == insn->args)
  39                 {
  40 +           jump_check_gpr:
  41                   asargStart = asarg;
  42                   if (reg_lookup (&asarg, RCLASS_GPR, NULL)
  43                       && (*asarg == ',' || (ISSPACE (*asarg) && asarg[1] == ',')))
  44 --- /dev/null
  45 +++ b/gas/testsuite/gas/riscv/c-branch-na.d
  46 @@ -0,0 +1,20 @@
  47 +#as: -march=rv32ic
  48 +#source: c-branch.s
  49 +#objdump: -drw -Mno-aliases
  50 +
  51 +.*:[   ]+file format .*
  52 +
  53 +
  54 +Disassembly of section .text:
  55 +
  56 +0+ <target>:
  57 +[      ]+[0-9a-f]+:[   ]+c001[         ]+c\.beqz[      ]+s0,0 <target>[        ]+0: R_RISCV_RVC_BRANCH .*
  58 +[      ]+[0-9a-f]+:[   ]+dcfd[         ]+c\.beqz[      ]+s1,0 <target>[        ]+2: R_RISCV_RVC_BRANCH .*
  59 +[      ]+[0-9a-f]+:[   ]+fc75[         ]+c\.bnez[      ]+s0,0 <target>[        ]+4: R_RISCV_RVC_BRANCH .*
  60 +[      ]+[0-9a-f]+:[   ]+fced[         ]+c\.bnez[      ]+s1,0 <target>[        ]+6: R_RISCV_RVC_BRANCH .*
  61 +[      ]+[0-9a-f]+:[   ]+bfe5[         ]+c\.j[         ]+0 <target>[   ]+8: R_RISCV_RVC_JUMP   .*
  62 +[      ]+[0-9a-f]+:[   ]+3fdd[         ]+c\.jal[       ]+0 <target>[   ]+a: R_RISCV_RVC_JUMP   .*
  63 +[      ]+[0-9a-f]+:[   ]+9302[         ]+c\.jalr[      ]+t1
  64 +[      ]+[0-9a-f]+:[   ]+8382[         ]+c\.jr[        ]+t2
  65 +[      ]+[0-9a-f]+:[   ]+8082[         ]+c\.jr[        ]+ra
  66 +#...
  67 --- /dev/null
  68 +++ b/gas/testsuite/gas/riscv/c-branch.d
  69 @@ -0,0 +1,19 @@
  70 +#as: -march=rv64ic
  71 +#objdump: -drw
  72 +
  73 +.*:[   ]+file format .*
  74 +
  75 +
  76 +Disassembly of section .text:
  77 +
  78 +0+ <target>:
  79 +[      ]+[0-9a-f]+:[   ]+c001[         ]+beqz[         ]+s0,0 <target>[        ]+0: R_RISCV_RVC_BRANCH .*
  80 +[      ]+[0-9a-f]+:[   ]+dcfd[         ]+beqz[         ]+s1,0 <target>[        ]+2: R_RISCV_RVC_BRANCH .*
  81 +[      ]+[0-9a-f]+:[   ]+fc75[         ]+bnez[         ]+s0,0 <target>[        ]+4: R_RISCV_RVC_BRANCH .*
  82 +[      ]+[0-9a-f]+:[   ]+fced[         ]+bnez[         ]+s1,0 <target>[        ]+6: R_RISCV_RVC_BRANCH .*
  83 +[      ]+[0-9a-f]+:[   ]+bfe5[         ]+j[    ]+0 <target>[   ]+8: R_RISCV_RVC_JUMP   .*
  84 +[      ]+[0-9a-f]+:[   ]+ff7ff0ef[     ]+jal[  ]+0 <target>[   ]+a: R_RISCV_JAL        .*
  85 +[      ]+[0-9a-f]+:[   ]+9302[         ]+jalr[         ]+t1
  86 +[      ]+[0-9a-f]+:[   ]+8382[         ]+jr[   ]+t2
  87 +[      ]+[0-9a-f]+:[   ]+8082[         ]+ret
  88 +#...
  89 --- /dev/null
  90 +++ b/gas/testsuite/gas/riscv/c-branch.s
  91 @@ -0,0 +1,11 @@
  92 +       .text
  93 +target:
  94 +       beq     x8, x0, target
  95 +       beqz    x9, target
  96 +       bne     x8, x0, target
  97 +       bnez    x9, target
  98 +       j       target
  99 +       jal     target
 100 +       jalr    x6
 101 +       jr      x7
 102 +       ret
 103 --- a/opcodes/riscv-opc.c
 104 +++ b/opcodes/riscv-opc.c
 105 @@ -340,9 +340,9 @@ const struct riscv_opcode riscv_opcodes[
 106  {"jalr",        0, INSN_CLASS_I, "d,s,j",     MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR },
 107  {"j",           0, INSN_CLASS_C, "Ca",        MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH },
 108  {"j",           0, INSN_CLASS_I, "a",         MATCH_JAL, MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH },
 109 +{"jal",        32, INSN_CLASS_C, "Ca",        MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR },
 110  {"jal",         0, INSN_CLASS_I, "a",         MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
 111  {"jal",         0, INSN_CLASS_I, "d,a",       MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR },
 112 -{"jal",        32, INSN_CLASS_C, "Ca",        MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR },
 113  {"call",        0, INSN_CLASS_I, "d,c",       (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
 114  {"call",        0, INSN_CLASS_I, "c",         (X_RA << OP_SH_RS1)|(X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO },
 115  {"tail",        0, INSN_CLASS_I, "c",         (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },