mxs: drop 6.1 support
[openwrt/staging/nbd.git] / target / linux / sunxi / patches-6.1 / 009-v6.9-soc-sunxi-sram-export-register-0-for-THS-on-H616.patch
1 From 898d96c5464b69af44f6407c5de81ebc349d574b Mon Sep 17 00:00:00 2001
2 From: Andre Przywara <andre.przywara@arm.com>
3 Date: Mon, 19 Feb 2024 15:36:33 +0000
4 Subject: [PATCH] soc: sunxi: sram: export register 0 for THS on H616
5
6 The Allwinner H616 SoC contains a mysterious bit at register offset 0x0
7 in the SRAM control block. If bit 16 is set (the reset value), the
8 temperature readings of the THS are way off, leading to reports about
9 200C, at normal ambient temperatures. Clearing this bits brings the
10 reported values down to the expected values.
11 The BSP code clears this bit in firmware (U-Boot), and has an explicit
12 comment about this, but offers no real explanation.
13
14 Experiments in U-Boot show that register 0x0 has no effect on the SRAM C
15 visibility: all tested bit settings still allow full read and write
16 access by the CPU to the whole of SRAM C. Only bit 24 of the register at
17 offset 0x4 makes all of SRAM C inaccessible by the CPU. So modelling
18 the THS switch functionality as an SRAM region would not reflect reality.
19
20 Since we should not rely on firmware settings, allow other code (the THS
21 driver) to access this register, by exporting it through the already
22 existing regmap. This mimics what we already do for the LDO control and
23 the EMAC register.
24
25 To avoid concurrent accesses to the same register at the same time, by
26 the SRAM switch code and the regmap code, use the same lock to protect
27 the access. The regmap subsystem allows to use an existing lock, so we
28 just need to hook in there.
29
30 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
31 Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
32 Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
33 Link: https://lore.kernel.org/r/20240219153639.179814-2-andre.przywara@arm.com
34 ---
35 drivers/soc/sunxi/sunxi_sram.c | 22 ++++++++++++++++++++++
36 1 file changed, 22 insertions(+)
37
38 --- a/drivers/soc/sunxi/sunxi_sram.c
39 +++ b/drivers/soc/sunxi/sunxi_sram.c
40 @@ -284,6 +284,7 @@ EXPORT_SYMBOL(sunxi_sram_release);
41 struct sunxi_sramc_variant {
42 int num_emac_clocks;
43 bool has_ldo_ctrl;
44 + bool has_ths_offset;
45 };
46
47 static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
48 @@ -305,8 +306,10 @@ static const struct sunxi_sramc_variant
49
50 static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = {
51 .num_emac_clocks = 2,
52 + .has_ths_offset = true,
53 };
54
55 +#define SUNXI_SRAM_THS_OFFSET_REG 0x0
56 #define SUNXI_SRAM_EMAC_CLOCK_REG 0x30
57 #define SUNXI_SYS_LDO_CTRL_REG 0x150
58
59 @@ -315,6 +318,8 @@ static bool sunxi_sram_regmap_accessible
60 {
61 const struct sunxi_sramc_variant *variant = dev_get_drvdata(dev);
62
63 + if (reg == SUNXI_SRAM_THS_OFFSET_REG && variant->has_ths_offset)
64 + return true;
65 if (reg >= SUNXI_SRAM_EMAC_CLOCK_REG &&
66 reg < SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4)
67 return true;
68 @@ -324,6 +329,20 @@ static bool sunxi_sram_regmap_accessible
69 return false;
70 }
71
72 +static void sunxi_sram_lock(void *_lock)
73 +{
74 + spinlock_t *lock = _lock;
75 +
76 + spin_lock(lock);
77 +}
78 +
79 +static void sunxi_sram_unlock(void *_lock)
80 +{
81 + spinlock_t *lock = _lock;
82 +
83 + spin_unlock(lock);
84 +}
85 +
86 static struct regmap_config sunxi_sram_regmap_config = {
87 .reg_bits = 32,
88 .val_bits = 32,
89 @@ -333,6 +352,9 @@ static struct regmap_config sunxi_sram_r
90 /* other devices have no business accessing other registers */
91 .readable_reg = sunxi_sram_regmap_accessible_reg,
92 .writeable_reg = sunxi_sram_regmap_accessible_reg,
93 + .lock = sunxi_sram_lock,
94 + .unlock = sunxi_sram_unlock,
95 + .lock_arg = &sram_lock,
96 };
97
98 static int __init sunxi_sram_probe(struct platform_device *pdev)