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mac80211: update to version 5.9.1
[openwrt/staging/nbd.git] / target / linux / realtek / files-5.15 / drivers / net / ethernet / rtl838x_eth.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/net/ethernet/rtl838x_eth.c
3 * Copyright (C) 2020 B. Koblitz
4 */
5
6 #include <linux/dma-mapping.h>
7 #include <linux/etherdevice.h>
8 #include <linux/interrupt.h>
9 #include <linux/io.h>
10 #include <linux/platform_device.h>
11 #include <linux/sched.h>
12 #include <linux/slab.h>
13 #include <linux/of.h>
14 #include <linux/of_net.h>
15 #include <linux/of_mdio.h>
16 #include <linux/module.h>
17 #include <linux/phylink.h>
18 #include <linux/pkt_sched.h>
19 #include <net/dsa.h>
20 #include <net/switchdev.h>
21 #include <asm/cacheflush.h>
22
23 #include <asm/mach-rtl838x/mach-rtl83xx.h>
24 #include "rtl838x_eth.h"
25
26 extern struct rtl83xx_soc_info soc_info;
27
28 /* Maximum number of RX rings is 8 on RTL83XX and 32 on the 93XX
29 * The ring is assigned by switch based on packet/port priortity
30 * Maximum number of TX rings is 2, Ring 2 being the high priority
31 * ring on the RTL93xx SoCs. MAX_RXLEN gives the maximum length
32 * for an RX ring, MAX_ENTRIES the maximum number of entries
33 * available in total for all queues.
34 */
35 #define MAX_RXRINGS 32
36 #define MAX_RXLEN 300
37 #define MAX_ENTRIES (300 * 8)
38 #define TXRINGS 2
39 #define TXRINGLEN 160
40 #define NOTIFY_EVENTS 10
41 #define NOTIFY_BLOCKS 10
42 #define TX_EN 0x8
43 #define RX_EN 0x4
44 #define TX_EN_93XX 0x20
45 #define RX_EN_93XX 0x10
46 #define RX_TRUNCATE_EN_93XX BIT(6)
47 #define RX_TRUNCATE_EN_83XX BIT(4)
48 #define TX_PAD_EN_838X BIT(5)
49 #define TX_DO 0x2
50 #define WRAP 0x2
51 #define MAX_PORTS 57
52 #define MAX_SMI_BUSSES 4
53
54 #define RING_BUFFER 1600
55
56 struct p_hdr {
57 uint8_t *buf;
58 uint16_t reserved;
59 uint16_t size; /* buffer size */
60 uint16_t offset;
61 uint16_t len; /* pkt len */
62 /* cpu_tag[0] is a reserved uint16_t on RTL83xx */
63 uint16_t cpu_tag[10];
64 } __packed __aligned(1);
65
66 struct n_event {
67 uint32_t type:2;
68 uint32_t fidVid:12;
69 uint64_t mac:48;
70 uint32_t slp:6;
71 uint32_t valid:1;
72 uint32_t reserved:27;
73 } __packed __aligned(1);
74
75 struct ring_b {
76 uint32_t rx_r[MAX_RXRINGS][MAX_RXLEN];
77 uint32_t tx_r[TXRINGS][TXRINGLEN];
78 struct p_hdr rx_header[MAX_RXRINGS][MAX_RXLEN];
79 struct p_hdr tx_header[TXRINGS][TXRINGLEN];
80 uint32_t c_rx[MAX_RXRINGS];
81 uint32_t c_tx[TXRINGS];
82 uint8_t tx_space[TXRINGS * TXRINGLEN * RING_BUFFER];
83 uint8_t *rx_space;
84 };
85
86 struct notify_block {
87 struct n_event events[NOTIFY_EVENTS];
88 };
89
90 struct notify_b {
91 struct notify_block blocks[NOTIFY_BLOCKS];
92 u32 reserved1[8];
93 u32 ring[NOTIFY_BLOCKS];
94 u32 reserved2[8];
95 };
96
97 static void rtl838x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio)
98 {
99 /* cpu_tag[0] is reserved on the RTL83XX SoCs */
100 h->cpu_tag[1] = 0x0400; /* BIT 10: RTL8380_CPU_TAG */
101 h->cpu_tag[2] = 0x0200; /* Set only AS_DPM, to enable DPM settings below */
102 h->cpu_tag[3] = 0x0000;
103 h->cpu_tag[4] = BIT(dest_port) >> 16;
104 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
105
106 /* Set internal priority (PRI) and enable (AS_PRI) */
107 if (prio >= 0)
108 h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 12;
109 }
110
111 static void rtl839x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio)
112 {
113 /* cpu_tag[0] is reserved on the RTL83XX SoCs */
114 h->cpu_tag[1] = 0x0100; /* RTL8390_CPU_TAG marker */
115 h->cpu_tag[2] = BIT(4); /* AS_DPM flag */
116 h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0;
117 /* h->cpu_tag[1] |= BIT(1) | BIT(0); */ /* Bypass filter 1/2 */
118 if (dest_port >= 32) {
119 dest_port -= 32;
120 h->cpu_tag[2] |= (BIT(dest_port) >> 16) & 0xf;
121 h->cpu_tag[3] = BIT(dest_port) & 0xffff;
122 } else {
123 h->cpu_tag[4] = BIT(dest_port) >> 16;
124 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
125 }
126
127 /* Set internal priority (PRI) and enable (AS_PRI) */
128 if (prio >= 0)
129 h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 8;
130 }
131
132 static void rtl930x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio)
133 {
134 h->cpu_tag[0] = 0x8000; /* CPU tag marker */
135 h->cpu_tag[1] = h->cpu_tag[2] = 0;
136 h->cpu_tag[3] = 0;
137 h->cpu_tag[4] = 0;
138 h->cpu_tag[5] = 0;
139 h->cpu_tag[6] = BIT(dest_port) >> 16;
140 h->cpu_tag[7] = BIT(dest_port) & 0xffff;
141
142 /* Enable (AS_QID) and set priority queue (QID) */
143 if (prio >= 0)
144 h->cpu_tag[2] = (BIT(5) | (prio & 0x1f)) << 8;
145 }
146
147 static void rtl931x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio)
148 {
149 h->cpu_tag[0] = 0x8000; /* CPU tag marker */
150 h->cpu_tag[1] = h->cpu_tag[2] = 0;
151 h->cpu_tag[3] = 0;
152 h->cpu_tag[4] = h->cpu_tag[5] = h->cpu_tag[6] = h->cpu_tag[7] = 0;
153 if (dest_port >= 32) {
154 dest_port -= 32;
155 h->cpu_tag[4] = BIT(dest_port) >> 16;
156 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
157 } else {
158 h->cpu_tag[6] = BIT(dest_port) >> 16;
159 h->cpu_tag[7] = BIT(dest_port) & 0xffff;
160 }
161
162 /* Enable (AS_QID) and set priority queue (QID) */
163 if (prio >= 0)
164 h->cpu_tag[2] = (BIT(5) | (prio & 0x1f)) << 8;
165 }
166
167 // Currently unused
168 // static void rtl93xx_header_vlan_set(struct p_hdr *h, int vlan)
169 // {
170 // h->cpu_tag[2] |= BIT(4); /* Enable VLAN forwarding offload */
171 // h->cpu_tag[2] |= (vlan >> 8) & 0xf;
172 // h->cpu_tag[3] |= (vlan & 0xff) << 8;
173 // }
174
175 struct rtl838x_rx_q {
176 int id;
177 struct rtl838x_eth_priv *priv;
178 struct napi_struct napi;
179 };
180
181 struct rtl838x_eth_priv {
182 struct net_device *netdev;
183 struct platform_device *pdev;
184 void *membase;
185 spinlock_t lock;
186 struct mii_bus *mii_bus;
187 struct rtl838x_rx_q rx_qs[MAX_RXRINGS];
188 struct phylink *phylink;
189 struct phylink_config phylink_config;
190 u16 id;
191 u16 family_id;
192 const struct rtl838x_eth_reg *r;
193 u8 cpu_port;
194 u32 lastEvent;
195 u16 rxrings;
196 u16 rxringlen;
197 u8 smi_bus[MAX_PORTS];
198 u8 smi_addr[MAX_PORTS];
199 u32 sds_id[MAX_PORTS];
200 bool smi_bus_isc45[MAX_SMI_BUSSES];
201 bool phy_is_internal[MAX_PORTS];
202 phy_interface_t interfaces[MAX_PORTS];
203 };
204
205 extern int rtl838x_phy_init(struct rtl838x_eth_priv *priv);
206 extern int rtl838x_read_sds_phy(int phy_addr, int phy_reg);
207 extern int rtl839x_read_sds_phy(int phy_addr, int phy_reg);
208 extern int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v);
209 extern int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg);
210 extern int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
211 extern int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg);
212 extern int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
213 extern int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
214 extern int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
215 extern int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
216 extern int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
217
218 /* On the RTL93XX, the RTL93XX_DMA_IF_RX_RING_CNTR track the fill level of
219 * the rings. Writing x into these registers substracts x from its content.
220 * When the content reaches the ring size, the ASIC no longer adds
221 * packets to this receive queue.
222 */
223 void rtl838x_update_cntr(int r, int released)
224 {
225 /* This feature is not available on RTL838x SoCs */
226 }
227
228 void rtl839x_update_cntr(int r, int released)
229 {
230 /* This feature is not available on RTL839x SoCs */
231 }
232
233 void rtl930x_update_cntr(int r, int released)
234 {
235 int pos = (r % 3) * 10;
236 u32 reg = RTL930X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
237 u32 v = sw_r32(reg);
238
239 v = (v >> pos) & 0x3ff;
240 pr_debug("RX: Work done %d, old value: %d, pos %d, reg %04x\n", released, v, pos, reg);
241 sw_w32_mask(0x3ff << pos, released << pos, reg);
242 sw_w32(v, reg);
243 }
244
245 void rtl931x_update_cntr(int r, int released)
246 {
247 int pos = (r % 3) * 10;
248 u32 reg = RTL931X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
249 u32 v = sw_r32(reg);
250
251 v = (v >> pos) & 0x3ff;
252 sw_w32_mask(0x3ff << pos, released << pos, reg);
253 sw_w32(v, reg);
254 }
255
256 struct dsa_tag {
257 u8 reason;
258 u8 queue;
259 u16 port;
260 u8 l2_offloaded;
261 u8 prio;
262 bool crc_error;
263 };
264
265 bool rtl838x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
266 {
267 /* cpu_tag[0] is reserved. Fields are off-by-one */
268 t->reason = h->cpu_tag[4] & 0xf;
269 t->queue = (h->cpu_tag[1] & 0xe0) >> 5;
270 t->port = h->cpu_tag[1] & 0x1f;
271 t->crc_error = t->reason == 13;
272
273 pr_debug("Reason: %d\n", t->reason);
274 if (t->reason != 6) /* NIC_RX_REASON_SPECIAL_TRAP */
275 t->l2_offloaded = 1;
276 else
277 t->l2_offloaded = 0;
278
279 return t->l2_offloaded;
280 }
281
282 bool rtl839x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
283 {
284 /* cpu_tag[0] is reserved. Fields are off-by-one */
285 t->reason = h->cpu_tag[5] & 0x1f;
286 t->queue = (h->cpu_tag[4] & 0xe000) >> 13;
287 t->port = h->cpu_tag[1] & 0x3f;
288 t->crc_error = h->cpu_tag[4] & BIT(6);
289
290 pr_debug("Reason: %d\n", t->reason);
291 if ((t->reason >= 7 && t->reason <= 13) || /* NIC_RX_REASON_RMA */
292 (t->reason >= 23 && t->reason <= 25)) /* NIC_RX_REASON_SPECIAL_TRAP */
293 t->l2_offloaded = 0;
294 else
295 t->l2_offloaded = 1;
296
297 return t->l2_offloaded;
298 }
299
300 bool rtl930x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
301 {
302 t->reason = h->cpu_tag[7] & 0x3f;
303 t->queue = (h->cpu_tag[2] >> 11) & 0x1f;
304 t->port = (h->cpu_tag[0] >> 8) & 0x1f;
305 t->crc_error = h->cpu_tag[1] & BIT(6);
306
307 pr_debug("Reason %d, port %d, queue %d\n", t->reason, t->port, t->queue);
308 if (t->reason >= 19 && t->reason <= 27)
309 t->l2_offloaded = 0;
310 else
311 t->l2_offloaded = 1;
312
313 return t->l2_offloaded;
314 }
315
316 bool rtl931x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
317 {
318 t->reason = h->cpu_tag[7] & 0x3f;
319 t->queue = (h->cpu_tag[2] >> 11) & 0x1f;
320 t->port = (h->cpu_tag[0] >> 8) & 0x3f;
321 t->crc_error = h->cpu_tag[1] & BIT(6);
322
323 if (t->reason != 63)
324 pr_info("%s: Reason %d, port %d, queue %d\n", __func__, t->reason, t->port, t->queue);
325 if (t->reason >= 19 && t->reason <= 27) /* NIC_RX_REASON_RMA */
326 t->l2_offloaded = 0;
327 else
328 t->l2_offloaded = 1;
329
330 return t->l2_offloaded;
331 }
332
333 /* Discard the RX ring-buffers, called as part of the net-ISR
334 * when the buffer runs over
335 */
336 static void rtl838x_rb_cleanup(struct rtl838x_eth_priv *priv, int status)
337 {
338 for (int r = 0; r < priv->rxrings; r++) {
339 struct ring_b *ring = priv->membase;
340 struct p_hdr *h;
341 u32 *last;
342
343 pr_debug("In %s working on r: %d\n", __func__, r);
344 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
345 do {
346 if ((ring->rx_r[r][ring->c_rx[r]] & 0x1))
347 break;
348 pr_debug("Got something: %d\n", ring->c_rx[r]);
349 h = &ring->rx_header[r][ring->c_rx[r]];
350 memset(h, 0, sizeof(struct p_hdr));
351 h->buf = (u8 *)KSEG1ADDR(ring->rx_space +
352 r * priv->rxringlen * RING_BUFFER +
353 ring->c_rx[r] * RING_BUFFER);
354 h->size = RING_BUFFER;
355 /* make sure the header is visible to the ASIC */
356 mb();
357
358 ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1 | (ring->c_rx[r] == (priv->rxringlen - 1) ?
359 WRAP :
360 0x1);
361 ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;
362 } while (&ring->rx_r[r][ring->c_rx[r]] != last);
363 }
364 }
365
366 struct fdb_update_work {
367 struct work_struct work;
368 struct net_device *ndev;
369 u64 macs[NOTIFY_EVENTS + 1];
370 };
371
372 void rtl838x_fdb_sync(struct work_struct *work)
373 {
374 const struct fdb_update_work *uw = container_of(work, struct fdb_update_work, work);
375
376 for (int i = 0; uw->macs[i]; i++) {
377 struct switchdev_notifier_fdb_info info;
378 u8 addr[ETH_ALEN];
379 int action;
380
381 action = (uw->macs[i] & (1ULL << 63)) ?
382 SWITCHDEV_FDB_ADD_TO_BRIDGE :
383 SWITCHDEV_FDB_DEL_TO_BRIDGE;
384 u64_to_ether_addr(uw->macs[i] & 0xffffffffffffULL, addr);
385 info.addr = &addr[0];
386 info.vid = 0;
387 info.offloaded = 1;
388 pr_debug("FDB entry %d: %llx, action %d\n", i, uw->macs[0], action);
389 call_switchdev_notifiers(action, uw->ndev, &info.info, NULL);
390 }
391 kfree(work);
392 }
393
394 static void rtl839x_l2_notification_handler(struct rtl838x_eth_priv *priv)
395 {
396 struct notify_b *nb = priv->membase + sizeof(struct ring_b);
397 u32 e = priv->lastEvent;
398
399 while (!(nb->ring[e] & 1)) {
400 struct fdb_update_work *w;
401 struct n_event *event;
402 u64 mac;
403 int i;
404
405 w = kzalloc(sizeof(*w), GFP_ATOMIC);
406 if (!w) {
407 pr_err("Out of memory: %s", __func__);
408 return;
409 }
410 INIT_WORK(&w->work, rtl838x_fdb_sync);
411
412 for (i = 0; i < NOTIFY_EVENTS; i++) {
413 event = &nb->blocks[e].events[i];
414 if (!event->valid)
415 continue;
416 mac = event->mac;
417 if (event->type)
418 mac |= 1ULL << 63;
419 w->ndev = priv->netdev;
420 w->macs[i] = mac;
421 }
422
423 /* Hand the ring entry back to the switch */
424 nb->ring[e] = nb->ring[e] | 1;
425 e = (e + 1) % NOTIFY_BLOCKS;
426
427 w->macs[i] = 0ULL;
428 schedule_work(&w->work);
429 }
430 priv->lastEvent = e;
431 }
432
433 static irqreturn_t rtl83xx_net_irq(int irq, void *dev_id)
434 {
435 struct net_device *dev = dev_id;
436 struct rtl838x_eth_priv *priv = netdev_priv(dev);
437 u32 status = sw_r32(priv->r->dma_if_intr_sts);
438
439 pr_debug("IRQ: %08x\n", status);
440
441 /* Ignore TX interrupt */
442 if ((status & 0xf0000)) {
443 /* Clear ISR */
444 sw_w32(0x000f0000, priv->r->dma_if_intr_sts);
445 }
446
447 /* RX interrupt */
448 if (status & 0x0ff00) {
449 /* ACK and disable RX interrupt for this ring */
450 sw_w32_mask(0xff00 & status, 0, priv->r->dma_if_intr_msk);
451 sw_w32(0x0000ff00 & status, priv->r->dma_if_intr_sts);
452 for (int i = 0; i < priv->rxrings; i++) {
453 if (status & BIT(i + 8)) {
454 pr_debug("Scheduling queue: %d\n", i);
455 napi_schedule(&priv->rx_qs[i].napi);
456 }
457 }
458 }
459
460 /* RX buffer overrun */
461 if (status & 0x000ff) {
462 pr_debug("RX buffer overrun: status %x, mask: %x\n",
463 status, sw_r32(priv->r->dma_if_intr_msk));
464 sw_w32(status, priv->r->dma_if_intr_sts);
465 rtl838x_rb_cleanup(priv, status & 0xff);
466 }
467
468 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00100000) {
469 sw_w32(0x00100000, priv->r->dma_if_intr_sts);
470 rtl839x_l2_notification_handler(priv);
471 }
472
473 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00200000) {
474 sw_w32(0x00200000, priv->r->dma_if_intr_sts);
475 rtl839x_l2_notification_handler(priv);
476 }
477
478 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00400000) {
479 sw_w32(0x00400000, priv->r->dma_if_intr_sts);
480 rtl839x_l2_notification_handler(priv);
481 }
482
483 return IRQ_HANDLED;
484 }
485
486 static irqreturn_t rtl93xx_net_irq(int irq, void *dev_id)
487 {
488 struct net_device *dev = dev_id;
489 struct rtl838x_eth_priv *priv = netdev_priv(dev);
490 u32 status_rx_r = sw_r32(priv->r->dma_if_intr_rx_runout_sts);
491 u32 status_rx = sw_r32(priv->r->dma_if_intr_rx_done_sts);
492 u32 status_tx = sw_r32(priv->r->dma_if_intr_tx_done_sts);
493
494 pr_debug("In %s, status_tx: %08x, status_rx: %08x, status_rx_r: %08x\n",
495 __func__, status_tx, status_rx, status_rx_r);
496
497 /* Ignore TX interrupt */
498 if (status_tx) {
499 /* Clear ISR */
500 pr_debug("TX done\n");
501 sw_w32(status_tx, priv->r->dma_if_intr_tx_done_sts);
502 }
503
504 /* RX interrupt */
505 if (status_rx) {
506 pr_debug("RX IRQ\n");
507 /* ACK and disable RX interrupt for given rings */
508 sw_w32(status_rx, priv->r->dma_if_intr_rx_done_sts);
509 sw_w32_mask(status_rx, 0, priv->r->dma_if_intr_rx_done_msk);
510 for (int i = 0; i < priv->rxrings; i++) {
511 if (status_rx & BIT(i)) {
512 pr_debug("Scheduling queue: %d\n", i);
513 napi_schedule(&priv->rx_qs[i].napi);
514 }
515 }
516 }
517
518 /* RX buffer overrun */
519 if (status_rx_r) {
520 pr_debug("RX buffer overrun: status %x, mask: %x\n",
521 status_rx_r, sw_r32(priv->r->dma_if_intr_rx_runout_msk));
522 sw_w32(status_rx_r, priv->r->dma_if_intr_rx_runout_sts);
523 rtl838x_rb_cleanup(priv, status_rx_r);
524 }
525
526 return IRQ_HANDLED;
527 }
528
529 static const struct rtl838x_eth_reg rtl838x_reg = {
530 .net_irq = rtl83xx_net_irq,
531 .mac_port_ctrl = rtl838x_mac_port_ctrl,
532 .dma_if_intr_sts = RTL838X_DMA_IF_INTR_STS,
533 .dma_if_intr_msk = RTL838X_DMA_IF_INTR_MSK,
534 .dma_if_ctrl = RTL838X_DMA_IF_CTRL,
535 .mac_force_mode_ctrl = RTL838X_MAC_FORCE_MODE_CTRL,
536 .dma_rx_base = RTL838X_DMA_RX_BASE,
537 .dma_tx_base = RTL838X_DMA_TX_BASE,
538 .dma_if_rx_ring_size = rtl838x_dma_if_rx_ring_size,
539 .dma_if_rx_ring_cntr = rtl838x_dma_if_rx_ring_cntr,
540 .dma_if_rx_cur = RTL838X_DMA_IF_RX_CUR,
541 .rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0,
542 .get_mac_link_sts = rtl838x_get_mac_link_sts,
543 .get_mac_link_dup_sts = rtl838x_get_mac_link_dup_sts,
544 .get_mac_link_spd_sts = rtl838x_get_mac_link_spd_sts,
545 .get_mac_rx_pause_sts = rtl838x_get_mac_rx_pause_sts,
546 .get_mac_tx_pause_sts = rtl838x_get_mac_tx_pause_sts,
547 .mac = RTL838X_MAC,
548 .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
549 .update_cntr = rtl838x_update_cntr,
550 .create_tx_header = rtl838x_create_tx_header,
551 .decode_tag = rtl838x_decode_tag,
552 };
553
554 static const struct rtl838x_eth_reg rtl839x_reg = {
555 .net_irq = rtl83xx_net_irq,
556 .mac_port_ctrl = rtl839x_mac_port_ctrl,
557 .dma_if_intr_sts = RTL839X_DMA_IF_INTR_STS,
558 .dma_if_intr_msk = RTL839X_DMA_IF_INTR_MSK,
559 .dma_if_ctrl = RTL839X_DMA_IF_CTRL,
560 .mac_force_mode_ctrl = RTL839X_MAC_FORCE_MODE_CTRL,
561 .dma_rx_base = RTL839X_DMA_RX_BASE,
562 .dma_tx_base = RTL839X_DMA_TX_BASE,
563 .dma_if_rx_ring_size = rtl839x_dma_if_rx_ring_size,
564 .dma_if_rx_ring_cntr = rtl839x_dma_if_rx_ring_cntr,
565 .dma_if_rx_cur = RTL839X_DMA_IF_RX_CUR,
566 .rst_glb_ctrl = RTL839X_RST_GLB_CTRL,
567 .get_mac_link_sts = rtl839x_get_mac_link_sts,
568 .get_mac_link_dup_sts = rtl839x_get_mac_link_dup_sts,
569 .get_mac_link_spd_sts = rtl839x_get_mac_link_spd_sts,
570 .get_mac_rx_pause_sts = rtl839x_get_mac_rx_pause_sts,
571 .get_mac_tx_pause_sts = rtl839x_get_mac_tx_pause_sts,
572 .mac = RTL839X_MAC,
573 .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
574 .update_cntr = rtl839x_update_cntr,
575 .create_tx_header = rtl839x_create_tx_header,
576 .decode_tag = rtl839x_decode_tag,
577 };
578
579 static const struct rtl838x_eth_reg rtl930x_reg = {
580 .net_irq = rtl93xx_net_irq,
581 .mac_port_ctrl = rtl930x_mac_port_ctrl,
582 .dma_if_intr_rx_runout_sts = RTL930X_DMA_IF_INTR_RX_RUNOUT_STS,
583 .dma_if_intr_rx_done_sts = RTL930X_DMA_IF_INTR_RX_DONE_STS,
584 .dma_if_intr_tx_done_sts = RTL930X_DMA_IF_INTR_TX_DONE_STS,
585 .dma_if_intr_rx_runout_msk = RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK,
586 .dma_if_intr_rx_done_msk = RTL930X_DMA_IF_INTR_RX_DONE_MSK,
587 .dma_if_intr_tx_done_msk = RTL930X_DMA_IF_INTR_TX_DONE_MSK,
588 .l2_ntfy_if_intr_sts = RTL930X_L2_NTFY_IF_INTR_STS,
589 .l2_ntfy_if_intr_msk = RTL930X_L2_NTFY_IF_INTR_MSK,
590 .dma_if_ctrl = RTL930X_DMA_IF_CTRL,
591 .mac_force_mode_ctrl = RTL930X_MAC_FORCE_MODE_CTRL,
592 .dma_rx_base = RTL930X_DMA_RX_BASE,
593 .dma_tx_base = RTL930X_DMA_TX_BASE,
594 .dma_if_rx_ring_size = rtl930x_dma_if_rx_ring_size,
595 .dma_if_rx_ring_cntr = rtl930x_dma_if_rx_ring_cntr,
596 .dma_if_rx_cur = RTL930X_DMA_IF_RX_CUR,
597 .rst_glb_ctrl = RTL930X_RST_GLB_CTRL_0,
598 .get_mac_link_sts = rtl930x_get_mac_link_sts,
599 .get_mac_link_dup_sts = rtl930x_get_mac_link_dup_sts,
600 .get_mac_link_spd_sts = rtl930x_get_mac_link_spd_sts,
601 .get_mac_rx_pause_sts = rtl930x_get_mac_rx_pause_sts,
602 .get_mac_tx_pause_sts = rtl930x_get_mac_tx_pause_sts,
603 .mac = RTL930X_MAC_L2_ADDR_CTRL,
604 .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
605 .update_cntr = rtl930x_update_cntr,
606 .create_tx_header = rtl930x_create_tx_header,
607 .decode_tag = rtl930x_decode_tag,
608 };
609
610 static const struct rtl838x_eth_reg rtl931x_reg = {
611 .net_irq = rtl93xx_net_irq,
612 .mac_port_ctrl = rtl931x_mac_port_ctrl,
613 .dma_if_intr_rx_runout_sts = RTL931X_DMA_IF_INTR_RX_RUNOUT_STS,
614 .dma_if_intr_rx_done_sts = RTL931X_DMA_IF_INTR_RX_DONE_STS,
615 .dma_if_intr_tx_done_sts = RTL931X_DMA_IF_INTR_TX_DONE_STS,
616 .dma_if_intr_rx_runout_msk = RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK,
617 .dma_if_intr_rx_done_msk = RTL931X_DMA_IF_INTR_RX_DONE_MSK,
618 .dma_if_intr_tx_done_msk = RTL931X_DMA_IF_INTR_TX_DONE_MSK,
619 .l2_ntfy_if_intr_sts = RTL931X_L2_NTFY_IF_INTR_STS,
620 .l2_ntfy_if_intr_msk = RTL931X_L2_NTFY_IF_INTR_MSK,
621 .dma_if_ctrl = RTL931X_DMA_IF_CTRL,
622 .mac_force_mode_ctrl = RTL931X_MAC_FORCE_MODE_CTRL,
623 .dma_rx_base = RTL931X_DMA_RX_BASE,
624 .dma_tx_base = RTL931X_DMA_TX_BASE,
625 .dma_if_rx_ring_size = rtl931x_dma_if_rx_ring_size,
626 .dma_if_rx_ring_cntr = rtl931x_dma_if_rx_ring_cntr,
627 .dma_if_rx_cur = RTL931X_DMA_IF_RX_CUR,
628 .rst_glb_ctrl = RTL931X_RST_GLB_CTRL,
629 .get_mac_link_sts = rtl931x_get_mac_link_sts,
630 .get_mac_link_dup_sts = rtl931x_get_mac_link_dup_sts,
631 .get_mac_link_spd_sts = rtl931x_get_mac_link_spd_sts,
632 .get_mac_rx_pause_sts = rtl931x_get_mac_rx_pause_sts,
633 .get_mac_tx_pause_sts = rtl931x_get_mac_tx_pause_sts,
634 .mac = RTL931X_MAC_L2_ADDR_CTRL,
635 .l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,
636 .update_cntr = rtl931x_update_cntr,
637 .create_tx_header = rtl931x_create_tx_header,
638 .decode_tag = rtl931x_decode_tag,
639 };
640
641 static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)
642 {
643 u32 int_saved, nbuf;
644 u32 reset_mask;
645
646 pr_info("RESETTING %x, CPU_PORT %d\n", priv->family_id, priv->cpu_port);
647 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
648 mdelay(100);
649
650 /* Disable and clear interrupts */
651 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
652 sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
653 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
654 sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
655 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);
656 sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);
657 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);
658 } else {
659 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
660 sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
661 }
662
663 if (priv->family_id == RTL8390_FAMILY_ID) {
664 /* Preserve L2 notification and NBUF settings */
665 int_saved = sw_r32(priv->r->dma_if_intr_msk);
666 nbuf = sw_r32(RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
667
668 /* Disable link change interrupt on RTL839x */
669 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG);
670 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
671
672 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
673 sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
674 }
675
676 /* Reset NIC (SW_NIC_RST) and queues (SW_Q_RST) */
677 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
678 reset_mask = 0x6;
679 else
680 reset_mask = 0xc;
681
682 sw_w32_mask(0, reset_mask, priv->r->rst_glb_ctrl);
683
684 do { /* Wait for reset of NIC and Queues done */
685 udelay(20);
686 } while (sw_r32(priv->r->rst_glb_ctrl) & reset_mask);
687 mdelay(100);
688
689 /* Setup Head of Line */
690 if (priv->family_id == RTL8380_FAMILY_ID)
691 sw_w32(0, RTL838X_DMA_IF_RX_RING_SIZE); /* Disabled on RTL8380 */
692 if (priv->family_id == RTL8390_FAMILY_ID)
693 sw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR);
694 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
695 for (int i = 0; i < priv->rxrings; i++) {
696 int pos = (i % 3) * 10;
697
698 sw_w32_mask(0x3ff << pos, 0, priv->r->dma_if_rx_ring_size(i));
699 sw_w32_mask(0x3ff << pos, priv->rxringlen,
700 priv->r->dma_if_rx_ring_cntr(i));
701 }
702 }
703
704 /* Re-enable link change interrupt */
705 if (priv->family_id == RTL8390_FAMILY_ID) {
706 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG);
707 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG + 4);
708 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG);
709 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
710
711 /* Restore notification settings: on RTL838x these bits are null */
712 sw_w32_mask(7 << 20, int_saved & (7 << 20), priv->r->dma_if_intr_msk);
713 sw_w32(nbuf, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
714 }
715 }
716
717 static void rtl838x_hw_ring_setup(struct rtl838x_eth_priv *priv)
718 {
719 struct ring_b *ring = priv->membase;
720
721 for (int i = 0; i < priv->rxrings; i++)
722 sw_w32(KSEG1ADDR(&ring->rx_r[i]), priv->r->dma_rx_base + i * 4);
723
724 for (int i = 0; i < TXRINGS; i++)
725 sw_w32(KSEG1ADDR(&ring->tx_r[i]), priv->r->dma_tx_base + i * 4);
726 }
727
728 static void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
729 {
730 /* Disable Head of Line features for all RX rings */
731 sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
732
733 /* Truncate RX buffer to DEFAULT_MTU bytes, pad TX */
734 sw_w32((DEFAULT_MTU << 16) | RX_TRUNCATE_EN_83XX | TX_PAD_EN_838X, priv->r->dma_if_ctrl);
735
736 /* Enable RX done, RX overflow and TX done interrupts */
737 sw_w32(0xfffff, priv->r->dma_if_intr_msk);
738
739 /* Enable DMA, engine expects empty FCS field */
740 sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
741
742 /* Restart TX/RX to CPU port */
743 sw_w32_mask(0x0, 0x3, priv->r->mac_port_ctrl(priv->cpu_port));
744 /* Set Speed, duplex, flow control
745 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
746 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
747 * | MEDIA_SEL
748 */
749 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
750
751 /* Enable CRC checks on CPU-port */
752 sw_w32_mask(0, BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
753 }
754
755 static void rtl839x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
756 {
757 /* Setup CPU-Port: RX Buffer */
758 sw_w32((DEFAULT_MTU << 5) | RX_TRUNCATE_EN_83XX, priv->r->dma_if_ctrl);
759
760 /* Enable Notify, RX done, RX overflow and TX done interrupts */
761 sw_w32(0x007fffff, priv->r->dma_if_intr_msk); /* Notify IRQ! */
762
763 /* Enable DMA */
764 sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
765
766 /* Restart TX/RX to CPU port, enable CRC checking */
767 sw_w32_mask(0x0, 0x3 | BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
768
769 /* CPU port joins Lookup Miss Flooding Portmask */
770 /* TODO: The code below should also work for the RTL838x */
771 sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL);
772 sw_w32_mask(0, 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0));
773 sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL);
774
775 /* Force CPU port link up */
776 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
777 }
778
779 static void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv *priv)
780 {
781 /* Setup CPU-Port: RX Buffer truncated at DEFAULT_MTU Bytes */
782 sw_w32((DEFAULT_MTU << 16) | RX_TRUNCATE_EN_93XX, priv->r->dma_if_ctrl);
783
784 for (int i = 0; i < priv->rxrings; i++) {
785 int pos = (i % 3) * 10;
786 u32 v;
787
788 sw_w32_mask(0x3ff << pos, priv->rxringlen << pos, priv->r->dma_if_rx_ring_size(i));
789
790 /* Some SoCs have issues with missing underflow protection */
791 v = (sw_r32(priv->r->dma_if_rx_ring_cntr(i)) >> pos) & 0x3ff;
792 sw_w32_mask(0x3ff << pos, v, priv->r->dma_if_rx_ring_cntr(i));
793 }
794
795 /* Enable Notify, RX done, RX overflow and TX done interrupts */
796 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_msk);
797 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);
798 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_msk);
799
800 /* Enable DMA */
801 sw_w32_mask(0, RX_EN_93XX | TX_EN_93XX, priv->r->dma_if_ctrl);
802
803 /* Restart TX/RX to CPU port, enable CRC checking */
804 sw_w32_mask(0x0, 0x3 | BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
805
806 if (priv->family_id == RTL9300_FAMILY_ID)
807 sw_w32_mask(0, BIT(priv->cpu_port), RTL930X_L2_UNKN_UC_FLD_PMSK);
808 else
809 sw_w32_mask(0, BIT(priv->cpu_port), RTL931X_L2_UNKN_UC_FLD_PMSK);
810
811 if (priv->family_id == RTL9300_FAMILY_ID)
812 sw_w32(0x217, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
813 else
814 sw_w32(0x2a1d, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
815 }
816
817 static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv *priv, struct ring_b *ring)
818 {
819 for (int i = 0; i < priv->rxrings; i++) {
820 struct p_hdr *h;
821 int j;
822
823 for (j = 0; j < priv->rxringlen; j++) {
824 h = &ring->rx_header[i][j];
825 memset(h, 0, sizeof(struct p_hdr));
826 h->buf = (u8 *)KSEG1ADDR(ring->rx_space +
827 i * priv->rxringlen * RING_BUFFER +
828 j * RING_BUFFER);
829 h->size = RING_BUFFER;
830 /* All rings owned by switch, last one wraps */
831 ring->rx_r[i][j] = KSEG1ADDR(h) | 1 | (j == (priv->rxringlen - 1) ?
832 WRAP :
833 0);
834 }
835 ring->c_rx[i] = 0;
836 }
837
838 for (int i = 0; i < TXRINGS; i++) {
839 struct p_hdr *h;
840 int j;
841
842 for (j = 0; j < TXRINGLEN; j++) {
843 h = &ring->tx_header[i][j];
844 memset(h, 0, sizeof(struct p_hdr));
845 h->buf = (u8 *)KSEG1ADDR(ring->tx_space +
846 i * TXRINGLEN * RING_BUFFER +
847 j * RING_BUFFER);
848 h->size = RING_BUFFER;
849 ring->tx_r[i][j] = KSEG1ADDR(&ring->tx_header[i][j]);
850 }
851 /* Last header is wrapping around */
852 ring->tx_r[i][j - 1] |= WRAP;
853 ring->c_tx[i] = 0;
854 }
855 }
856
857 static void rtl839x_setup_notify_ring_buffer(struct rtl838x_eth_priv *priv)
858 {
859 struct notify_b *b = priv->membase + sizeof(struct ring_b);
860
861 for (int i = 0; i < NOTIFY_BLOCKS; i++)
862 b->ring[i] = KSEG1ADDR(&b->blocks[i]) | 1 | (i == (NOTIFY_BLOCKS - 1) ? WRAP : 0);
863
864 sw_w32((u32) b->ring, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
865 sw_w32_mask(0x3ff << 2, 100 << 2, RTL839X_L2_NOTIFICATION_CTRL);
866
867 /* Setup notification events */
868 sw_w32_mask(0, 1 << 14, RTL839X_L2_CTRL_0); /* RTL8390_L2_CTRL_0_FLUSH_NOTIFY_EN */
869 sw_w32_mask(0, 1 << 12, RTL839X_L2_NOTIFICATION_CTRL); /* SUSPEND_NOTIFICATION_EN */
870
871 /* Enable Notification */
872 sw_w32_mask(0, 1 << 0, RTL839X_L2_NOTIFICATION_CTRL);
873 priv->lastEvent = 0;
874 }
875
876 static int rtl838x_eth_open(struct net_device *ndev)
877 {
878 unsigned long flags;
879 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
880 struct ring_b *ring = priv->membase;
881
882 pr_debug("%s called: RX rings %d(length %d), TX rings %d(length %d)\n",
883 __func__, priv->rxrings, priv->rxringlen, TXRINGS, TXRINGLEN);
884
885 spin_lock_irqsave(&priv->lock, flags);
886 rtl838x_hw_reset(priv);
887 rtl838x_setup_ring_buffer(priv, ring);
888 if (priv->family_id == RTL8390_FAMILY_ID) {
889 rtl839x_setup_notify_ring_buffer(priv);
890 /* Make sure the ring structure is visible to the ASIC */
891 mb();
892 flush_cache_all();
893 }
894
895 rtl838x_hw_ring_setup(priv);
896 phylink_start(priv->phylink);
897
898 for (int i = 0; i < priv->rxrings; i++)
899 napi_enable(&priv->rx_qs[i].napi);
900
901 switch (priv->family_id) {
902 case RTL8380_FAMILY_ID:
903 rtl838x_hw_en_rxtx(priv);
904 /* Trap IGMP/MLD traffic to CPU-Port */
905 sw_w32(0x3, RTL838X_SPCL_TRAP_IGMP_CTRL);
906 /* Flush learned FDB entries on link down of a port */
907 sw_w32_mask(0, BIT(7), RTL838X_L2_CTRL_0);
908 break;
909
910 case RTL8390_FAMILY_ID:
911 rtl839x_hw_en_rxtx(priv);
912 /* Trap MLD and IGMP messages to CPU_PORT */
913 sw_w32(0x3, RTL839X_SPCL_TRAP_IGMP_CTRL);
914 /* Flush learned FDB entries on link down of a port */
915 sw_w32_mask(0, BIT(7), RTL839X_L2_CTRL_0);
916 break;
917
918 case RTL9300_FAMILY_ID:
919 rtl93xx_hw_en_rxtx(priv);
920 /* Flush learned FDB entries on link down of a port */
921 sw_w32_mask(0, BIT(7), RTL930X_L2_CTRL);
922 /* Trap MLD and IGMP messages to CPU_PORT */
923 sw_w32((0x2 << 3) | 0x2, RTL930X_VLAN_APP_PKT_CTRL);
924 break;
925
926 case RTL9310_FAMILY_ID:
927 rtl93xx_hw_en_rxtx(priv);
928
929 /* Trap MLD and IGMP messages to CPU_PORT */
930 sw_w32((0x2 << 3) | 0x2, RTL931X_VLAN_APP_PKT_CTRL);
931
932 /* Disable External CPU access to switch, clear EXT_CPU_EN */
933 sw_w32_mask(BIT(2), 0, RTL931X_MAC_L2_GLOBAL_CTRL2);
934
935 /* Set PCIE_PWR_DOWN */
936 sw_w32_mask(0, BIT(1), RTL931X_PS_SOC_CTRL);
937 break;
938 }
939
940 netif_tx_start_all_queues(ndev);
941
942 spin_unlock_irqrestore(&priv->lock, flags);
943
944 return 0;
945 }
946
947 static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv)
948 {
949 u32 force_mac = priv->family_id == RTL8380_FAMILY_ID ? 0x6192C : 0x75;
950 u32 clear_irq = priv->family_id == RTL8380_FAMILY_ID ? 0x000fffff : 0x007fffff;
951
952 /* Disable RX/TX from/to CPU-port */
953 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
954
955 /* Disable traffic */
956 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
957 sw_w32_mask(RX_EN_93XX | TX_EN_93XX, 0, priv->r->dma_if_ctrl);
958 else
959 sw_w32_mask(RX_EN | TX_EN, 0, priv->r->dma_if_ctrl);
960 mdelay(200); /* Test, whether this is needed */
961
962 /* Block all ports */
963 if (priv->family_id == RTL8380_FAMILY_ID) {
964 sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0));
965 sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1));
966 sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0);
967 }
968
969 /* Flush L2 address cache */
970 if (priv->family_id == RTL8380_FAMILY_ID) {
971 for (int i = 0; i <= priv->cpu_port; i++) {
972 sw_w32(1 << 26 | 1 << 23 | i << 5, priv->r->l2_tbl_flush_ctrl);
973 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 26));
974 }
975 } else if (priv->family_id == RTL8390_FAMILY_ID) {
976 for (int i = 0; i <= priv->cpu_port; i++) {
977 sw_w32(1 << 28 | 1 << 25 | i << 5, priv->r->l2_tbl_flush_ctrl);
978 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 28));
979 }
980 }
981 /* TODO: L2 flush register is 64 bit on RTL931X and 930X */
982
983 /* CPU-Port: Link down */
984 if (priv->family_id == RTL8380_FAMILY_ID || priv->family_id == RTL8390_FAMILY_ID)
985 sw_w32(force_mac, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
986 else if (priv->family_id == RTL9300_FAMILY_ID)
987 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);
988 else if (priv->family_id == RTL9310_FAMILY_ID)
989 sw_w32_mask(BIT(0) | BIT(9), 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);
990 mdelay(100);
991
992 /* Disable all TX/RX interrupts */
993 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
994 sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
995 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
996 sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
997 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);
998 sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);
999 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);
1000 } else {
1001 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
1002 sw_w32(clear_irq, priv->r->dma_if_intr_sts);
1003 }
1004
1005 /* Disable TX/RX DMA */
1006 sw_w32(0x00000000, priv->r->dma_if_ctrl);
1007 mdelay(200);
1008 }
1009
1010 static int rtl838x_eth_stop(struct net_device *ndev)
1011 {
1012 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1013
1014 pr_info("in %s\n", __func__);
1015
1016 phylink_stop(priv->phylink);
1017 rtl838x_hw_stop(priv);
1018
1019 for (int i = 0; i < priv->rxrings; i++)
1020 napi_disable(&priv->rx_qs[i].napi);
1021
1022 netif_tx_stop_all_queues(ndev);
1023
1024 return 0;
1025 }
1026
1027 static void rtl838x_eth_set_multicast_list(struct net_device *ndev)
1028 {
1029 /* Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F})
1030 * CTRL_0_FULL = GENMASK(21, 0) = 0x3FFFFF
1031 */
1032 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1033 sw_w32(0x0, RTL838X_RMA_CTRL_0);
1034 sw_w32(0x0, RTL838X_RMA_CTRL_1);
1035 }
1036 if (ndev->flags & IFF_ALLMULTI)
1037 sw_w32(GENMASK(21, 0), RTL838X_RMA_CTRL_0);
1038 if (ndev->flags & IFF_PROMISC) {
1039 sw_w32(GENMASK(21, 0), RTL838X_RMA_CTRL_0);
1040 sw_w32(0x7fff, RTL838X_RMA_CTRL_1);
1041 }
1042 }
1043
1044 static void rtl839x_eth_set_multicast_list(struct net_device *ndev)
1045 {
1046 /* Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F})
1047 * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC
1048 * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00
1049 * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0)
1050 */
1051 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1052 sw_w32(0x0, RTL839X_RMA_CTRL_0);
1053 sw_w32(0x0, RTL839X_RMA_CTRL_1);
1054 sw_w32(0x0, RTL839X_RMA_CTRL_2);
1055 sw_w32(0x0, RTL839X_RMA_CTRL_3);
1056 }
1057 if (ndev->flags & IFF_ALLMULTI) {
1058 sw_w32(GENMASK(31, 2), RTL839X_RMA_CTRL_0);
1059 sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_1);
1060 sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_2);
1061 }
1062 if (ndev->flags & IFF_PROMISC) {
1063 sw_w32(GENMASK(31, 2), RTL839X_RMA_CTRL_0);
1064 sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_1);
1065 sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_2);
1066 sw_w32(0x3ff, RTL839X_RMA_CTRL_3);
1067 }
1068 }
1069
1070 static void rtl930x_eth_set_multicast_list(struct net_device *ndev)
1071 {
1072 /* Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F})
1073 * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC
1074 * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00
1075 * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0)
1076 */
1077 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1078 sw_w32(GENMASK(31, 2), RTL930X_RMA_CTRL_0);
1079 sw_w32(GENMASK(31, 0), RTL930X_RMA_CTRL_1);
1080 sw_w32(GENMASK(31, 0), RTL930X_RMA_CTRL_2);
1081 } else {
1082 sw_w32(0x0, RTL930X_RMA_CTRL_0);
1083 sw_w32(0x0, RTL930X_RMA_CTRL_1);
1084 sw_w32(0x0, RTL930X_RMA_CTRL_2);
1085 }
1086 }
1087
1088 static void rtl931x_eth_set_multicast_list(struct net_device *ndev)
1089 {
1090 /* Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F})
1091 * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC
1092 * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00.
1093 * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0)
1094 */
1095 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1096 sw_w32(GENMASK(31, 2), RTL931X_RMA_CTRL_0);
1097 sw_w32(GENMASK(31, 0), RTL931X_RMA_CTRL_1);
1098 sw_w32(GENMASK(31, 0), RTL931X_RMA_CTRL_2);
1099 } else {
1100 sw_w32(0x0, RTL931X_RMA_CTRL_0);
1101 sw_w32(0x0, RTL931X_RMA_CTRL_1);
1102 sw_w32(0x0, RTL931X_RMA_CTRL_2);
1103 }
1104 }
1105
1106 static void rtl838x_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1107 {
1108 unsigned long flags;
1109 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1110
1111 pr_warn("%s\n", __func__);
1112 spin_lock_irqsave(&priv->lock, flags);
1113 rtl838x_hw_stop(priv);
1114 rtl838x_hw_ring_setup(priv);
1115 rtl838x_hw_en_rxtx(priv);
1116 netif_trans_update(ndev);
1117 netif_start_queue(ndev);
1118 spin_unlock_irqrestore(&priv->lock, flags);
1119 }
1120
1121 static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev)
1122 {
1123 int len;
1124 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1125 struct ring_b *ring = priv->membase;
1126 int ret;
1127 unsigned long flags;
1128 struct p_hdr *h;
1129 int dest_port = -1;
1130 int q = skb_get_queue_mapping(skb) % TXRINGS;
1131
1132 if (q) /* Check for high prio queue */
1133 pr_debug("SKB priority: %d\n", skb->priority);
1134
1135 spin_lock_irqsave(&priv->lock, flags);
1136 len = skb->len;
1137
1138 /* Check for DSA tagging at the end of the buffer */
1139 if (netdev_uses_dsa(dev) &&
1140 skb->data[len - 4] == 0x80 &&
1141 skb->data[len - 3] < priv->cpu_port &&
1142 skb->data[len - 2] == 0x10 &&
1143 skb->data[len - 1] == 0x00) {
1144 /* Reuse tag space for CRC if possible */
1145 dest_port = skb->data[len - 3];
1146 skb->data[len - 4] = skb->data[len - 3] = skb->data[len - 2] = skb->data[len - 1] = 0x00;
1147 len -= 4;
1148 }
1149
1150 len += 4; /* Add space for CRC */
1151
1152 if (skb_padto(skb, len)) {
1153 ret = NETDEV_TX_OK;
1154 goto txdone;
1155 }
1156
1157 /* We can send this packet if CPU owns the descriptor */
1158 if (!(ring->tx_r[q][ring->c_tx[q]] & 0x1)) {
1159
1160 /* Set descriptor for tx */
1161 h = &ring->tx_header[q][ring->c_tx[q]];
1162 h->size = len;
1163 h->len = len;
1164 /* On RTL8380 SoCs, small packet lengths being sent need adjustments */
1165 if (priv->family_id == RTL8380_FAMILY_ID) {
1166 if (len < ETH_ZLEN - 4)
1167 h->len -= 4;
1168 }
1169
1170 if (dest_port >= 0)
1171 priv->r->create_tx_header(h, dest_port, skb->priority >> 1);
1172
1173 /* Copy packet data to tx buffer */
1174 memcpy((void *)KSEG1ADDR(h->buf), skb->data, len);
1175 /* Make sure packet data is visible to ASIC */
1176 wmb();
1177
1178 /* Hand over to switch */
1179 ring->tx_r[q][ring->c_tx[q]] |= 1;
1180
1181 /* Before starting TX, prevent a Lextra bus bug on RTL8380 SoCs */
1182 if (priv->family_id == RTL8380_FAMILY_ID) {
1183 for (int i = 0; i < 10; i++) {
1184 u32 val = sw_r32(priv->r->dma_if_ctrl);
1185 if ((val & 0xc) == 0xc)
1186 break;
1187 }
1188 }
1189
1190 /* Tell switch to send data */
1191 if (priv->family_id == RTL9310_FAMILY_ID || priv->family_id == RTL9300_FAMILY_ID) {
1192 /* Ring ID q == 0: Low priority, Ring ID = 1: High prio queue */
1193 if (!q)
1194 sw_w32_mask(0, BIT(2), priv->r->dma_if_ctrl);
1195 else
1196 sw_w32_mask(0, BIT(3), priv->r->dma_if_ctrl);
1197 } else {
1198 sw_w32_mask(0, TX_DO, priv->r->dma_if_ctrl);
1199 }
1200
1201 dev->stats.tx_packets++;
1202 dev->stats.tx_bytes += len;
1203 dev_kfree_skb(skb);
1204 ring->c_tx[q] = (ring->c_tx[q] + 1) % TXRINGLEN;
1205 ret = NETDEV_TX_OK;
1206 } else {
1207 dev_warn(&priv->pdev->dev, "Data is owned by switch\n");
1208 ret = NETDEV_TX_BUSY;
1209 }
1210
1211 txdone:
1212 spin_unlock_irqrestore(&priv->lock, flags);
1213
1214 return ret;
1215 }
1216
1217 /* Return queue number for TX. On the RTL83XX, these queues have equal priority
1218 * so we do round-robin
1219 */
1220 u16 rtl83xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
1221 struct net_device *sb_dev)
1222 {
1223 static u8 last = 0;
1224
1225 last++;
1226 return last % TXRINGS;
1227 }
1228
1229 /* Return queue number for TX. On the RTL93XX, queue 1 is the high priority queue
1230 */
1231 u16 rtl93xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
1232 struct net_device *sb_dev)
1233 {
1234 if (skb->priority >= TC_PRIO_CONTROL)
1235 return 1;
1236
1237 return 0;
1238 }
1239
1240 static int rtl838x_hw_receive(struct net_device *dev, int r, int budget)
1241 {
1242 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1243 struct ring_b *ring = priv->membase;
1244 LIST_HEAD(rx_list);
1245 unsigned long flags;
1246 int work_done = 0;
1247 u32 *last;
1248 bool dsa = netdev_uses_dsa(dev);
1249
1250 pr_debug("---------------------------------------------------------- RX - %d\n", r);
1251 spin_lock_irqsave(&priv->lock, flags);
1252 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
1253
1254 do {
1255 struct sk_buff *skb;
1256 struct dsa_tag tag;
1257 struct p_hdr *h;
1258 u8 *skb_data;
1259 u8 *data;
1260 int len;
1261
1262 if ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) {
1263 if (&ring->rx_r[r][ring->c_rx[r]] != last) {
1264 netdev_warn(dev, "Ring contention: r: %x, last %x, cur %x\n",
1265 r, (uint32_t)last, (u32) &ring->rx_r[r][ring->c_rx[r]]);
1266 }
1267 break;
1268 }
1269
1270 h = &ring->rx_header[r][ring->c_rx[r]];
1271 data = (u8 *)KSEG1ADDR(h->buf);
1272 len = h->len;
1273 if (!len)
1274 break;
1275 work_done++;
1276
1277 len -= 4; /* strip the CRC */
1278 /* Add 4 bytes for cpu_tag */
1279 if (dsa)
1280 len += 4;
1281
1282 skb = netdev_alloc_skb(dev, len + 4);
1283 skb_reserve(skb, NET_IP_ALIGN);
1284
1285 if (likely(skb)) {
1286 /* BUG: Prevent bug on RTL838x SoCs */
1287 if (priv->family_id == RTL8380_FAMILY_ID) {
1288 sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
1289 for (int i = 0; i < priv->rxrings; i++) {
1290 unsigned int val;
1291
1292 /* Update each ring cnt */
1293 val = sw_r32(priv->r->dma_if_rx_ring_cntr(i));
1294 sw_w32(val, priv->r->dma_if_rx_ring_cntr(i));
1295 }
1296 }
1297
1298 skb_data = skb_put(skb, len);
1299 /* Make sure data is visible */
1300 mb();
1301 memcpy(skb->data, (u8 *)KSEG1ADDR(data), len);
1302 /* Overwrite CRC with cpu_tag */
1303 if (dsa) {
1304 priv->r->decode_tag(h, &tag);
1305 skb->data[len - 4] = 0x80;
1306 skb->data[len - 3] = tag.port;
1307 skb->data[len - 2] = 0x10;
1308 skb->data[len - 1] = 0x00;
1309 if (tag.l2_offloaded)
1310 skb->data[len - 3] |= 0x40;
1311 }
1312
1313 if (tag.queue >= 0)
1314 pr_debug("Queue: %d, len: %d, reason %d port %d\n",
1315 tag.queue, len, tag.reason, tag.port);
1316
1317 skb->protocol = eth_type_trans(skb, dev);
1318 if (dev->features & NETIF_F_RXCSUM) {
1319 if (tag.crc_error)
1320 skb_checksum_none_assert(skb);
1321 else
1322 skb->ip_summed = CHECKSUM_UNNECESSARY;
1323 }
1324 dev->stats.rx_packets++;
1325 dev->stats.rx_bytes += len;
1326
1327 list_add_tail(&skb->list, &rx_list);
1328 } else {
1329 if (net_ratelimit())
1330 dev_warn(&dev->dev, "low on memory - packet dropped\n");
1331 dev->stats.rx_dropped++;
1332 }
1333
1334 /* Reset header structure */
1335 memset(h, 0, sizeof(struct p_hdr));
1336 h->buf = data;
1337 h->size = RING_BUFFER;
1338
1339 ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1 | (ring->c_rx[r] == (priv->rxringlen - 1) ?
1340 WRAP :
1341 0x1);
1342 ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;
1343 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
1344 } while (&ring->rx_r[r][ring->c_rx[r]] != last && work_done < budget);
1345
1346 netif_receive_skb_list(&rx_list);
1347
1348 /* Update counters */
1349 priv->r->update_cntr(r, 0);
1350
1351 spin_unlock_irqrestore(&priv->lock, flags);
1352
1353 return work_done;
1354 }
1355
1356 static int rtl838x_poll_rx(struct napi_struct *napi, int budget)
1357 {
1358 struct rtl838x_rx_q *rx_q = container_of(napi, struct rtl838x_rx_q, napi);
1359 struct rtl838x_eth_priv *priv = rx_q->priv;
1360 int work_done = 0;
1361 int r = rx_q->id;
1362 int work;
1363
1364 while (work_done < budget) {
1365 work = rtl838x_hw_receive(priv->netdev, r, budget - work_done);
1366 if (!work)
1367 break;
1368 work_done += work;
1369 }
1370
1371 if (work_done < budget) {
1372 napi_complete_done(napi, work_done);
1373
1374 /* Enable RX interrupt */
1375 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
1376 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);
1377 else
1378 sw_w32_mask(0, 0xf00ff | BIT(r + 8), priv->r->dma_if_intr_msk);
1379 }
1380
1381 return work_done;
1382 }
1383
1384
1385 static void rtl838x_validate(struct phylink_config *config,
1386 unsigned long *supported,
1387 struct phylink_link_state *state)
1388 {
1389 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1390
1391 pr_debug("In %s\n", __func__);
1392
1393 if (!phy_interface_mode_is_rgmii(state->interface) &&
1394 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
1395 state->interface != PHY_INTERFACE_MODE_MII &&
1396 state->interface != PHY_INTERFACE_MODE_REVMII &&
1397 state->interface != PHY_INTERFACE_MODE_GMII &&
1398 state->interface != PHY_INTERFACE_MODE_QSGMII &&
1399 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
1400 state->interface != PHY_INTERFACE_MODE_SGMII) {
1401 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1402 pr_err("Unsupported interface: %d\n", state->interface);
1403 return;
1404 }
1405
1406 /* Allow all the expected bits */
1407 phylink_set(mask, Autoneg);
1408 phylink_set_port_modes(mask);
1409 phylink_set(mask, Pause);
1410 phylink_set(mask, Asym_Pause);
1411
1412 /* With the exclusion of MII and Reverse MII, we support Gigabit,
1413 * including Half duplex
1414 */
1415 if (state->interface != PHY_INTERFACE_MODE_MII &&
1416 state->interface != PHY_INTERFACE_MODE_REVMII) {
1417 phylink_set(mask, 1000baseT_Full);
1418 phylink_set(mask, 1000baseT_Half);
1419 }
1420
1421 phylink_set(mask, 10baseT_Half);
1422 phylink_set(mask, 10baseT_Full);
1423 phylink_set(mask, 100baseT_Half);
1424 phylink_set(mask, 100baseT_Full);
1425
1426 bitmap_and(supported, supported, mask,
1427 __ETHTOOL_LINK_MODE_MASK_NBITS);
1428 bitmap_and(state->advertising, state->advertising, mask,
1429 __ETHTOOL_LINK_MODE_MASK_NBITS);
1430 }
1431
1432
1433 static void rtl838x_mac_config(struct phylink_config *config,
1434 unsigned int mode,
1435 const struct phylink_link_state *state)
1436 {
1437 /* This is only being called for the master device,
1438 * i.e. the CPU-Port. We don't need to do anything.
1439 */
1440
1441 pr_info("In %s, mode %x\n", __func__, mode);
1442 }
1443
1444 static void rtl838x_mac_an_restart(struct phylink_config *config)
1445 {
1446 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1447 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1448
1449 /* This works only on RTL838x chips */
1450 if (priv->family_id != RTL8380_FAMILY_ID)
1451 return;
1452
1453 pr_debug("In %s\n", __func__);
1454 /* Restart by disabling and re-enabling link */
1455 sw_w32(0x6192D, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
1456 mdelay(20);
1457 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
1458 }
1459
1460 static void rtl838x_mac_pcs_get_state(struct phylink_config *config,
1461 struct phylink_link_state *state)
1462 {
1463 u32 speed;
1464 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1465 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1466 int port = priv->cpu_port;
1467
1468 pr_info("In %s\n", __func__);
1469
1470 state->link = priv->r->get_mac_link_sts(port) ? 1 : 0;
1471 state->duplex = priv->r->get_mac_link_dup_sts(port) ? 1 : 0;
1472
1473 pr_info("%s link status is %d\n", __func__, state->link);
1474 speed = priv->r->get_mac_link_spd_sts(port);
1475 switch (speed) {
1476 case 0:
1477 state->speed = SPEED_10;
1478 break;
1479 case 1:
1480 state->speed = SPEED_100;
1481 break;
1482 case 2:
1483 state->speed = SPEED_1000;
1484 break;
1485 case 5:
1486 state->speed = SPEED_2500;
1487 break;
1488 case 6:
1489 state->speed = SPEED_5000;
1490 break;
1491 case 4:
1492 state->speed = SPEED_10000;
1493 break;
1494 default:
1495 state->speed = SPEED_UNKNOWN;
1496 break;
1497 }
1498
1499 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
1500 if (priv->r->get_mac_rx_pause_sts(port))
1501 state->pause |= MLO_PAUSE_RX;
1502 if (priv->r->get_mac_tx_pause_sts(port))
1503 state->pause |= MLO_PAUSE_TX;
1504 }
1505
1506 static void rtl838x_mac_link_down(struct phylink_config *config,
1507 unsigned int mode,
1508 phy_interface_t interface)
1509 {
1510 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1511 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1512
1513 pr_debug("In %s\n", __func__);
1514 /* Stop TX/RX to port */
1515 sw_w32_mask(0x03, 0, priv->r->mac_port_ctrl(priv->cpu_port));
1516 }
1517
1518 static void rtl838x_mac_link_up(struct phylink_config *config,
1519 struct phy_device *phy, unsigned int mode,
1520 phy_interface_t interface, int speed, int duplex,
1521 bool tx_pause, bool rx_pause)
1522 {
1523 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1524 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1525
1526 pr_debug("In %s\n", __func__);
1527 /* Restart TX/RX to port */
1528 sw_w32_mask(0, 0x03, priv->r->mac_port_ctrl(priv->cpu_port));
1529 }
1530
1531 static void rtl838x_set_mac_hw(struct net_device *dev, u8 *mac)
1532 {
1533 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1534 unsigned long flags;
1535
1536 spin_lock_irqsave(&priv->lock, flags);
1537 pr_debug("In %s\n", __func__);
1538 sw_w32((mac[0] << 8) | mac[1], priv->r->mac);
1539 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], priv->r->mac + 4);
1540
1541 if (priv->family_id == RTL8380_FAMILY_ID) {
1542 /* 2 more registers, ALE/MAC block */
1543 sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC_ALE);
1544 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
1545 (RTL838X_MAC_ALE + 4));
1546
1547 sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC2);
1548 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
1549 RTL838X_MAC2 + 4);
1550 }
1551 spin_unlock_irqrestore(&priv->lock, flags);
1552 }
1553
1554 static int rtl838x_set_mac_address(struct net_device *dev, void *p)
1555 {
1556 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1557 const struct sockaddr *addr = p;
1558 u8 *mac = (u8 *) (addr->sa_data);
1559
1560 if (!is_valid_ether_addr(addr->sa_data))
1561 return -EADDRNOTAVAIL;
1562
1563 dev_addr_set(dev, addr->sa_data);
1564 rtl838x_set_mac_hw(dev, mac);
1565
1566 pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac), sw_r32(priv->r->mac + 4));
1567
1568 return 0;
1569 }
1570
1571 static int rtl8390_init_mac(struct rtl838x_eth_priv *priv)
1572 {
1573 /* We will need to set-up EEE and the egress-rate limitation */
1574 return 0;
1575 }
1576
1577 static int rtl8380_init_mac(struct rtl838x_eth_priv *priv)
1578 {
1579 if (priv->family_id == 0x8390)
1580 return rtl8390_init_mac(priv);
1581
1582 /* At present we do not know how to set up EEE on any other SoC than RTL8380 */
1583 if (priv->family_id != 0x8380)
1584 return 0;
1585
1586 pr_info("%s\n", __func__);
1587 /* fix timer for EEE */
1588 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
1589 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
1590
1591 /* Init VLAN. TODO: Understand what is being done, here */
1592 if (priv->id == 0x8382) {
1593 for (int i = 0; i <= 28; i++)
1594 sw_w32(0, 0xd57c + i * 0x80);
1595 }
1596 if (priv->id == 0x8380) {
1597 for (int i = 8; i <= 28; i++)
1598 sw_w32(0, 0xd57c + i * 0x80);
1599 }
1600
1601 return 0;
1602 }
1603
1604 static int rtl838x_get_link_ksettings(struct net_device *ndev,
1605 struct ethtool_link_ksettings *cmd)
1606 {
1607 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1608
1609 pr_debug("%s called\n", __func__);
1610
1611 return phylink_ethtool_ksettings_get(priv->phylink, cmd);
1612 }
1613
1614 static int rtl838x_set_link_ksettings(struct net_device *ndev,
1615 const struct ethtool_link_ksettings *cmd)
1616 {
1617 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1618
1619 pr_debug("%s called\n", __func__);
1620
1621 return phylink_ethtool_ksettings_set(priv->phylink, cmd);
1622 }
1623
1624 static int rtl838x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)
1625 {
1626 u32 val;
1627 int err;
1628 struct rtl838x_eth_priv *priv = bus->priv;
1629
1630 if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380)
1631 return rtl838x_read_sds_phy(mii_id, regnum);
1632
1633 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1634 err = rtl838x_read_mmd_phy(mii_id,
1635 mdiobus_c45_devad(regnum),
1636 regnum, &val);
1637 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id,
1638 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1639 val, err);
1640 } else {
1641 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err);
1642 err = rtl838x_read_phy(mii_id, page, regnum, &val);
1643 }
1644 if (err)
1645 return err;
1646
1647 return val;
1648 }
1649
1650 static int rtl838x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1651 {
1652 return rtl838x_mdio_read_paged(bus, mii_id, 0, regnum);
1653 }
1654
1655 static int rtl839x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)
1656 {
1657 u32 val;
1658 int err;
1659 struct rtl838x_eth_priv *priv = bus->priv;
1660
1661 if (priv->phy_is_internal[mii_id])
1662 return rtl839x_read_sds_phy(mii_id, regnum);
1663
1664 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1665 err = rtl839x_read_mmd_phy(mii_id,
1666 mdiobus_c45_devad(regnum),
1667 regnum, &val);
1668 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id,
1669 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1670 val, err);
1671 } else {
1672 err = rtl839x_read_phy(mii_id, page, regnum, &val);
1673 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err);
1674 }
1675
1676 if (err)
1677 return err;
1678
1679 return val;
1680 }
1681
1682 static int rtl839x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1683 {
1684 return rtl839x_mdio_read_paged(bus, mii_id, 0, regnum);
1685 }
1686
1687 static int rtl930x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)
1688 {
1689 u32 val;
1690 int err;
1691 struct rtl838x_eth_priv *priv = bus->priv;
1692
1693 if (priv->phy_is_internal[mii_id])
1694 return rtl930x_read_sds_phy(priv->sds_id[mii_id], page, regnum);
1695
1696 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1697 err = rtl930x_read_mmd_phy(mii_id,
1698 mdiobus_c45_devad(regnum),
1699 regnum, &val);
1700 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id,
1701 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1702 val, err);
1703 } else {
1704 err = rtl930x_read_phy(mii_id, page, regnum, &val);
1705 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err);
1706 }
1707
1708 if (err)
1709 return err;
1710
1711 return val;
1712 }
1713
1714 static int rtl930x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1715 {
1716 return rtl930x_mdio_read_paged(bus, mii_id, 0, regnum);
1717 }
1718
1719 static int rtl931x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)
1720 {
1721 u32 val;
1722 int err, v;
1723 struct rtl838x_eth_priv *priv = bus->priv;
1724
1725 pr_debug("%s: In here, port %d\n", __func__, mii_id);
1726 if (priv->phy_is_internal[mii_id]) {
1727 v = rtl931x_read_sds_phy(priv->sds_id[mii_id], page, regnum);
1728 if (v < 0) {
1729 err = v;
1730 } else {
1731 err = 0;
1732 val = v;
1733 }
1734 } else {
1735 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1736 err = rtl931x_read_mmd_phy(mii_id,
1737 mdiobus_c45_devad(regnum),
1738 regnum, &val);
1739 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id,
1740 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1741 val, err);
1742 } else {
1743 err = rtl931x_read_phy(mii_id, page, regnum, &val);
1744 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err);
1745 }
1746 }
1747
1748 if (err)
1749 return err;
1750
1751 return val;
1752 }
1753
1754 static int rtl931x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1755 {
1756 return rtl931x_mdio_read_paged(bus, mii_id, 0, regnum);
1757 }
1758
1759 static int rtl838x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
1760 int regnum, u16 value)
1761 {
1762 u32 offset = 0;
1763 struct rtl838x_eth_priv *priv = bus->priv;
1764 int err;
1765
1766 if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380) {
1767 if (mii_id == 26)
1768 offset = 0x100;
1769 sw_w32(value, RTL838X_SDS4_FIB_REG0 + offset + (regnum << 2));
1770 return 0;
1771 }
1772
1773 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1774 err = rtl838x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),
1775 regnum, value);
1776 pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id,
1777 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1778 value, err);
1779
1780 return err;
1781 }
1782 err = rtl838x_write_phy(mii_id, page, regnum, value);
1783 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err);
1784
1785 return err;
1786 }
1787
1788 static int rtl838x_mdio_write(struct mii_bus *bus, int mii_id,
1789 int regnum, u16 value)
1790 {
1791 return rtl838x_mdio_write_paged(bus, mii_id, 0, regnum, value);
1792 }
1793
1794 static int rtl839x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
1795 int regnum, u16 value)
1796 {
1797 struct rtl838x_eth_priv *priv = bus->priv;
1798 int err;
1799
1800 if (priv->phy_is_internal[mii_id])
1801 return rtl839x_write_sds_phy(mii_id, regnum, value);
1802
1803 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1804 err = rtl839x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),
1805 regnum, value);
1806 pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id,
1807 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1808 value, err);
1809
1810 return err;
1811 }
1812
1813 err = rtl839x_write_phy(mii_id, page, regnum, value);
1814 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err);
1815
1816 return err;
1817 }
1818
1819 static int rtl839x_mdio_write(struct mii_bus *bus, int mii_id,
1820 int regnum, u16 value)
1821 {
1822 return rtl839x_mdio_write_paged(bus, mii_id, 0, regnum, value);
1823 }
1824
1825 static int rtl930x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
1826 int regnum, u16 value)
1827 {
1828 struct rtl838x_eth_priv *priv = bus->priv;
1829 int err;
1830
1831 if (priv->phy_is_internal[mii_id])
1832 return rtl930x_write_sds_phy(priv->sds_id[mii_id], page, regnum, value);
1833
1834 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD))
1835 return rtl930x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),
1836 regnum, value);
1837
1838 err = rtl930x_write_phy(mii_id, page, regnum, value);
1839 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err);
1840
1841 return err;
1842 }
1843
1844 static int rtl930x_mdio_write(struct mii_bus *bus, int mii_id,
1845 int regnum, u16 value)
1846 {
1847 return rtl930x_mdio_write_paged(bus, mii_id, 0, regnum, value);
1848 }
1849
1850 static int rtl931x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
1851 int regnum, u16 value)
1852 {
1853 struct rtl838x_eth_priv *priv = bus->priv;
1854 int err;
1855
1856 if (priv->phy_is_internal[mii_id])
1857 return rtl931x_write_sds_phy(priv->sds_id[mii_id], page, regnum, value);
1858
1859 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1860 err = rtl931x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),
1861 regnum, value);
1862 pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id,
1863 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1864 value, err);
1865
1866 return err;
1867 }
1868
1869 err = rtl931x_write_phy(mii_id, page, regnum, value);
1870 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err);
1871
1872 return err;
1873 }
1874
1875 static int rtl931x_mdio_write(struct mii_bus *bus, int mii_id,
1876 int regnum, u16 value)
1877 {
1878 return rtl931x_mdio_write_paged(bus, mii_id, 0, regnum, value);
1879 }
1880
1881 static int rtl838x_mdio_reset(struct mii_bus *bus)
1882 {
1883 pr_debug("%s called\n", __func__);
1884 /* Disable MAC polling the PHY so that we can start configuration */
1885 sw_w32(0x00000000, RTL838X_SMI_POLL_CTRL);
1886
1887 /* Enable PHY control via SoC */
1888 sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL);
1889
1890 /* Probably should reset all PHYs here... */
1891 return 0;
1892 }
1893
1894 static int rtl839x_mdio_reset(struct mii_bus *bus)
1895 {
1896 return 0;
1897
1898 pr_debug("%s called\n", __func__);
1899 /* BUG: The following does not work, but should! */
1900 /* Disable MAC polling the PHY so that we can start configuration */
1901 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL);
1902 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL + 4);
1903 /* Disable PHY polling via SoC */
1904 sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL);
1905
1906 /* Probably should reset all PHYs here... */
1907 return 0;
1908 }
1909
1910 u8 mac_type_bit[RTL930X_CPU_PORT] = {0, 0, 0, 0, 2, 2, 2, 2, 4, 4, 4, 4, 6, 6, 6, 6,
1911 8, 8, 8, 8, 10, 10, 10, 10, 12, 15, 18, 21};
1912
1913 static int rtl930x_mdio_reset(struct mii_bus *bus)
1914 {
1915 struct rtl838x_eth_priv *priv = bus->priv;
1916 u32 c45_mask = 0;
1917 u32 poll_sel[2];
1918 u32 poll_ctrl = 0;
1919 u32 private_poll_mask = 0;
1920 u32 v;
1921 bool uses_usxgmii = false; /* For the Aquantia PHYs */
1922 bool uses_hisgmii = false; /* For the RTL8221/8226 */
1923
1924 /* Mapping of port to phy-addresses on an SMI bus */
1925 poll_sel[0] = poll_sel[1] = 0;
1926 for (int i = 0; i < RTL930X_CPU_PORT; i++) {
1927 int pos;
1928
1929 if (priv->smi_bus[i] > 3)
1930 continue;
1931 pos = (i % 6) * 5;
1932 sw_w32_mask(0x1f << pos, priv->smi_addr[i] << pos,
1933 RTL930X_SMI_PORT0_5_ADDR + (i / 6) * 4);
1934
1935 pos = (i * 2) % 32;
1936 poll_sel[i / 16] |= priv->smi_bus[i] << pos;
1937 poll_ctrl |= BIT(20 + priv->smi_bus[i]);
1938 }
1939
1940 /* Configure which SMI bus is behind which port number */
1941 sw_w32(poll_sel[0], RTL930X_SMI_PORT0_15_POLLING_SEL);
1942 sw_w32(poll_sel[1], RTL930X_SMI_PORT16_27_POLLING_SEL);
1943
1944 /* Disable POLL_SEL for any SMI bus with a normal PHY (not RTL8295R for SFP+) */
1945 sw_w32_mask(poll_ctrl, 0, RTL930X_SMI_GLB_CTRL);
1946
1947 /* Configure which SMI busses are polled in c45 based on a c45 PHY being on that bus */
1948 for (int i = 0; i < 4; i++)
1949 if (priv->smi_bus_isc45[i])
1950 c45_mask |= BIT(i + 16);
1951
1952 pr_info("c45_mask: %08x\n", c45_mask);
1953 sw_w32_mask(0, c45_mask, RTL930X_SMI_GLB_CTRL);
1954
1955 /* Set the MAC type of each port according to the PHY-interface */
1956 /* Values are FE: 2, GE: 3, XGE/2.5G: 0(SERDES) or 1(otherwise), SXGE: 0 */
1957 v = 0;
1958 for (int i = 0; i < RTL930X_CPU_PORT; i++) {
1959 switch (priv->interfaces[i]) {
1960 case PHY_INTERFACE_MODE_10GBASER:
1961 break; /* Serdes: Value = 0 */
1962 case PHY_INTERFACE_MODE_HSGMII:
1963 private_poll_mask |= BIT(i);
1964 fallthrough;
1965 case PHY_INTERFACE_MODE_USXGMII:
1966 v |= BIT(mac_type_bit[i]);
1967 uses_usxgmii = true;
1968 break;
1969 case PHY_INTERFACE_MODE_QSGMII:
1970 private_poll_mask |= BIT(i);
1971 v |= 3 << mac_type_bit[i];
1972 break;
1973 default:
1974 break;
1975 }
1976 }
1977 sw_w32(v, RTL930X_SMI_MAC_TYPE_CTRL);
1978
1979 /* Set the private polling mask for all Realtek PHYs (i.e. not the 10GBit Aquantia ones) */
1980 sw_w32(private_poll_mask, RTL930X_SMI_PRVTE_POLLING_CTRL);
1981
1982 /* The following magic values are found in the port configuration, they seem to
1983 * define different ways of polling a PHY. The below is for the Aquantia PHYs of
1984 * the XGS1250 and the RTL8226 of the XGS1210
1985 */
1986 if (uses_usxgmii) {
1987 sw_w32(0x01010000, RTL930X_SMI_10GPHY_POLLING_REG0_CFG);
1988 sw_w32(0x01E7C400, RTL930X_SMI_10GPHY_POLLING_REG9_CFG);
1989 sw_w32(0x01E7E820, RTL930X_SMI_10GPHY_POLLING_REG10_CFG);
1990 }
1991 if (uses_hisgmii) {
1992 sw_w32(0x011FA400, RTL930X_SMI_10GPHY_POLLING_REG0_CFG);
1993 sw_w32(0x013FA412, RTL930X_SMI_10GPHY_POLLING_REG9_CFG);
1994 sw_w32(0x017FA414, RTL930X_SMI_10GPHY_POLLING_REG10_CFG);
1995 }
1996
1997 pr_debug("%s: RTL930X_SMI_GLB_CTRL %08x\n", __func__,
1998 sw_r32(RTL930X_SMI_GLB_CTRL));
1999 pr_debug("%s: RTL930X_SMI_PORT0_15_POLLING_SEL %08x\n", __func__,
2000 sw_r32(RTL930X_SMI_PORT0_15_POLLING_SEL));
2001 pr_debug("%s: RTL930X_SMI_PORT16_27_POLLING_SEL %08x\n", __func__,
2002 sw_r32(RTL930X_SMI_PORT16_27_POLLING_SEL));
2003 pr_debug("%s: RTL930X_SMI_MAC_TYPE_CTRL %08x\n", __func__,
2004 sw_r32(RTL930X_SMI_MAC_TYPE_CTRL));
2005 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG0_CFG %08x\n", __func__,
2006 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG0_CFG));
2007 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG9_CFG %08x\n", __func__,
2008 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG9_CFG));
2009 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG10_CFG %08x\n", __func__,
2010 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG10_CFG));
2011 pr_debug("%s: RTL930X_SMI_PRVTE_POLLING_CTRL %08x\n", __func__,
2012 sw_r32(RTL930X_SMI_PRVTE_POLLING_CTRL));
2013
2014 return 0;
2015 }
2016
2017 static int rtl931x_mdio_reset(struct mii_bus *bus)
2018 {
2019 struct rtl838x_eth_priv *priv = bus->priv;
2020 u32 c45_mask = 0;
2021 u32 poll_sel[4];
2022 u32 poll_ctrl = 0;
2023 bool mdc_on[4];
2024
2025 pr_info("%s called\n", __func__);
2026 /* Disable port polling for configuration purposes */
2027 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
2028 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
2029 msleep(100);
2030
2031 mdc_on[0] = mdc_on[1] = mdc_on[2] = mdc_on[3] = false;
2032 /* Mapping of port to phy-addresses on an SMI bus */
2033 poll_sel[0] = poll_sel[1] = poll_sel[2] = poll_sel[3] = 0;
2034 for (int i = 0; i < 56; i++) {
2035 u32 pos;
2036
2037 pos = (i % 6) * 5;
2038 sw_w32_mask(0x1f << pos, priv->smi_addr[i] << pos, RTL931X_SMI_PORT_ADDR + (i / 6) * 4);
2039 pos = (i * 2) % 32;
2040 poll_sel[i / 16] |= priv->smi_bus[i] << pos;
2041 poll_ctrl |= BIT(20 + priv->smi_bus[i]);
2042 mdc_on[priv->smi_bus[i]] = true;
2043 }
2044
2045 /* Configure which SMI bus is behind which port number */
2046 for (int i = 0; i < 4; i++) {
2047 pr_info("poll sel %d, %08x\n", i, poll_sel[i]);
2048 sw_w32(poll_sel[i], RTL931X_SMI_PORT_POLLING_SEL + (i * 4));
2049 }
2050
2051 /* Configure which SMI busses */
2052 pr_info("%s: WAS RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2));
2053 pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0));
2054 for (int i = 0; i < 4; i++) {
2055 /* bus is polled in c45 */
2056 if (priv->smi_bus_isc45[i])
2057 c45_mask |= 0x2 << (i * 2); /* Std. C45, non-standard is 0x3 */
2058 /* Enable bus access via MDC */
2059 if (mdc_on[i])
2060 sw_w32_mask(0, BIT(9 + i), RTL931X_MAC_L2_GLOBAL_CTRL2);
2061 }
2062
2063 pr_info("%s: RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2));
2064 pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0));
2065
2066 /* We have a 10G PHY enable polling
2067 * sw_w32(0x01010000, RTL931X_SMI_10GPHY_POLLING_SEL2);
2068 * sw_w32(0x01E7C400, RTL931X_SMI_10GPHY_POLLING_SEL3);
2069 * sw_w32(0x01E7E820, RTL931X_SMI_10GPHY_POLLING_SEL4);
2070 */
2071 sw_w32_mask(0xff, c45_mask, RTL931X_SMI_GLB_CTRL1);
2072
2073 return 0;
2074 }
2075
2076 static int rtl931x_chip_init(struct rtl838x_eth_priv *priv)
2077 {
2078 pr_info("In %s\n", __func__);
2079
2080 /* Initialize Encapsulation memory and wait until finished */
2081 sw_w32(0x1, RTL931X_MEM_ENCAP_INIT);
2082 do { } while (sw_r32(RTL931X_MEM_ENCAP_INIT) & 1);
2083 pr_info("%s: init ENCAP done\n", __func__);
2084
2085 /* Initialize Managemen Information Base memory and wait until finished */
2086 sw_w32(0x1, RTL931X_MEM_MIB_INIT);
2087 do { } while (sw_r32(RTL931X_MEM_MIB_INIT) & 1);
2088 pr_info("%s: init MIB done\n", __func__);
2089
2090 /* Initialize ACL (PIE) memory and wait until finished */
2091 sw_w32(0x1, RTL931X_MEM_ACL_INIT);
2092 do { } while (sw_r32(RTL931X_MEM_ACL_INIT) & 1);
2093 pr_info("%s: init ACL done\n", __func__);
2094
2095 /* Initialize ALE memory and wait until finished */
2096 sw_w32(0xFFFFFFFF, RTL931X_MEM_ALE_INIT_0);
2097 do { } while (sw_r32(RTL931X_MEM_ALE_INIT_0));
2098 sw_w32(0x7F, RTL931X_MEM_ALE_INIT_1);
2099 sw_w32(0x7ff, RTL931X_MEM_ALE_INIT_2);
2100 do { } while (sw_r32(RTL931X_MEM_ALE_INIT_2) & 0x7ff);
2101 pr_info("%s: init ALE done\n", __func__);
2102
2103 /* Enable ESD auto recovery */
2104 sw_w32(0x1, RTL931X_MDX_CTRL_RSVD);
2105
2106 /* Init SPI, is this for thermal control or what? */
2107 sw_w32_mask(0x7 << 11, 0x2 << 11, RTL931X_SPI_CTRL0);
2108
2109 return 0;
2110 }
2111
2112 static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv)
2113 {
2114 struct device_node *mii_np, *dn;
2115 u32 pn;
2116 int ret;
2117
2118 pr_debug("%s called\n", __func__);
2119 mii_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus");
2120
2121 if (!mii_np) {
2122 dev_err(&priv->pdev->dev, "no %s child node found", "mdio-bus");
2123 return -ENODEV;
2124 }
2125
2126 if (!of_device_is_available(mii_np)) {
2127 ret = -ENODEV;
2128 goto err_put_node;
2129 }
2130
2131 priv->mii_bus = devm_mdiobus_alloc(&priv->pdev->dev);
2132 if (!priv->mii_bus) {
2133 ret = -ENOMEM;
2134 goto err_put_node;
2135 }
2136
2137 switch(priv->family_id) {
2138 case RTL8380_FAMILY_ID:
2139 priv->mii_bus->name = "rtl838x-eth-mdio";
2140 priv->mii_bus->read = rtl838x_mdio_read;
2141 priv->mii_bus->read_paged = rtl838x_mdio_read_paged;
2142 priv->mii_bus->write = rtl838x_mdio_write;
2143 priv->mii_bus->write_paged = rtl838x_mdio_write_paged;
2144 priv->mii_bus->reset = rtl838x_mdio_reset;
2145 break;
2146 case RTL8390_FAMILY_ID:
2147 priv->mii_bus->name = "rtl839x-eth-mdio";
2148 priv->mii_bus->read = rtl839x_mdio_read;
2149 priv->mii_bus->read_paged = rtl839x_mdio_read_paged;
2150 priv->mii_bus->write = rtl839x_mdio_write;
2151 priv->mii_bus->write_paged = rtl839x_mdio_write_paged;
2152 priv->mii_bus->reset = rtl839x_mdio_reset;
2153 break;
2154 case RTL9300_FAMILY_ID:
2155 priv->mii_bus->name = "rtl930x-eth-mdio";
2156 priv->mii_bus->read = rtl930x_mdio_read;
2157 priv->mii_bus->read_paged = rtl930x_mdio_read_paged;
2158 priv->mii_bus->write = rtl930x_mdio_write;
2159 priv->mii_bus->write_paged = rtl930x_mdio_write_paged;
2160 priv->mii_bus->reset = rtl930x_mdio_reset;
2161 priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
2162 break;
2163 case RTL9310_FAMILY_ID:
2164 priv->mii_bus->name = "rtl931x-eth-mdio";
2165 priv->mii_bus->read = rtl931x_mdio_read;
2166 priv->mii_bus->read_paged = rtl931x_mdio_read_paged;
2167 priv->mii_bus->write = rtl931x_mdio_write;
2168 priv->mii_bus->write_paged = rtl931x_mdio_write_paged;
2169 priv->mii_bus->reset = rtl931x_mdio_reset;
2170 priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
2171 break;
2172 }
2173 priv->mii_bus->access_capabilities = MDIOBUS_ACCESS_C22_MMD;
2174 priv->mii_bus->priv = priv;
2175 priv->mii_bus->parent = &priv->pdev->dev;
2176
2177 for_each_node_by_name(dn, "ethernet-phy") {
2178 u32 smi_addr[2];
2179
2180 if (of_property_read_u32(dn, "reg", &pn))
2181 continue;
2182
2183 if (of_property_read_u32_array(dn, "rtl9300,smi-address", &smi_addr[0], 2)) {
2184 smi_addr[0] = 0;
2185 smi_addr[1] = pn;
2186 }
2187
2188 if (of_property_read_u32(dn, "sds", &priv->sds_id[pn]))
2189 priv->sds_id[pn] = -1;
2190 else {
2191 pr_info("set sds port %d to %d\n", pn, priv->sds_id[pn]);
2192 }
2193
2194 if (pn < MAX_PORTS) {
2195 priv->smi_bus[pn] = smi_addr[0];
2196 priv->smi_addr[pn] = smi_addr[1];
2197 } else {
2198 pr_err("%s: illegal port number %d\n", __func__, pn);
2199 }
2200
2201 if (of_device_is_compatible(dn, "ethernet-phy-ieee802.3-c45"))
2202 priv->smi_bus_isc45[smi_addr[0]] = true;
2203
2204 if (of_property_read_bool(dn, "phy-is-integrated")) {
2205 priv->phy_is_internal[pn] = true;
2206 }
2207 }
2208
2209 dn = of_find_compatible_node(NULL, NULL, "realtek,rtl83xx-switch");
2210 if (!dn) {
2211 dev_err(&priv->pdev->dev, "No RTL switch node in DTS\n");
2212 return -ENODEV;
2213 }
2214
2215 for_each_node_by_name(dn, "port") {
2216 if (of_property_read_u32(dn, "reg", &pn))
2217 continue;
2218 pr_debug("%s Looking at port %d\n", __func__, pn);
2219 if (pn > priv->cpu_port)
2220 continue;
2221 if (of_get_phy_mode(dn, &priv->interfaces[pn]))
2222 priv->interfaces[pn] = PHY_INTERFACE_MODE_NA;
2223 pr_debug("%s phy mode of port %d is %s\n", __func__, pn, phy_modes(priv->interfaces[pn]));
2224 }
2225
2226 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
2227 ret = of_mdiobus_register(priv->mii_bus, mii_np);
2228
2229 err_put_node:
2230 of_node_put(mii_np);
2231
2232 return ret;
2233 }
2234
2235 static int rtl838x_mdio_remove(struct rtl838x_eth_priv *priv)
2236 {
2237 pr_debug("%s called\n", __func__);
2238 if (!priv->mii_bus)
2239 return 0;
2240
2241 mdiobus_unregister(priv->mii_bus);
2242 mdiobus_free(priv->mii_bus);
2243
2244 return 0;
2245 }
2246
2247 static netdev_features_t rtl838x_fix_features(struct net_device *dev,
2248 netdev_features_t features)
2249 {
2250 return features;
2251 }
2252
2253 static int rtl83xx_set_features(struct net_device *dev, netdev_features_t features)
2254 {
2255 struct rtl838x_eth_priv *priv = netdev_priv(dev);
2256
2257 if ((features ^ dev->features) & NETIF_F_RXCSUM) {
2258 if (!(features & NETIF_F_RXCSUM))
2259 sw_w32_mask(BIT(3), 0, priv->r->mac_port_ctrl(priv->cpu_port));
2260 else
2261 sw_w32_mask(0, BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
2262 }
2263
2264 return 0;
2265 }
2266
2267 static int rtl93xx_set_features(struct net_device *dev, netdev_features_t features)
2268 {
2269 struct rtl838x_eth_priv *priv = netdev_priv(dev);
2270
2271 if ((features ^ dev->features) & NETIF_F_RXCSUM) {
2272 if (!(features & NETIF_F_RXCSUM))
2273 sw_w32_mask(BIT(4), 0, priv->r->mac_port_ctrl(priv->cpu_port));
2274 else
2275 sw_w32_mask(0, BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
2276 }
2277
2278 return 0;
2279 }
2280
2281 static const struct net_device_ops rtl838x_eth_netdev_ops = {
2282 .ndo_open = rtl838x_eth_open,
2283 .ndo_stop = rtl838x_eth_stop,
2284 .ndo_start_xmit = rtl838x_eth_tx,
2285 .ndo_select_queue = rtl83xx_pick_tx_queue,
2286 .ndo_set_mac_address = rtl838x_set_mac_address,
2287 .ndo_validate_addr = eth_validate_addr,
2288 .ndo_set_rx_mode = rtl838x_eth_set_multicast_list,
2289 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2290 .ndo_set_features = rtl83xx_set_features,
2291 .ndo_fix_features = rtl838x_fix_features,
2292 .ndo_setup_tc = rtl83xx_setup_tc,
2293 };
2294
2295 static const struct net_device_ops rtl839x_eth_netdev_ops = {
2296 .ndo_open = rtl838x_eth_open,
2297 .ndo_stop = rtl838x_eth_stop,
2298 .ndo_start_xmit = rtl838x_eth_tx,
2299 .ndo_select_queue = rtl83xx_pick_tx_queue,
2300 .ndo_set_mac_address = rtl838x_set_mac_address,
2301 .ndo_validate_addr = eth_validate_addr,
2302 .ndo_set_rx_mode = rtl839x_eth_set_multicast_list,
2303 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2304 .ndo_set_features = rtl83xx_set_features,
2305 .ndo_fix_features = rtl838x_fix_features,
2306 .ndo_setup_tc = rtl83xx_setup_tc,
2307 };
2308
2309 static const struct net_device_ops rtl930x_eth_netdev_ops = {
2310 .ndo_open = rtl838x_eth_open,
2311 .ndo_stop = rtl838x_eth_stop,
2312 .ndo_start_xmit = rtl838x_eth_tx,
2313 .ndo_select_queue = rtl93xx_pick_tx_queue,
2314 .ndo_set_mac_address = rtl838x_set_mac_address,
2315 .ndo_validate_addr = eth_validate_addr,
2316 .ndo_set_rx_mode = rtl930x_eth_set_multicast_list,
2317 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2318 .ndo_set_features = rtl93xx_set_features,
2319 .ndo_fix_features = rtl838x_fix_features,
2320 .ndo_setup_tc = rtl83xx_setup_tc,
2321 };
2322
2323 static const struct net_device_ops rtl931x_eth_netdev_ops = {
2324 .ndo_open = rtl838x_eth_open,
2325 .ndo_stop = rtl838x_eth_stop,
2326 .ndo_start_xmit = rtl838x_eth_tx,
2327 .ndo_select_queue = rtl93xx_pick_tx_queue,
2328 .ndo_set_mac_address = rtl838x_set_mac_address,
2329 .ndo_validate_addr = eth_validate_addr,
2330 .ndo_set_rx_mode = rtl931x_eth_set_multicast_list,
2331 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2332 .ndo_set_features = rtl93xx_set_features,
2333 .ndo_fix_features = rtl838x_fix_features,
2334 };
2335
2336 static const struct phylink_mac_ops rtl838x_phylink_ops = {
2337 .validate = rtl838x_validate,
2338 .mac_pcs_get_state = rtl838x_mac_pcs_get_state,
2339 .mac_an_restart = rtl838x_mac_an_restart,
2340 .mac_config = rtl838x_mac_config,
2341 .mac_link_down = rtl838x_mac_link_down,
2342 .mac_link_up = rtl838x_mac_link_up,
2343 };
2344
2345 static const struct ethtool_ops rtl838x_ethtool_ops = {
2346 .get_link_ksettings = rtl838x_get_link_ksettings,
2347 .set_link_ksettings = rtl838x_set_link_ksettings,
2348 };
2349
2350 static int __init rtl838x_eth_probe(struct platform_device *pdev)
2351 {
2352 struct net_device *dev;
2353 struct device_node *dn = pdev->dev.of_node;
2354 struct rtl838x_eth_priv *priv;
2355 struct resource *res, *mem;
2356 phy_interface_t phy_mode;
2357 struct phylink *phylink;
2358 u8 mac_addr[ETH_ALEN];
2359 int err = 0, rxrings, rxringlen;
2360 struct ring_b *ring;
2361
2362 pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n",
2363 (u32)pdev, (u32)(&(pdev->dev)));
2364
2365 if (!dn) {
2366 dev_err(&pdev->dev, "No DT found\n");
2367 return -EINVAL;
2368 }
2369
2370 rxrings = (soc_info.family == RTL8380_FAMILY_ID
2371 || soc_info.family == RTL8390_FAMILY_ID) ? 8 : 32;
2372 rxrings = rxrings > MAX_RXRINGS ? MAX_RXRINGS : rxrings;
2373 rxringlen = MAX_ENTRIES / rxrings;
2374 rxringlen = rxringlen > MAX_RXLEN ? MAX_RXLEN : rxringlen;
2375
2376 dev = alloc_etherdev_mqs(sizeof(struct rtl838x_eth_priv), TXRINGS, rxrings);
2377 if (!dev) {
2378 err = -ENOMEM;
2379 goto err_free;
2380 }
2381 SET_NETDEV_DEV(dev, &pdev->dev);
2382 priv = netdev_priv(dev);
2383
2384 /* obtain buffer memory space */
2385 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2386 if (res) {
2387 mem = devm_request_mem_region(&pdev->dev, res->start,
2388 resource_size(res), res->name);
2389 if (!mem) {
2390 dev_err(&pdev->dev, "cannot request memory space\n");
2391 err = -ENXIO;
2392 goto err_free;
2393 }
2394
2395 dev->mem_start = mem->start;
2396 dev->mem_end = mem->end;
2397 } else {
2398 dev_err(&pdev->dev, "cannot request IO resource\n");
2399 err = -ENXIO;
2400 goto err_free;
2401 }
2402
2403 /* Allocate buffer memory */
2404 priv->membase = dmam_alloc_coherent(&pdev->dev, rxrings * rxringlen * RING_BUFFER +
2405 sizeof(struct ring_b) + sizeof(struct notify_b),
2406 (void *)&dev->mem_start, GFP_KERNEL);
2407 if (!priv->membase) {
2408 dev_err(&pdev->dev, "cannot allocate DMA buffer\n");
2409 err = -ENOMEM;
2410 goto err_free;
2411 }
2412
2413 /* Allocate ring-buffer space at the end of the allocated memory */
2414 ring = priv->membase;
2415 ring->rx_space = priv->membase + sizeof(struct ring_b) + sizeof(struct notify_b);
2416
2417 spin_lock_init(&priv->lock);
2418
2419 dev->ethtool_ops = &rtl838x_ethtool_ops;
2420 dev->min_mtu = ETH_ZLEN;
2421 dev->max_mtu = DEFAULT_MTU;
2422 dev->features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM;
2423 dev->hw_features = NETIF_F_RXCSUM;
2424
2425 priv->id = soc_info.id;
2426 priv->family_id = soc_info.family;
2427 if (priv->id) {
2428 pr_info("Found SoC ID: %4x: %s, family %x\n",
2429 priv->id, soc_info.name, priv->family_id);
2430 } else {
2431 pr_err("Unknown chip id (%04x)\n", priv->id);
2432 return -ENODEV;
2433 }
2434
2435 switch (priv->family_id) {
2436 case RTL8380_FAMILY_ID:
2437 priv->cpu_port = RTL838X_CPU_PORT;
2438 priv->r = &rtl838x_reg;
2439 dev->netdev_ops = &rtl838x_eth_netdev_ops;
2440 break;
2441 case RTL8390_FAMILY_ID:
2442 priv->cpu_port = RTL839X_CPU_PORT;
2443 priv->r = &rtl839x_reg;
2444 dev->netdev_ops = &rtl839x_eth_netdev_ops;
2445 break;
2446 case RTL9300_FAMILY_ID:
2447 priv->cpu_port = RTL930X_CPU_PORT;
2448 priv->r = &rtl930x_reg;
2449 dev->netdev_ops = &rtl930x_eth_netdev_ops;
2450 break;
2451 case RTL9310_FAMILY_ID:
2452 priv->cpu_port = RTL931X_CPU_PORT;
2453 priv->r = &rtl931x_reg;
2454 dev->netdev_ops = &rtl931x_eth_netdev_ops;
2455 rtl931x_chip_init(priv);
2456 break;
2457 default:
2458 pr_err("Unknown SoC family\n");
2459 return -ENODEV;
2460 }
2461 priv->rxringlen = rxringlen;
2462 priv->rxrings = rxrings;
2463
2464 /* Obtain device IRQ number */
2465 dev->irq = platform_get_irq(pdev, 0);
2466 if (dev->irq < 0) {
2467 dev_err(&pdev->dev, "cannot obtain network-device IRQ\n");
2468 goto err_free;
2469 }
2470
2471 err = devm_request_irq(&pdev->dev, dev->irq, priv->r->net_irq,
2472 IRQF_SHARED, dev->name, dev);
2473 if (err) {
2474 dev_err(&pdev->dev, "%s: could not acquire interrupt: %d\n",
2475 __func__, err);
2476 goto err_free;
2477 }
2478
2479 rtl8380_init_mac(priv);
2480
2481 /* Try to get mac address in the following order:
2482 * 1) from device tree data
2483 * 2) from internal registers set by bootloader
2484 */
2485 of_get_mac_address(pdev->dev.of_node, mac_addr);
2486 if (is_valid_ether_addr(mac_addr)) {
2487 rtl838x_set_mac_hw(dev, mac_addr);
2488 } else {
2489 mac_addr[0] = (sw_r32(priv->r->mac) >> 8) & 0xff;
2490 mac_addr[1] = sw_r32(priv->r->mac) & 0xff;
2491 mac_addr[2] = (sw_r32(priv->r->mac + 4) >> 24) & 0xff;
2492 mac_addr[3] = (sw_r32(priv->r->mac + 4) >> 16) & 0xff;
2493 mac_addr[4] = (sw_r32(priv->r->mac + 4) >> 8) & 0xff;
2494 mac_addr[5] = sw_r32(priv->r->mac + 4) & 0xff;
2495 }
2496 dev_addr_set(dev, mac_addr);
2497 /* if the address is invalid, use a random value */
2498 if (!is_valid_ether_addr(dev->dev_addr)) {
2499 struct sockaddr sa = { AF_UNSPEC };
2500
2501 netdev_warn(dev, "Invalid MAC address, using random\n");
2502 eth_hw_addr_random(dev);
2503 memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN);
2504 if (rtl838x_set_mac_address(dev, &sa))
2505 netdev_warn(dev, "Failed to set MAC address.\n");
2506 }
2507 pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac),
2508 sw_r32(priv->r->mac + 4));
2509 strcpy(dev->name, "eth%d");
2510 priv->pdev = pdev;
2511 priv->netdev = dev;
2512
2513 err = rtl838x_mdio_init(priv);
2514 if (err)
2515 goto err_free;
2516
2517 err = register_netdev(dev);
2518 if (err)
2519 goto err_free;
2520
2521 for (int i = 0; i < priv->rxrings; i++) {
2522 priv->rx_qs[i].id = i;
2523 priv->rx_qs[i].priv = priv;
2524 netif_napi_add(dev, &priv->rx_qs[i].napi, rtl838x_poll_rx, 64);
2525 }
2526
2527 platform_set_drvdata(pdev, dev);
2528
2529 phy_mode = PHY_INTERFACE_MODE_NA;
2530 err = of_get_phy_mode(dn, &phy_mode);
2531 if (err < 0) {
2532 dev_err(&pdev->dev, "incorrect phy-mode\n");
2533 err = -EINVAL;
2534 goto err_free;
2535 }
2536 priv->phylink_config.dev = &dev->dev;
2537 priv->phylink_config.type = PHYLINK_NETDEV;
2538
2539 phylink = phylink_create(&priv->phylink_config, pdev->dev.fwnode,
2540 phy_mode, &rtl838x_phylink_ops);
2541
2542 if (IS_ERR(phylink)) {
2543 err = PTR_ERR(phylink);
2544 goto err_free;
2545 }
2546 priv->phylink = phylink;
2547
2548 return 0;
2549
2550 err_free:
2551 pr_err("Error setting up netdev, freeing it again.\n");
2552 free_netdev(dev);
2553
2554 return err;
2555 }
2556
2557 static int rtl838x_eth_remove(struct platform_device *pdev)
2558 {
2559 struct net_device *dev = platform_get_drvdata(pdev);
2560 struct rtl838x_eth_priv *priv = netdev_priv(dev);
2561
2562 if (dev) {
2563 pr_info("Removing platform driver for rtl838x-eth\n");
2564 rtl838x_mdio_remove(priv);
2565 rtl838x_hw_stop(priv);
2566
2567 netif_tx_stop_all_queues(dev);
2568
2569 for (int i = 0; i < priv->rxrings; i++)
2570 netif_napi_del(&priv->rx_qs[i].napi);
2571
2572 unregister_netdev(dev);
2573 free_netdev(dev);
2574 }
2575
2576 return 0;
2577 }
2578
2579 static const struct of_device_id rtl838x_eth_of_ids[] = {
2580 { .compatible = "realtek,rtl838x-eth"},
2581 { /* sentinel */ }
2582 };
2583 MODULE_DEVICE_TABLE(of, rtl838x_eth_of_ids);
2584
2585 static struct platform_driver rtl838x_eth_driver = {
2586 .probe = rtl838x_eth_probe,
2587 .remove = rtl838x_eth_remove,
2588 .driver = {
2589 .name = "rtl838x-eth",
2590 .pm = NULL,
2591 .of_match_table = rtl838x_eth_of_ids,
2592 },
2593 };
2594
2595 module_platform_driver(rtl838x_eth_driver);
2596
2597 MODULE_AUTHOR("B. Koblitz");
2598 MODULE_DESCRIPTION("RTL838X SoC Ethernet Driver");
2599 MODULE_LICENSE("GPL");
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