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mac80211: update to version 5.9.1
[openwrt/staging/nbd.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / mtk_eth_soc.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/init.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/platform_device.h>
24 #include <linux/of_device.h>
25 #include <linux/clk.h>
26 #include <linux/of_net.h>
27 #include <linux/of_mdio.h>
28 #include <linux/if_vlan.h>
29 #include <linux/reset.h>
30 #include <linux/tcp.h>
31 #include <linux/io.h>
32 #include <linux/bug.h>
33 #include <linux/netfilter.h>
34 #include <net/netfilter/nf_flow_table.h>
35 #include <linux/of_gpio.h>
36 #include <linux/gpio.h>
37 #include <linux/gpio/consumer.h>
38
39 #include <asm/mach-ralink/ralink_regs.h>
40
41 #include "mtk_eth_soc.h"
42 #include "mdio.h"
43 #include "ethtool.h"
44
45 #define MAX_RX_LENGTH 1536
46 #define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
47 #define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
48 #define DMA_DUMMY_DESC 0xffffffff
49 #define FE_DEFAULT_MSG_ENABLE \
50 (NETIF_MSG_DRV | \
51 NETIF_MSG_PROBE | \
52 NETIF_MSG_LINK | \
53 NETIF_MSG_TIMER | \
54 NETIF_MSG_IFDOWN | \
55 NETIF_MSG_IFUP | \
56 NETIF_MSG_RX_ERR | \
57 NETIF_MSG_TX_ERR)
58
59 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
60 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
61 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
62 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
63
64 static int fe_msg_level = -1;
65 module_param_named(msg_level, fe_msg_level, int, 0);
66 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
67
68 static const u16 fe_reg_table_default[FE_REG_COUNT] = {
69 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
70 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
71 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
72 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
73 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
74 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
75 [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
76 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
77 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
78 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
79 [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
80 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
81 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
82 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
83 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
84 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
85 };
86
87 static const u16 *fe_reg_table = fe_reg_table_default;
88
89 struct fe_work_t {
90 int bitnr;
91 void (*action)(struct fe_priv *);
92 };
93
94 static void __iomem *fe_base;
95
96 void fe_w32(u32 val, unsigned reg)
97 {
98 __raw_writel(val, fe_base + reg);
99 }
100
101 u32 fe_r32(unsigned reg)
102 {
103 return __raw_readl(fe_base + reg);
104 }
105
106 void fe_reg_w32(u32 val, enum fe_reg reg)
107 {
108 fe_w32(val, fe_reg_table[reg]);
109 }
110
111 u32 fe_reg_r32(enum fe_reg reg)
112 {
113 return fe_r32(fe_reg_table[reg]);
114 }
115
116 void fe_m32(struct fe_priv *eth, u32 clear, u32 set, unsigned reg)
117 {
118 u32 val;
119
120 spin_lock(&eth->page_lock);
121 val = __raw_readl(fe_base + reg);
122 val &= ~clear;
123 val |= set;
124 __raw_writel(val, fe_base + reg);
125 spin_unlock(&eth->page_lock);
126 }
127
128 static void fe_reset_fe(struct fe_priv *priv)
129 {
130 if (!priv->resets)
131 return;
132
133 reset_control_assert(priv->resets);
134 usleep_range(60, 120);
135 reset_control_deassert(priv->resets);
136 usleep_range(1000, 1200);
137 }
138
139 static inline void fe_int_disable(u32 mask)
140 {
141 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
142 FE_REG_FE_INT_ENABLE);
143 /* flush write */
144 fe_reg_r32(FE_REG_FE_INT_ENABLE);
145 }
146
147 static inline void fe_int_enable(u32 mask)
148 {
149 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
150 FE_REG_FE_INT_ENABLE);
151 /* flush write */
152 fe_reg_r32(FE_REG_FE_INT_ENABLE);
153 }
154
155 static inline void fe_hw_set_macaddr(struct fe_priv *priv, const unsigned char *mac)
156 {
157 unsigned long flags;
158
159 spin_lock_irqsave(&priv->page_lock, flags);
160 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
161 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
162 FE_GDMA1_MAC_ADRL);
163 spin_unlock_irqrestore(&priv->page_lock, flags);
164 }
165
166 static int fe_set_mac_address(struct net_device *dev, void *p)
167 {
168 int ret = eth_mac_addr(dev, p);
169
170 if (!ret) {
171 struct fe_priv *priv = netdev_priv(dev);
172
173 if (priv->soc->set_mac)
174 priv->soc->set_mac(priv, dev->dev_addr);
175 else
176 fe_hw_set_macaddr(priv, p);
177 }
178
179 return ret;
180 }
181
182 static inline int fe_max_frag_size(int mtu)
183 {
184 /* make sure buf_size will be at least MAX_RX_LENGTH */
185 if (mtu + FE_RX_ETH_HLEN < MAX_RX_LENGTH)
186 mtu = MAX_RX_LENGTH - FE_RX_ETH_HLEN;
187
188 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
189 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
190 }
191
192 static inline int fe_max_buf_size(int frag_size)
193 {
194 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
195 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
196
197 BUG_ON(buf_size < MAX_RX_LENGTH);
198 return buf_size;
199 }
200
201 static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
202 {
203 rxd->rxd1 = dma_rxd->rxd1;
204 rxd->rxd2 = dma_rxd->rxd2;
205 rxd->rxd3 = dma_rxd->rxd3;
206 rxd->rxd4 = dma_rxd->rxd4;
207 }
208
209 static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
210 {
211 dma_txd->txd1 = txd->txd1;
212 dma_txd->txd3 = txd->txd3;
213 dma_txd->txd4 = txd->txd4;
214 /* clean dma done flag last */
215 dma_txd->txd2 = txd->txd2;
216 }
217
218 static void fe_clean_rx(struct fe_priv *priv)
219 {
220 struct fe_rx_ring *ring = &priv->rx_ring;
221 struct page *page;
222 int i;
223
224 if (ring->rx_data) {
225 for (i = 0; i < ring->rx_ring_size; i++)
226 if (ring->rx_data[i]) {
227 if (ring->rx_dma && ring->rx_dma[i].rxd1)
228 dma_unmap_single(priv->dev,
229 ring->rx_dma[i].rxd1,
230 ring->rx_buf_size,
231 DMA_FROM_DEVICE);
232 skb_free_frag(ring->rx_data[i]);
233 }
234
235 kfree(ring->rx_data);
236 ring->rx_data = NULL;
237 }
238
239 if (ring->rx_dma) {
240 dma_free_coherent(priv->dev,
241 ring->rx_ring_size * sizeof(*ring->rx_dma),
242 ring->rx_dma,
243 ring->rx_phys);
244 ring->rx_dma = NULL;
245 }
246
247 if (!ring->frag_cache.va)
248 return;
249
250 page = virt_to_page(ring->frag_cache.va);
251 __page_frag_cache_drain(page, ring->frag_cache.pagecnt_bias);
252 memset(&ring->frag_cache, 0, sizeof(ring->frag_cache));
253 }
254
255 static int fe_alloc_rx(struct fe_priv *priv)
256 {
257 struct fe_rx_ring *ring = &priv->rx_ring;
258 int i, pad;
259
260 ring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data),
261 GFP_KERNEL);
262 if (!ring->rx_data)
263 goto no_rx_mem;
264
265 for (i = 0; i < ring->rx_ring_size; i++) {
266 ring->rx_data[i] = page_frag_alloc(&ring->frag_cache,
267 ring->frag_size,
268 GFP_KERNEL);
269 if (!ring->rx_data[i])
270 goto no_rx_mem;
271 }
272
273 ring->rx_dma = dma_alloc_coherent(priv->dev,
274 ring->rx_ring_size * sizeof(*ring->rx_dma),
275 &ring->rx_phys,
276 GFP_ATOMIC | __GFP_ZERO);
277 if (!ring->rx_dma)
278 goto no_rx_mem;
279
280 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
281 pad = 0;
282 else
283 pad = NET_IP_ALIGN;
284 for (i = 0; i < ring->rx_ring_size; i++) {
285 dma_addr_t dma_addr = dma_map_single(priv->dev,
286 ring->rx_data[i] + NET_SKB_PAD + pad,
287 ring->rx_buf_size,
288 DMA_FROM_DEVICE);
289 if (unlikely(dma_mapping_error(priv->dev, dma_addr)))
290 goto no_rx_mem;
291 ring->rx_dma[i].rxd1 = (unsigned int)dma_addr;
292
293 if (priv->flags & FE_FLAG_RX_SG_DMA)
294 ring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
295 else
296 ring->rx_dma[i].rxd2 = RX_DMA_LSO;
297 }
298 ring->rx_calc_idx = ring->rx_ring_size - 1;
299 /* make sure that all changes to the dma ring are flushed before we
300 * continue
301 */
302 wmb();
303
304 fe_reg_w32(ring->rx_phys, FE_REG_RX_BASE_PTR0);
305 fe_reg_w32(ring->rx_ring_size, FE_REG_RX_MAX_CNT0);
306 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
307 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
308
309 return 0;
310
311 no_rx_mem:
312 return -ENOMEM;
313 }
314
315 static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)
316 {
317 if (dma_unmap_len(tx_buf, dma_len0))
318 dma_unmap_page(dev,
319 dma_unmap_addr(tx_buf, dma_addr0),
320 dma_unmap_len(tx_buf, dma_len0),
321 DMA_TO_DEVICE);
322
323 if (dma_unmap_len(tx_buf, dma_len1))
324 dma_unmap_page(dev,
325 dma_unmap_addr(tx_buf, dma_addr1),
326 dma_unmap_len(tx_buf, dma_len1),
327 DMA_TO_DEVICE);
328
329 dma_unmap_len_set(tx_buf, dma_addr0, 0);
330 dma_unmap_len_set(tx_buf, dma_addr1, 0);
331 if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *)DMA_DUMMY_DESC))
332 dev_kfree_skb_any(tx_buf->skb);
333 tx_buf->skb = NULL;
334 }
335
336 static void fe_clean_tx(struct fe_priv *priv)
337 {
338 int i;
339 struct device *dev = priv->dev;
340 struct fe_tx_ring *ring = &priv->tx_ring;
341
342 if (ring->tx_buf) {
343 for (i = 0; i < ring->tx_ring_size; i++)
344 fe_txd_unmap(dev, &ring->tx_buf[i]);
345 kfree(ring->tx_buf);
346 ring->tx_buf = NULL;
347 }
348
349 if (ring->tx_dma) {
350 dma_free_coherent(dev,
351 ring->tx_ring_size * sizeof(*ring->tx_dma),
352 ring->tx_dma,
353 ring->tx_phys);
354 ring->tx_dma = NULL;
355 }
356
357 netdev_reset_queue(priv->netdev);
358 }
359
360 static int fe_alloc_tx(struct fe_priv *priv)
361 {
362 int i;
363 struct fe_tx_ring *ring = &priv->tx_ring;
364
365 ring->tx_free_idx = 0;
366 ring->tx_next_idx = 0;
367 ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2,
368 MAX_SKB_FRAGS);
369
370 ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
371 GFP_KERNEL);
372 if (!ring->tx_buf)
373 goto no_tx_mem;
374
375 ring->tx_dma = dma_alloc_coherent(priv->dev,
376 ring->tx_ring_size * sizeof(*ring->tx_dma),
377 &ring->tx_phys,
378 GFP_ATOMIC | __GFP_ZERO);
379 if (!ring->tx_dma)
380 goto no_tx_mem;
381
382 for (i = 0; i < ring->tx_ring_size; i++) {
383 if (priv->soc->tx_dma)
384 priv->soc->tx_dma(&ring->tx_dma[i]);
385 ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
386 }
387 /* make sure that all changes to the dma ring are flushed before we
388 * continue
389 */
390 wmb();
391
392 fe_reg_w32(ring->tx_phys, FE_REG_TX_BASE_PTR0);
393 fe_reg_w32(ring->tx_ring_size, FE_REG_TX_MAX_CNT0);
394 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
395 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
396
397 return 0;
398
399 no_tx_mem:
400 return -ENOMEM;
401 }
402
403 static int fe_init_dma(struct fe_priv *priv)
404 {
405 int err;
406
407 err = fe_alloc_tx(priv);
408 if (err)
409 return err;
410
411 err = fe_alloc_rx(priv);
412 if (err)
413 return err;
414
415 return 0;
416 }
417
418 static void fe_free_dma(struct fe_priv *priv)
419 {
420 fe_clean_tx(priv);
421 fe_clean_rx(priv);
422 }
423
424 void fe_stats_update(struct fe_priv *priv)
425 {
426 struct fe_hw_stats *hwstats = priv->hw_stats;
427 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
428 u64 stats;
429
430 u64_stats_update_begin(&hwstats->syncp);
431
432 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
433 hwstats->rx_bytes += fe_r32(base);
434 stats = fe_r32(base + 0x04);
435 if (stats)
436 hwstats->rx_bytes += (stats << 32);
437 hwstats->rx_packets += fe_r32(base + 0x08);
438 hwstats->rx_overflow += fe_r32(base + 0x10);
439 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
440 hwstats->rx_short_errors += fe_r32(base + 0x18);
441 hwstats->rx_long_errors += fe_r32(base + 0x1c);
442 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
443 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
444 hwstats->tx_skip += fe_r32(base + 0x28);
445 hwstats->tx_collisions += fe_r32(base + 0x2c);
446 hwstats->tx_bytes += fe_r32(base + 0x30);
447 stats = fe_r32(base + 0x34);
448 if (stats)
449 hwstats->tx_bytes += (stats << 32);
450 hwstats->tx_packets += fe_r32(base + 0x38);
451 } else {
452 hwstats->tx_bytes += fe_r32(base);
453 hwstats->tx_packets += fe_r32(base + 0x04);
454 hwstats->tx_skip += fe_r32(base + 0x08);
455 hwstats->tx_collisions += fe_r32(base + 0x0c);
456 hwstats->rx_bytes += fe_r32(base + 0x20);
457 hwstats->rx_packets += fe_r32(base + 0x24);
458 hwstats->rx_overflow += fe_r32(base + 0x28);
459 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
460 hwstats->rx_short_errors += fe_r32(base + 0x30);
461 hwstats->rx_long_errors += fe_r32(base + 0x34);
462 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
463 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
464 }
465
466 u64_stats_update_end(&hwstats->syncp);
467 }
468
469 static void fe_get_stats64(struct net_device *dev,
470 struct rtnl_link_stats64 *storage)
471 {
472 struct fe_priv *priv = netdev_priv(dev);
473 struct fe_hw_stats *hwstats = priv->hw_stats;
474 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
475 unsigned int start;
476
477 if (!base) {
478 netdev_stats_to_stats64(storage, &dev->stats);
479 return;
480 }
481
482 if (netif_running(dev) && netif_device_present(dev)) {
483 if (spin_trylock_bh(&hwstats->stats_lock)) {
484 fe_stats_update(priv);
485 spin_unlock_bh(&hwstats->stats_lock);
486 }
487 }
488
489 do {
490 start = u64_stats_fetch_begin(&hwstats->syncp);
491 storage->rx_packets = hwstats->rx_packets;
492 storage->tx_packets = hwstats->tx_packets;
493 storage->rx_bytes = hwstats->rx_bytes;
494 storage->tx_bytes = hwstats->tx_bytes;
495 storage->collisions = hwstats->tx_collisions;
496 storage->rx_length_errors = hwstats->rx_short_errors +
497 hwstats->rx_long_errors;
498 storage->rx_over_errors = hwstats->rx_overflow;
499 storage->rx_crc_errors = hwstats->rx_fcs_errors;
500 storage->rx_errors = hwstats->rx_checksum_errors;
501 storage->tx_aborted_errors = hwstats->tx_skip;
502 } while (u64_stats_fetch_retry(&hwstats->syncp, start));
503
504 storage->tx_errors = priv->netdev->stats.tx_errors;
505 storage->rx_dropped = priv->netdev->stats.rx_dropped;
506 storage->tx_dropped = priv->netdev->stats.tx_dropped;
507 }
508
509 static int fe_vlan_rx_add_vid(struct net_device *dev,
510 __be16 proto, u16 vid)
511 {
512 struct fe_priv *priv = netdev_priv(dev);
513 u32 idx = (vid & 0xf);
514 u32 vlan_cfg;
515
516 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
517 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
518 return 0;
519
520 if (test_bit(idx, &priv->vlan_map)) {
521 netdev_warn(dev, "disable tx vlan offload\n");
522 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
523 netdev_update_features(dev);
524 } else {
525 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
526 ((idx >> 1) << 2));
527 if (idx & 0x1) {
528 vlan_cfg &= 0xffff;
529 vlan_cfg |= (vid << 16);
530 } else {
531 vlan_cfg &= 0xffff0000;
532 vlan_cfg |= vid;
533 }
534 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
535 ((idx >> 1) << 2));
536 set_bit(idx, &priv->vlan_map);
537 }
538
539 return 0;
540 }
541
542 static int fe_vlan_rx_kill_vid(struct net_device *dev,
543 __be16 proto, u16 vid)
544 {
545 struct fe_priv *priv = netdev_priv(dev);
546 u32 idx = (vid & 0xf);
547
548 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
549 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
550 return 0;
551
552 clear_bit(idx, &priv->vlan_map);
553
554 return 0;
555 }
556
557 static inline u32 fe_empty_txd(struct fe_tx_ring *ring)
558 {
559 barrier();
560 return (u32)(ring->tx_ring_size -
561 ((ring->tx_next_idx - ring->tx_free_idx) &
562 (ring->tx_ring_size - 1)));
563 }
564
565 struct fe_map_state {
566 struct device *dev;
567 struct fe_tx_dma txd;
568 u32 def_txd4;
569 int ring_idx;
570 int i;
571 };
572
573 static void fe_tx_dma_write_desc(struct fe_tx_ring *ring, struct fe_map_state *st)
574 {
575 fe_set_txd(&st->txd, &ring->tx_dma[st->ring_idx]);
576 memset(&st->txd, 0, sizeof(st->txd));
577 st->txd.txd4 = st->def_txd4;
578 st->ring_idx = NEXT_TX_DESP_IDX(st->ring_idx);
579 }
580
581 static int __fe_tx_dma_map_page(struct fe_tx_ring *ring, struct fe_map_state *st,
582 struct page *page, size_t offset, size_t size)
583 {
584 struct device *dev = st->dev;
585 struct fe_tx_buf *tx_buf;
586 dma_addr_t mapped_addr;
587
588 mapped_addr = dma_map_page(dev, page, offset, size, DMA_TO_DEVICE);
589 if (unlikely(dma_mapping_error(dev, mapped_addr)))
590 return -EIO;
591
592 if (st->i && !(st->i & 1))
593 fe_tx_dma_write_desc(ring, st);
594
595 tx_buf = &ring->tx_buf[st->ring_idx];
596 if (st->i & 1) {
597 st->txd.txd3 = mapped_addr;
598 st->txd.txd2 |= TX_DMA_PLEN1(size);
599 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
600 dma_unmap_len_set(tx_buf, dma_len1, size);
601 } else {
602 tx_buf->skb = (struct sk_buff *)DMA_DUMMY_DESC;
603 st->txd.txd1 = mapped_addr;
604 st->txd.txd2 = TX_DMA_PLEN0(size);
605 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
606 dma_unmap_len_set(tx_buf, dma_len0, size);
607 }
608 st->i++;
609
610 return 0;
611 }
612
613 static int fe_tx_dma_map_page(struct fe_tx_ring *ring, struct fe_map_state *st,
614 struct page *page, size_t offset, size_t size)
615 {
616 int cur_size;
617 int ret;
618
619 while (size > 0) {
620 cur_size = min_t(size_t, size, TX_DMA_BUF_LEN);
621
622 ret = __fe_tx_dma_map_page(ring, st, page, offset, cur_size);
623 if (ret)
624 return ret;
625
626 size -= cur_size;
627 offset += cur_size;
628 }
629
630 return 0;
631 }
632
633 static int fe_tx_dma_map_skb(struct fe_tx_ring *ring, struct fe_map_state *st,
634 struct sk_buff *skb)
635 {
636 struct page *page = virt_to_page(skb->data);
637 size_t offset = offset_in_page(skb->data);
638 size_t size = skb_headlen(skb);
639
640 return fe_tx_dma_map_page(ring, st, page, offset, size);
641 }
642
643 static inline struct sk_buff *
644 fe_next_frag(struct sk_buff *head, struct sk_buff *skb)
645 {
646 if (skb != head)
647 return skb->next;
648
649 if (skb_has_frag_list(skb))
650 return skb_shinfo(skb)->frag_list;
651
652 return NULL;
653 }
654
655
656 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
657 int tx_num, struct fe_tx_ring *ring)
658 {
659 struct fe_priv *priv = netdev_priv(dev);
660 struct fe_map_state st = {
661 .dev = priv->dev,
662 .ring_idx = ring->tx_next_idx,
663 };
664 struct sk_buff *head = skb;
665 struct fe_tx_buf *tx_buf;
666 unsigned int nr_frags;
667 int i, j;
668
669 /* init tx descriptor */
670 if (priv->soc->tx_dma)
671 priv->soc->tx_dma(&st.txd);
672 else
673 st.txd.txd4 = TX_DMA_DESP4_DEF;
674 st.def_txd4 = st.txd.txd4;
675
676 /* TX Checksum offload */
677 if (skb->ip_summed == CHECKSUM_PARTIAL)
678 st.txd.txd4 |= TX_DMA_CHKSUM;
679
680 /* VLAN header offload */
681 if (skb_vlan_tag_present(skb)) {
682 u16 tag = skb_vlan_tag_get(skb);
683
684 if (IS_ENABLED(CONFIG_SOC_MT7621))
685 st.txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | tag;
686 else
687 st.txd.txd4 |= TX_DMA_INS_VLAN |
688 ((tag >> VLAN_PRIO_SHIFT) << 4) |
689 (tag & 0xF);
690 }
691
692 /* TSO: fill MSS info in tcp checksum field */
693 if (skb_is_gso(skb)) {
694 if (skb_cow_head(skb, 0)) {
695 netif_warn(priv, tx_err, dev,
696 "GSO expand head fail.\n");
697 goto err_out;
698 }
699 if (skb_shinfo(skb)->gso_type &
700 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
701 st.txd.txd4 |= TX_DMA_TSO;
702 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
703 }
704 }
705
706 next_frag:
707 if (skb_headlen(skb) && fe_tx_dma_map_skb(ring, &st, skb))
708 goto err_dma;
709
710 /* TX SG offload */
711 nr_frags = skb_shinfo(skb)->nr_frags;
712 for (i = 0; i < nr_frags; i++) {
713 skb_frag_t *frag;
714
715 frag = &skb_shinfo(skb)->frags[i];
716 if (fe_tx_dma_map_page(ring, &st, skb_frag_page(frag),
717 skb_frag_off(frag), skb_frag_size(frag)))
718 goto err_dma;
719 }
720
721 skb = fe_next_frag(head, skb);
722 if (skb)
723 goto next_frag;
724
725 /* set last segment */
726 if (st.i & 0x1)
727 st.txd.txd2 |= TX_DMA_LS0;
728 else
729 st.txd.txd2 |= TX_DMA_LS1;
730
731 /* store skb to cleanup */
732 tx_buf = &ring->tx_buf[st.ring_idx];
733 tx_buf->skb = head;
734
735 netdev_sent_queue(dev, head->len);
736 skb_tx_timestamp(head);
737
738 fe_tx_dma_write_desc(ring, &st);
739 ring->tx_next_idx = st.ring_idx;
740
741 /* make sure that all changes to the dma ring are flushed before we
742 * continue
743 */
744 wmb();
745 if (unlikely(fe_empty_txd(ring) <= ring->tx_thresh)) {
746 netif_stop_queue(dev);
747 smp_mb();
748 if (unlikely(fe_empty_txd(ring) > ring->tx_thresh))
749 netif_wake_queue(dev);
750 }
751
752 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !netdev_xmit_more())
753 fe_reg_w32(ring->tx_next_idx, FE_REG_TX_CTX_IDX0);
754
755 return 0;
756
757 err_dma:
758 j = ring->tx_next_idx;
759 for (i = 0; i < tx_num; i++) {
760 /* unmap dma */
761 fe_txd_unmap(priv->dev, &ring->tx_buf[j]);
762 ring->tx_dma[j].txd2 = TX_DMA_DESP2_DEF;
763
764 j = NEXT_TX_DESP_IDX(j);
765 }
766 /* make sure that all changes to the dma ring are flushed before we
767 * continue
768 */
769 wmb();
770
771 err_out:
772 return -1;
773 }
774
775 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv)
776 {
777 unsigned int len;
778 int ret;
779
780 ret = 0;
781 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
782 if ((priv->flags & FE_FLAG_PADDING_64B) &&
783 !(priv->flags & FE_FLAG_PADDING_BUG))
784 return ret;
785
786 if (skb_vlan_tag_present(skb))
787 len = ETH_ZLEN;
788 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
789 len = VLAN_ETH_ZLEN;
790 else if (!(priv->flags & FE_FLAG_PADDING_64B))
791 len = ETH_ZLEN;
792 else
793 return ret;
794
795 if (skb->len < len) {
796 ret = skb_pad(skb, len - skb->len);
797 if (ret < 0)
798 return ret;
799 skb->len = len;
800 skb_set_tail_pointer(skb, len);
801 }
802 }
803
804 return ret;
805 }
806
807 static inline int fe_cal_txd_req(struct sk_buff *skb)
808 {
809 struct sk_buff *head = skb;
810 int i, nfrags = 0;
811 skb_frag_t *frag;
812
813 next_frag:
814 nfrags++;
815 if (skb_is_gso(skb)) {
816 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
817 frag = &skb_shinfo(skb)->frags[i];
818 nfrags += DIV_ROUND_UP(skb_frag_size(frag), TX_DMA_BUF_LEN);
819 }
820 } else {
821 nfrags += skb_shinfo(skb)->nr_frags;
822 }
823
824 skb = fe_next_frag(head, skb);
825 if (skb)
826 goto next_frag;
827
828 return DIV_ROUND_UP(nfrags, 2);
829 }
830
831 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
832 {
833 struct fe_priv *priv = netdev_priv(dev);
834 struct fe_tx_ring *ring = &priv->tx_ring;
835 struct net_device_stats *stats = &dev->stats;
836 int tx_num;
837 int len = skb->len;
838
839 if (fe_skb_padto(skb, priv)) {
840 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
841 return NETDEV_TX_OK;
842 }
843
844 tx_num = fe_cal_txd_req(skb);
845 if (unlikely(fe_empty_txd(ring) <= tx_num)) {
846 netif_stop_queue(dev);
847 netif_err(priv, tx_queued, dev,
848 "Tx Ring full when queue awake!\n");
849 return NETDEV_TX_BUSY;
850 }
851
852 if (fe_tx_map_dma(skb, dev, tx_num, ring) < 0) {
853 stats->tx_dropped++;
854 } else {
855 stats->tx_packets++;
856 stats->tx_bytes += len;
857 }
858
859 return NETDEV_TX_OK;
860 }
861
862 static int fe_poll_rx(struct napi_struct *napi, int budget,
863 struct fe_priv *priv, u32 rx_intr)
864 {
865 struct net_device *netdev = priv->netdev;
866 struct net_device_stats *stats = &netdev->stats;
867 struct fe_soc_data *soc = priv->soc;
868 struct fe_rx_ring *ring = &priv->rx_ring;
869 int idx = ring->rx_calc_idx;
870 u32 checksum_bit;
871 struct sk_buff *skb;
872 u8 *data, *new_data;
873 struct fe_rx_dma *rxd, trxd;
874 int done = 0, pad;
875
876 if (netdev->features & NETIF_F_RXCSUM)
877 checksum_bit = soc->checksum_bit;
878 else
879 checksum_bit = 0;
880
881 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
882 pad = 0;
883 else
884 pad = NET_IP_ALIGN;
885
886 while (done < budget) {
887 unsigned int pktlen;
888 dma_addr_t dma_addr;
889
890 idx = NEXT_RX_DESP_IDX(idx);
891 rxd = &ring->rx_dma[idx];
892 data = ring->rx_data[idx];
893
894 fe_get_rxd(&trxd, rxd);
895 if (!(trxd.rxd2 & RX_DMA_DONE))
896 break;
897
898 /* alloc new buffer */
899 new_data = page_frag_alloc(&ring->frag_cache, ring->frag_size,
900 GFP_ATOMIC);
901 if (unlikely(!new_data)) {
902 stats->rx_dropped++;
903 goto release_desc;
904 }
905 dma_addr = dma_map_single(priv->dev,
906 new_data + NET_SKB_PAD + pad,
907 ring->rx_buf_size,
908 DMA_FROM_DEVICE);
909 if (unlikely(dma_mapping_error(priv->dev, dma_addr))) {
910 skb_free_frag(new_data);
911 goto release_desc;
912 }
913
914 /* receive data */
915 skb = build_skb(data, ring->frag_size);
916 if (unlikely(!skb)) {
917 skb_free_frag(new_data);
918 goto release_desc;
919 }
920 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
921
922 dma_unmap_single(priv->dev, trxd.rxd1,
923 ring->rx_buf_size, DMA_FROM_DEVICE);
924 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
925 skb->dev = netdev;
926 skb_put(skb, pktlen);
927 if (trxd.rxd4 & checksum_bit)
928 skb->ip_summed = CHECKSUM_UNNECESSARY;
929 else
930 skb_checksum_none_assert(skb);
931 skb->protocol = eth_type_trans(skb, netdev);
932
933 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
934 RX_DMA_VID(trxd.rxd3))
935 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
936 RX_DMA_VID(trxd.rxd3));
937
938 stats->rx_packets++;
939 stats->rx_bytes += pktlen;
940
941 napi_gro_receive(napi, skb);
942
943 ring->rx_data[idx] = new_data;
944 rxd->rxd1 = (unsigned int)dma_addr;
945
946 release_desc:
947 if (priv->flags & FE_FLAG_RX_SG_DMA)
948 rxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
949 else
950 rxd->rxd2 = RX_DMA_LSO;
951
952 ring->rx_calc_idx = idx;
953 /* make sure that all changes to the dma ring are flushed before
954 * we continue
955 */
956 wmb();
957 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
958 done++;
959 }
960
961 if (done < budget)
962 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
963
964 return done;
965 }
966
967 static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr,
968 int *tx_again)
969 {
970 struct net_device *netdev = priv->netdev;
971 unsigned int bytes_compl = 0;
972 struct sk_buff *skb;
973 struct fe_tx_buf *tx_buf;
974 int done = 0;
975 u32 idx, hwidx;
976 struct fe_tx_ring *ring = &priv->tx_ring;
977
978 idx = ring->tx_free_idx;
979 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
980
981 while ((idx != hwidx) && budget) {
982 tx_buf = &ring->tx_buf[idx];
983 skb = tx_buf->skb;
984
985 if (!skb)
986 break;
987
988 if (skb != (struct sk_buff *)DMA_DUMMY_DESC) {
989 bytes_compl += skb->len;
990 done++;
991 budget--;
992 }
993 fe_txd_unmap(priv->dev, tx_buf);
994 idx = NEXT_TX_DESP_IDX(idx);
995 }
996 ring->tx_free_idx = idx;
997
998 if (idx == hwidx) {
999 /* read hw index again make sure no new tx packet */
1000 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
1001 if (idx == hwidx)
1002 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
1003 else
1004 *tx_again = 1;
1005 } else {
1006 *tx_again = 1;
1007 }
1008
1009 if (done) {
1010 netdev_completed_queue(netdev, done, bytes_compl);
1011 smp_mb();
1012 if (unlikely(netif_queue_stopped(netdev) &&
1013 (fe_empty_txd(ring) > ring->tx_thresh)))
1014 netif_wake_queue(netdev);
1015 }
1016
1017 return done;
1018 }
1019
1020 static int fe_poll(struct napi_struct *napi, int budget)
1021 {
1022 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
1023 struct fe_hw_stats *hwstat = priv->hw_stats;
1024 int tx_done, rx_done, tx_again;
1025 u32 status, fe_status, status_reg, mask;
1026 u32 tx_intr, rx_intr, status_intr;
1027
1028 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1029 fe_status = status;
1030 tx_intr = priv->soc->tx_int;
1031 rx_intr = priv->soc->rx_int;
1032 status_intr = priv->soc->status_int;
1033 tx_done = 0;
1034 rx_done = 0;
1035 tx_again = 0;
1036
1037 if (fe_reg_table[FE_REG_FE_INT_STATUS2]) {
1038 fe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2);
1039 status_reg = FE_REG_FE_INT_STATUS2;
1040 } else {
1041 status_reg = FE_REG_FE_INT_STATUS;
1042 }
1043
1044 if (status & tx_intr)
1045 tx_done = fe_poll_tx(priv, budget, tx_intr, &tx_again);
1046
1047 if (status & rx_intr)
1048 rx_done = fe_poll_rx(napi, budget, priv, rx_intr);
1049
1050 if (unlikely(fe_status & status_intr)) {
1051 if (hwstat && spin_trylock(&hwstat->stats_lock)) {
1052 fe_stats_update(priv);
1053 spin_unlock(&hwstat->stats_lock);
1054 }
1055 fe_reg_w32(status_intr, status_reg);
1056 }
1057
1058 if (unlikely(netif_msg_intr(priv))) {
1059 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
1060 netdev_info(priv->netdev,
1061 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
1062 tx_done, rx_done, status, mask);
1063 }
1064
1065 if (!tx_again && (rx_done < budget)) {
1066 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1067 if (status & (tx_intr | rx_intr)) {
1068 /* let napi poll again */
1069 rx_done = budget;
1070 goto poll_again;
1071 }
1072
1073 napi_complete_done(napi, rx_done);
1074 fe_int_enable(tx_intr | rx_intr);
1075 } else {
1076 rx_done = budget;
1077 }
1078
1079 poll_again:
1080 return rx_done;
1081 }
1082
1083 static void fe_tx_timeout(struct net_device *dev, unsigned int txqueue)
1084 {
1085 struct fe_priv *priv = netdev_priv(dev);
1086 struct fe_tx_ring *ring = &priv->tx_ring;
1087
1088 priv->netdev->stats.tx_errors++;
1089 netif_err(priv, tx_err, dev,
1090 "transmit timed out\n");
1091 netif_info(priv, drv, dev, "dma_cfg:%08x\n",
1092 fe_reg_r32(FE_REG_PDMA_GLO_CFG));
1093 netif_info(priv, drv, dev, "tx_ring=%d, "
1094 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
1095 0, fe_reg_r32(FE_REG_TX_BASE_PTR0),
1096 fe_reg_r32(FE_REG_TX_MAX_CNT0),
1097 fe_reg_r32(FE_REG_TX_CTX_IDX0),
1098 fe_reg_r32(FE_REG_TX_DTX_IDX0),
1099 ring->tx_free_idx,
1100 ring->tx_next_idx);
1101 netif_info(priv, drv, dev,
1102 "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
1103 0, fe_reg_r32(FE_REG_RX_BASE_PTR0),
1104 fe_reg_r32(FE_REG_RX_MAX_CNT0),
1105 fe_reg_r32(FE_REG_RX_CALC_IDX0),
1106 fe_reg_r32(FE_REG_RX_DRX_IDX0));
1107
1108 if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
1109 schedule_work(&priv->pending_work);
1110 }
1111
1112 static irqreturn_t fe_handle_irq(int irq, void *dev)
1113 {
1114 struct fe_priv *priv = netdev_priv(dev);
1115 u32 status, int_mask;
1116
1117 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1118
1119 if (unlikely(!status))
1120 return IRQ_NONE;
1121
1122 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
1123 if (likely(status & int_mask)) {
1124 if (likely(napi_schedule_prep(&priv->rx_napi))) {
1125 fe_int_disable(int_mask);
1126 __napi_schedule(&priv->rx_napi);
1127 }
1128 } else {
1129 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
1130 }
1131
1132 return IRQ_HANDLED;
1133 }
1134
1135 #ifdef CONFIG_NET_POLL_CONTROLLER
1136 static void fe_poll_controller(struct net_device *dev)
1137 {
1138 struct fe_priv *priv = netdev_priv(dev);
1139 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
1140
1141 fe_int_disable(int_mask);
1142 fe_handle_irq(dev->irq, dev);
1143 fe_int_enable(int_mask);
1144 }
1145 #endif
1146
1147 int fe_set_clock_cycle(struct fe_priv *priv)
1148 {
1149 unsigned long sysclk = priv->sysclk;
1150
1151 sysclk /= FE_US_CYC_CNT_DIVISOR;
1152 sysclk <<= FE_US_CYC_CNT_SHIFT;
1153
1154 fe_w32((fe_r32(FE_FE_GLO_CFG) &
1155 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
1156 sysclk,
1157 FE_FE_GLO_CFG);
1158 return 0;
1159 }
1160
1161 void fe_fwd_config(struct fe_priv *priv)
1162 {
1163 u32 fwd_cfg;
1164
1165 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1166
1167 /* disable jumbo frame */
1168 if (priv->flags & FE_FLAG_JUMBO_FRAME)
1169 fwd_cfg &= ~FE_GDM1_JMB_EN;
1170
1171 /* set unicast/multicast/broadcast frame to cpu */
1172 fwd_cfg &= ~0xffff;
1173
1174 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1175 }
1176
1177 static void fe_rxcsum_config(bool enable)
1178 {
1179 if (enable)
1180 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1181 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1182 FE_GDMA1_FWD_CFG);
1183 else
1184 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1185 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1186 FE_GDMA1_FWD_CFG);
1187 }
1188
1189 static void fe_txcsum_config(bool enable)
1190 {
1191 if (enable)
1192 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1193 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1194 FE_CDMA_CSG_CFG);
1195 else
1196 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1197 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1198 FE_CDMA_CSG_CFG);
1199 }
1200
1201 void fe_csum_config(struct fe_priv *priv)
1202 {
1203 struct net_device *dev = priv_netdev(priv);
1204
1205 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1206 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1207 }
1208
1209 static int fe_hw_init(struct net_device *dev)
1210 {
1211 struct fe_priv *priv = netdev_priv(dev);
1212 int i, err;
1213
1214 err = devm_request_irq(priv->dev, dev->irq, fe_handle_irq, 0,
1215 dev_name(priv->dev), dev);
1216 if (err)
1217 return err;
1218
1219 if (priv->soc->set_mac)
1220 priv->soc->set_mac(priv, dev->dev_addr);
1221 else
1222 fe_hw_set_macaddr(priv, dev->dev_addr);
1223
1224 /* disable delay interrupt */
1225 fe_reg_w32(0, FE_REG_DLY_INT_CFG);
1226
1227 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1228
1229 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc */
1230 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1231 for (i = 0; i < 16; i += 2)
1232 fe_w32(((i + 1) << 16) + i,
1233 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1234 (i * 2));
1235
1236 if (priv->soc->fwd_config(priv))
1237 netdev_err(dev, "unable to get clock\n");
1238
1239 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1240 fe_reg_w32(1, FE_REG_FE_RST_GL);
1241 fe_reg_w32(0, FE_REG_FE_RST_GL);
1242 }
1243
1244 return 0;
1245 }
1246
1247 static int fe_open(struct net_device *dev)
1248 {
1249 struct fe_priv *priv = netdev_priv(dev);
1250 unsigned long flags;
1251 u32 val;
1252 int err;
1253
1254 err = fe_init_dma(priv);
1255 if (err) {
1256 fe_free_dma(priv);
1257 return err;
1258 }
1259
1260 spin_lock_irqsave(&priv->page_lock, flags);
1261
1262 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1263 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
1264 val |= FE_RX_2B_OFFSET;
1265 val |= priv->soc->pdma_glo_cfg;
1266 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1267
1268 spin_unlock_irqrestore(&priv->page_lock, flags);
1269
1270 if (priv->phy)
1271 priv->phy->start(priv);
1272
1273 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1274 netif_carrier_on(dev);
1275
1276 napi_enable(&priv->rx_napi);
1277 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1278 netif_start_queue(dev);
1279
1280 return 0;
1281 }
1282
1283 static int fe_stop(struct net_device *dev)
1284 {
1285 struct fe_priv *priv = netdev_priv(dev);
1286 unsigned long flags;
1287 int i;
1288
1289 netif_tx_disable(dev);
1290 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1291 napi_disable(&priv->rx_napi);
1292
1293 if (priv->phy)
1294 priv->phy->stop(priv);
1295
1296 spin_lock_irqsave(&priv->page_lock, flags);
1297
1298 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1299 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1300 FE_REG_PDMA_GLO_CFG);
1301 spin_unlock_irqrestore(&priv->page_lock, flags);
1302
1303 /* wait dma stop */
1304 for (i = 0; i < 10; i++) {
1305 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1306 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1307 msleep(20);
1308 continue;
1309 }
1310 break;
1311 }
1312
1313 fe_free_dma(priv);
1314
1315 return 0;
1316 }
1317
1318 static void fe_reset_phy(struct fe_priv *priv)
1319 {
1320 int err, msec = 30;
1321 struct gpio_desc *phy_reset;
1322
1323 phy_reset = devm_gpiod_get_optional(priv->dev, "phy-reset",
1324 GPIOD_OUT_HIGH);
1325 if (!phy_reset)
1326 return;
1327
1328 if (IS_ERR(phy_reset)) {
1329 dev_err(priv->dev, "Error acquiring reset gpio pins: %ld\n",
1330 PTR_ERR(phy_reset));
1331 return;
1332 }
1333
1334 err = of_property_read_u32(priv->dev->of_node, "phy-reset-duration",
1335 &msec);
1336 if (!err && msec > 1000)
1337 msec = 30;
1338
1339 if (msec > 20)
1340 msleep(msec);
1341 else
1342 usleep_range(msec * 1000, msec * 1000 + 1000);
1343
1344 gpiod_set_value(phy_reset, 0);
1345 }
1346
1347 static int __init fe_init(struct net_device *dev)
1348 {
1349 struct fe_priv *priv = netdev_priv(dev);
1350 struct device_node *port;
1351 int err;
1352
1353 fe_reset_fe(priv);
1354
1355 if (priv->soc->switch_init) {
1356 err = priv->soc->switch_init(priv);
1357 if (err) {
1358 if (err == -EPROBE_DEFER)
1359 return err;
1360
1361 netdev_err(dev, "failed to initialize switch core\n");
1362 return -ENODEV;
1363 }
1364 }
1365
1366 fe_reset_phy(priv);
1367
1368 /* Set the MAC address if it is correct, if not use a random MAC address */
1369 if (of_get_ethdev_address(priv->dev->of_node, dev)) {
1370 eth_hw_addr_random(dev);
1371 dev_err(priv->dev, "generated random MAC address %pM\n",
1372 dev->dev_addr);
1373 }
1374
1375 err = fe_mdio_init(priv);
1376 if (err)
1377 return err;
1378
1379 if (priv->soc->port_init)
1380 for_each_child_of_node(priv->dev->of_node, port)
1381 if (of_device_is_compatible(port, "mediatek,eth-port") &&
1382 of_device_is_available(port))
1383 priv->soc->port_init(priv, port);
1384
1385 if (priv->phy) {
1386 err = priv->phy->connect(priv);
1387 if (err)
1388 goto err_phy_disconnect;
1389 }
1390
1391 err = fe_hw_init(dev);
1392 if (err)
1393 goto err_phy_disconnect;
1394
1395 if ((priv->flags & FE_FLAG_HAS_SWITCH) && priv->soc->switch_config)
1396 priv->soc->switch_config(priv);
1397
1398 return 0;
1399
1400 err_phy_disconnect:
1401 if (priv->phy)
1402 priv->phy->disconnect(priv);
1403 fe_mdio_cleanup(priv);
1404
1405 return err;
1406 }
1407
1408 static void fe_uninit(struct net_device *dev)
1409 {
1410 struct fe_priv *priv = netdev_priv(dev);
1411
1412 if (priv->phy)
1413 priv->phy->disconnect(priv);
1414 fe_mdio_cleanup(priv);
1415
1416 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1417 free_irq(dev->irq, dev);
1418 }
1419
1420 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1421 {
1422 struct fe_priv *priv = netdev_priv(dev);
1423
1424 if (!priv->phy_dev)
1425 return -ENODEV;
1426
1427
1428 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1429 }
1430
1431 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1432 {
1433 struct fe_priv *priv = netdev_priv(dev);
1434 int frag_size, old_mtu;
1435 u32 fwd_cfg;
1436
1437 old_mtu = dev->mtu;
1438 dev->mtu = new_mtu;
1439
1440 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1441 return 0;
1442
1443 /* return early if the buffer sizes will not change */
1444 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1445 return 0;
1446 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1447 return 0;
1448
1449 if (new_mtu <= ETH_DATA_LEN)
1450 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1451 else
1452 priv->rx_ring.frag_size = PAGE_SIZE;
1453 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1454
1455 if (!netif_running(dev))
1456 return 0;
1457
1458 fe_stop(dev);
1459 if (!IS_ENABLED(CONFIG_SOC_MT7621)) {
1460 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1461 if (new_mtu <= ETH_DATA_LEN) {
1462 fwd_cfg &= ~FE_GDM1_JMB_EN;
1463 } else {
1464 frag_size = fe_max_frag_size(new_mtu);
1465 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1466 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1467 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1468 }
1469 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1470 }
1471
1472 return fe_open(dev);
1473 }
1474
1475 static const struct net_device_ops fe_netdev_ops = {
1476 .ndo_init = fe_init,
1477 .ndo_uninit = fe_uninit,
1478 .ndo_open = fe_open,
1479 .ndo_stop = fe_stop,
1480 .ndo_start_xmit = fe_start_xmit,
1481 .ndo_set_mac_address = fe_set_mac_address,
1482 .ndo_validate_addr = eth_validate_addr,
1483 .ndo_do_ioctl = fe_do_ioctl,
1484 .ndo_change_mtu = fe_change_mtu,
1485 .ndo_tx_timeout = fe_tx_timeout,
1486 .ndo_get_stats64 = fe_get_stats64,
1487 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1488 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1489 #ifdef CONFIG_NET_POLL_CONTROLLER
1490 .ndo_poll_controller = fe_poll_controller,
1491 #endif
1492 };
1493
1494 static void fe_reset_pending(struct fe_priv *priv)
1495 {
1496 struct net_device *dev = priv->netdev;
1497 int err;
1498
1499 rtnl_lock();
1500 fe_stop(dev);
1501
1502 err = fe_open(dev);
1503 if (err) {
1504 netif_alert(priv, ifup, dev,
1505 "Driver up/down cycle failed, closing device.\n");
1506 dev_close(dev);
1507 }
1508 rtnl_unlock();
1509 }
1510
1511 static const struct fe_work_t fe_work[] = {
1512 {FE_FLAG_RESET_PENDING, fe_reset_pending},
1513 };
1514
1515 static void fe_pending_work(struct work_struct *work)
1516 {
1517 struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
1518 int i;
1519 bool pending;
1520
1521 for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
1522 pending = test_and_clear_bit(fe_work[i].bitnr,
1523 priv->pending_flags);
1524 if (pending)
1525 fe_work[i].action(priv);
1526 }
1527 }
1528
1529 static int fe_probe(struct platform_device *pdev)
1530 {
1531 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1532 const struct of_device_id *match;
1533 struct fe_soc_data *soc;
1534 struct net_device *netdev;
1535 struct fe_priv *priv;
1536 struct clk *sysclk;
1537 int err, napi_weight;
1538
1539 err = device_reset(&pdev->dev);
1540 if (err)
1541 dev_err(&pdev->dev, "failed to reset device\n");
1542
1543 match = of_match_device(of_fe_match, &pdev->dev);
1544 soc = (struct fe_soc_data *)match->data;
1545
1546 if (soc->reg_table)
1547 fe_reg_table = soc->reg_table;
1548 else
1549 soc->reg_table = fe_reg_table;
1550
1551 fe_base = devm_ioremap_resource(&pdev->dev, res);
1552 if (IS_ERR(fe_base)) {
1553 err = -EADDRNOTAVAIL;
1554 goto err_out;
1555 }
1556
1557 netdev = alloc_etherdev(sizeof(*priv));
1558 if (!netdev) {
1559 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1560 err = -ENOMEM;
1561 goto err_iounmap;
1562 }
1563
1564 SET_NETDEV_DEV(netdev, &pdev->dev);
1565 netdev->netdev_ops = &fe_netdev_ops;
1566 netdev->base_addr = (unsigned long)fe_base;
1567
1568 netdev->irq = platform_get_irq(pdev, 0);
1569 if (netdev->irq < 0) {
1570 dev_err(&pdev->dev, "no IRQ resource found\n");
1571 err = -ENXIO;
1572 goto err_free_dev;
1573 }
1574
1575 priv = netdev_priv(netdev);
1576 spin_lock_init(&priv->page_lock);
1577 priv->resets = devm_reset_control_array_get_exclusive(&pdev->dev);
1578 if (IS_ERR(priv->resets)) {
1579 dev_err(&pdev->dev, "Failed to get resets for FE and ESW cores: %pe\n", priv->resets);
1580 priv->resets = NULL;
1581 }
1582
1583 if (soc->init_data)
1584 soc->init_data(soc, netdev);
1585 netdev->vlan_features = netdev->hw_features &
1586 ~(NETIF_F_HW_VLAN_CTAG_TX |
1587 NETIF_F_HW_VLAN_CTAG_RX);
1588 netdev->features |= netdev->hw_features;
1589
1590 if (IS_ENABLED(CONFIG_SOC_MT7621))
1591 netdev->max_mtu = 2048;
1592
1593 /* fake rx vlan filter func. to support tx vlan offload func */
1594 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1595 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1596
1597 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1598 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1599 if (!priv->hw_stats) {
1600 err = -ENOMEM;
1601 goto err_free_dev;
1602 }
1603 spin_lock_init(&priv->hw_stats->stats_lock);
1604 u64_stats_init(&priv->hw_stats->syncp);
1605 }
1606
1607 sysclk = devm_clk_get(&pdev->dev, NULL);
1608 if (!IS_ERR(sysclk)) {
1609 priv->sysclk = clk_get_rate(sysclk);
1610 } else if ((priv->flags & FE_FLAG_CALIBRATE_CLK)) {
1611 dev_err(&pdev->dev, "this soc needs a clk for calibration\n");
1612 err = -ENXIO;
1613 goto err_free_dev;
1614 }
1615
1616 priv->switch_np = of_parse_phandle(pdev->dev.of_node, "mediatek,switch", 0);
1617 if ((priv->flags & FE_FLAG_HAS_SWITCH) && !priv->switch_np) {
1618 dev_err(&pdev->dev, "failed to read switch phandle\n");
1619 err = -ENODEV;
1620 goto err_free_dev;
1621 }
1622
1623 priv->netdev = netdev;
1624 priv->dev = &pdev->dev;
1625 priv->soc = soc;
1626 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1627 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1628 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1629 priv->tx_ring.tx_ring_size = NUM_DMA_DESC;
1630 priv->rx_ring.rx_ring_size = NUM_DMA_DESC;
1631 INIT_WORK(&priv->pending_work, fe_pending_work);
1632
1633 napi_weight = 16;
1634 if (priv->flags & FE_FLAG_NAPI_WEIGHT) {
1635 napi_weight *= 4;
1636 priv->tx_ring.tx_ring_size *= 4;
1637 priv->rx_ring.rx_ring_size *= 4;
1638 }
1639 netif_napi_add_weight(netdev, &priv->rx_napi, fe_poll, napi_weight);
1640 fe_set_ethtool_ops(netdev);
1641
1642 err = register_netdev(netdev);
1643 if (err) {
1644 dev_err(&pdev->dev, "error bringing up device\n");
1645 goto err_free_dev;
1646 }
1647
1648 platform_set_drvdata(pdev, netdev);
1649
1650 netif_info(priv, probe, netdev, "mediatek frame engine at 0x%08lx, irq %d\n",
1651 netdev->base_addr, netdev->irq);
1652
1653 return 0;
1654
1655 err_free_dev:
1656 free_netdev(netdev);
1657 err_iounmap:
1658 devm_iounmap(&pdev->dev, fe_base);
1659 err_out:
1660 return err;
1661 }
1662
1663 static int fe_remove(struct platform_device *pdev)
1664 {
1665 struct net_device *dev = platform_get_drvdata(pdev);
1666 struct fe_priv *priv = netdev_priv(dev);
1667
1668 netif_napi_del(&priv->rx_napi);
1669 kfree(priv->hw_stats);
1670
1671 cancel_work_sync(&priv->pending_work);
1672
1673 unregister_netdev(dev);
1674 free_netdev(dev);
1675 platform_set_drvdata(pdev, NULL);
1676
1677 return 0;
1678 }
1679
1680 static struct platform_driver fe_driver = {
1681 .probe = fe_probe,
1682 .remove = fe_remove,
1683 .driver = {
1684 .name = "mtk_soc_eth",
1685 .owner = THIS_MODULE,
1686 .of_match_table = of_fe_match,
1687 },
1688 };
1689
1690 module_platform_driver(fe_driver);
1691
1692 MODULE_LICENSE("GPL");
1693 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1694 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1695 MODULE_VERSION(MTK_FE_DRV_VERSION);
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