target/linux/mediatek/patches-6.1/225-v6.3-clk-mediatek-Switch-to-mtk_clk_simple_probe-where-po.patch

   1 From c26e28015b74af73e0b299f6ad3ff22931e600b4 Mon Sep 17 00:00:00 2001
   2 From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
   3 Date: Fri, 20 Jan 2023 10:20:41 +0100
   4 Subject: [PATCH 05/15] clk: mediatek: Switch to mtk_clk_simple_probe() where
   5  possible
   6
   7 mtk_clk_simple_probe() is a function that registers mtk gate clocks
   8 and, if reset data is present, a reset controller and across all of
   9 the MTK clock drivers, such a function is duplicated many times:
  10 switch to the common mtk_clk_simple_probe() function for all of the
  11 clock drivers that are registering as platform drivers.
  12
  13 Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  14 Reviewed-by: Miles Chen <miles.chen@mediatek.com>
  15 Tested-by: Miles Chen <miles.chen@mediatek.com>
  16 Link: https://lore.kernel.org/r/20230120092053.182923-12-angelogioacchino.delregno@collabora.com
  17 Tested-by: Mingming Su <mingming.su@mediatek.com>
  18 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  19
  20 [daniel@makrotopia.org: removed parts not relevant for OpenWrt]
  21 ---
  22  drivers/clk/mediatek/clk-mt2701-aud.c | 31 ++++++----
  23  drivers/clk/mediatek/clk-mt2701-eth.c | 36 ++++--------
  24  drivers/clk/mediatek/clk-mt2701-g3d.c | 56 ++++--------------
  25  drivers/clk/mediatek/clk-mt2701-hif.c | 38 ++++--------
  26  drivers/clk/mediatek/clk-mt2712.c     | 83 ++++++++++----------------
  27  drivers/clk/mediatek/clk-mt7622-aud.c | 54 ++++++-----------
  28  drivers/clk/mediatek/clk-mt7622-eth.c | 82 +++++---------------------
  29  drivers/clk/mediatek/clk-mt7622-hif.c | 85 +++++----------------------
  30  drivers/clk/mediatek/clk-mt7629-hif.c | 85 +++++----------------------
  31  9 files changed, 144 insertions(+), 406 deletions(-)
  32
  33 --- a/drivers/clk/mediatek/clk-mt2701-aud.c
  34 +++ b/drivers/clk/mediatek/clk-mt2701-aud.c
  35 @@ -52,6 +52,7 @@ static const struct mtk_gate_regs audio3
  36  };
  37
  38  static const struct mtk_gate audio_clks[] = {
  39 +       GATE_DUMMY(CLK_DUMMY, "aud_dummy"),
  40         /* AUDIO0 */
  41         GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
  42         GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
  43 @@ -114,29 +115,27 @@ static const struct mtk_gate audio_clks[
  44         GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
  45  };
  46
  47 +static const struct mtk_clk_desc audio_desc = {
  48 +       .clks = audio_clks,
  49 +       .num_clks = ARRAY_SIZE(audio_clks),
  50 +};
  51 +
  52  static const struct of_device_id of_match_clk_mt2701_aud[] = {
  53 -       { .compatible = "mediatek,mt2701-audsys", },
  54 -       {}
  55 +       { .compatible = "mediatek,mt2701-audsys", .data = &audio_desc },
  56 +       { /* sentinel */ }
  57  };
  58
  59  static int clk_mt2701_aud_probe(struct platform_device *pdev)
  60  {
  61 -       struct clk_hw_onecell_data *clk_data;
  62 -       struct device_node *node = pdev->dev.of_node;
  63         int r;
  64
  65 -       clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
  66 -
  67 -       mtk_clk_register_gates(&pdev->dev, node, audio_clks,
  68 -                              ARRAY_SIZE(audio_clks), clk_data);
  69 -
  70 -       r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  71 +       r = mtk_clk_simple_probe(pdev);
  72         if (r) {
  73                 dev_err(&pdev->dev,
  74                         "could not register clock provider: %s: %d\n",
  75                         pdev->name, r);
  76
  77 -               goto err_clk_provider;
  78 +               return r;
  79         }
  80
  81         r = devm_of_platform_populate(&pdev->dev);
  82 @@ -146,13 +145,19 @@ static int clk_mt2701_aud_probe(struct p
  83         return 0;
  84
  85  err_plat_populate:
  86 -       of_clk_del_provider(node);
  87 -err_clk_provider:
  88 +       mtk_clk_simple_remove(pdev);
  89         return r;
  90  }
  91
  92 +static int clk_mt2701_aud_remove(struct platform_device *pdev)
  93 +{
  94 +       of_platform_depopulate(&pdev->dev);
  95 +       return mtk_clk_simple_remove(pdev);
  96 +}
  97 +
  98  static struct platform_driver clk_mt2701_aud_drv = {
  99         .probe = clk_mt2701_aud_probe,
 100 +       .remove = clk_mt2701_aud_remove,
 101         .driver = {
 102                 .name = "clk-mt2701-aud",
 103                 .of_match_table = of_match_clk_mt2701_aud,
 104 --- a/drivers/clk/mediatek/clk-mt2701-eth.c
 105 +++ b/drivers/clk/mediatek/clk-mt2701-eth.c
 106 @@ -20,6 +20,7 @@ static const struct mtk_gate_regs eth_cg
 107         GATE_MTK(_id, _name, _parent, &eth_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
 108
 109  static const struct mtk_gate eth_clks[] = {
 110 +       GATE_DUMMY(CLK_DUMMY, "eth_dummy"),
 111         GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
 112         GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
 113         GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
 114 @@ -38,35 +39,20 @@ static const struct mtk_clk_rst_desc clk
 115         .rst_bank_nr = ARRAY_SIZE(rst_ofs),
 116  };
 117
 118 -static const struct of_device_id of_match_clk_mt2701_eth[] = {
 119 -       { .compatible = "mediatek,mt2701-ethsys", },
 120 -       {}
 121 +static const struct mtk_clk_desc eth_desc = {
 122 +       .clks = eth_clks,
 123 +       .num_clks = ARRAY_SIZE(eth_clks),
 124 +       .rst_desc = &clk_rst_desc,
 125  };
 126
 127 -static int clk_mt2701_eth_probe(struct platform_device *pdev)
 128 -{
 129 -       struct clk_hw_onecell_data *clk_data;
 130 -       int r;
 131 -       struct device_node *node = pdev->dev.of_node;
 132 -
 133 -       clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
 134 -
 135 -       mtk_clk_register_gates(&pdev->dev, node, eth_clks,
 136 -                              ARRAY_SIZE(eth_clks), clk_data);
 137 -
 138 -       r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 139 -       if (r)
 140 -               dev_err(&pdev->dev,
 141 -                       "could not register clock provider: %s: %d\n",
 142 -                       pdev->name, r);
 143 -
 144 -       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 145 -
 146 -       return r;
 147 -}
 148 +static const struct of_device_id of_match_clk_mt2701_eth[] = {
 149 +       { .compatible = "mediatek,mt2701-ethsys", .data = &eth_desc },
 150 +       { /* sentinel */ }
 151 +};
 152
 153  static struct platform_driver clk_mt2701_eth_drv = {
 154 -       .probe = clk_mt2701_eth_probe,
 155 +       .probe = mtk_clk_simple_probe,
 156 +       .remove = mtk_clk_simple_remove,
 157         .driver = {
 158                 .name = "clk-mt2701-eth",
 159                 .of_match_table = of_match_clk_mt2701_eth,
 160 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c
 161 +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
 162 @@ -26,6 +26,7 @@ static const struct mtk_gate_regs g3d_cg
 163  };
 164
 165  static const struct mtk_gate g3d_clks[] = {
 166 +       GATE_DUMMY(CLK_DUMMY, "g3d_dummy"),
 167         GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
 168  };
 169
 170 @@ -37,57 +38,20 @@ static const struct mtk_clk_rst_desc clk
 171         .rst_bank_nr = ARRAY_SIZE(rst_ofs),
 172  };
 173
 174 -static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
 175 -{
 176 -       struct clk_hw_onecell_data *clk_data;
 177 -       struct device_node *node = pdev->dev.of_node;
 178 -       int r;
 179 -
 180 -       clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
 181 -
 182 -       mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks),
 183 -                              clk_data);
 184 -
 185 -       r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 186 -       if (r)
 187 -               dev_err(&pdev->dev,
 188 -                       "could not register clock provider: %s: %d\n",
 189 -                       pdev->name, r);
 190 -
 191 -       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 192 -
 193 -       return r;
 194 -}
 195 +static const struct mtk_clk_desc g3d_desc = {
 196 +       .clks = g3d_clks,
 197 +       .num_clks = ARRAY_SIZE(g3d_clks),
 198 +       .rst_desc = &clk_rst_desc,
 199 +};
 200
 201  static const struct of_device_id of_match_clk_mt2701_g3d[] = {
 202 -       {
 203 -               .compatible = "mediatek,mt2701-g3dsys",
 204 -               .data = clk_mt2701_g3dsys_init,
 205 -       }, {
 206 -               /* sentinel */
 207 -       }
 208 +       { .compatible = "mediatek,mt2701-g3dsys", .data = &g3d_desc },
 209 +       { /* sentinel */ }
 210  };
 211
 212 -static int clk_mt2701_g3d_probe(struct platform_device *pdev)
 213 -{
 214 -       int (*clk_init)(struct platform_device *);
 215 -       int r;
 216 -
 217 -       clk_init = of_device_get_match_data(&pdev->dev);
 218 -       if (!clk_init)
 219 -               return -EINVAL;
 220 -
 221 -       r = clk_init(pdev);
 222 -       if (r)
 223 -               dev_err(&pdev->dev,
 224 -                       "could not register clock provider: %s: %d\n",
 225 -                       pdev->name, r);
 226 -
 227 -       return r;
 228 -}
 229 -
 230  static struct platform_driver clk_mt2701_g3d_drv = {
 231 -       .probe = clk_mt2701_g3d_probe,
 232 +       .probe = mtk_clk_simple_probe,
 233 +       .remove = mtk_clk_simple_remove,
 234         .driver = {
 235                 .name = "clk-mt2701-g3d",
 236                 .of_match_table = of_match_clk_mt2701_g3d,
 237 --- a/drivers/clk/mediatek/clk-mt2701-hif.c
 238 +++ b/drivers/clk/mediatek/clk-mt2701-hif.c
 239 @@ -20,6 +20,7 @@ static const struct mtk_gate_regs hif_cg
 240         GATE_MTK(_id, _name, _parent, &hif_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
 241
 242  static const struct mtk_gate hif_clks[] = {
 243 +       GATE_DUMMY(CLK_DUMMY, "hif_dummy"),
 244         GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),
 245         GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),
 246         GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
 247 @@ -35,37 +36,20 @@ static const struct mtk_clk_rst_desc clk
 248         .rst_bank_nr = ARRAY_SIZE(rst_ofs),
 249  };
 250
 251 -static const struct of_device_id of_match_clk_mt2701_hif[] = {
 252 -       { .compatible = "mediatek,mt2701-hifsys", },
 253 -       {}
 254 +static const struct mtk_clk_desc hif_desc = {
 255 +       .clks = hif_clks,
 256 +       .num_clks = ARRAY_SIZE(hif_clks),
 257 +       .rst_desc = &clk_rst_desc,
 258  };
 259
 260 -static int clk_mt2701_hif_probe(struct platform_device *pdev)
 261 -{
 262 -       struct clk_hw_onecell_data *clk_data;
 263 -       int r;
 264 -       struct device_node *node = pdev->dev.of_node;
 265 -
 266 -       clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
 267 -
 268 -       mtk_clk_register_gates(&pdev->dev, node, hif_clks,
 269 -                              ARRAY_SIZE(hif_clks), clk_data);
 270 -
 271 -       r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 272 -       if (r) {
 273 -               dev_err(&pdev->dev,
 274 -                       "could not register clock provider: %s: %d\n",
 275 -                       pdev->name, r);
 276 -               return r;
 277 -       }
 278 -
 279 -       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 280 -
 281 -       return 0;
 282 -}
 283 +static const struct of_device_id of_match_clk_mt2701_hif[] = {
 284 +       { .compatible = "mediatek,mt2701-hifsys", .data = &hif_desc },
 285 +       { /* sentinel */ }
 286 +};
 287
 288  static struct platform_driver clk_mt2701_hif_drv = {
 289 -       .probe = clk_mt2701_hif_probe,
 290 +       .probe = mtk_clk_simple_probe,
 291 +       .remove = mtk_clk_simple_remove,
 292         .driver = {
 293                 .name = "clk-mt2701-hif",
 294                 .of_match_table = of_match_clk_mt2701_hif,
 295 --- a/drivers/clk/mediatek/clk-mt2712.c
 296 +++ b/drivers/clk/mediatek/clk-mt2712.c
 297 @@ -1337,50 +1337,6 @@ static int clk_mt2712_top_probe(struct p
 298         return r;
 299  }
 300
 301 -static int clk_mt2712_infra_probe(struct platform_device *pdev)
 302 -{
 303 -       struct clk_hw_onecell_data *clk_data;
 304 -       int r;
 305 -       struct device_node *node = pdev->dev.of_node;
 306 -
 307 -       clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
 308 -
 309 -       mtk_clk_register_gates(&pdev->dev, node, infra_clks,
 310 -                              ARRAY_SIZE(infra_clks), clk_data);
 311 -
 312 -       r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 313 -
 314 -       if (r != 0)
 315 -               pr_err("%s(): could not register clock provider: %d\n",
 316 -                       __func__, r);
 317 -
 318 -       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
 319 -
 320 -       return r;
 321 -}
 322 -
 323 -static int clk_mt2712_peri_probe(struct platform_device *pdev)
 324 -{
 325 -       struct clk_hw_onecell_data *clk_data;
 326 -       int r;
 327 -       struct device_node *node = pdev->dev.of_node;
 328 -
 329 -       clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
 330 -
 331 -       mtk_clk_register_gates(&pdev->dev, node, peri_clks,
 332 -                              ARRAY_SIZE(peri_clks), clk_data);
 333 -
 334 -       r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 335 -
 336 -       if (r != 0)
 337 -               pr_err("%s(): could not register clock provider: %d\n",
 338 -                       __func__, r);
 339 -
 340 -       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
 341 -
 342 -       return r;
 343 -}
 344 -
 345  static int clk_mt2712_mcu_probe(struct platform_device *pdev)
 346  {
 347         struct clk_hw_onecell_data *clk_data;
 348 @@ -1419,12 +1375,6 @@ static const struct of_device_id of_matc
 349                 .compatible = "mediatek,mt2712-topckgen",
 350                 .data = clk_mt2712_top_probe,
 351         }, {
 352 -               .compatible = "mediatek,mt2712-infracfg",
 353 -               .data = clk_mt2712_infra_probe,
 354 -       }, {
 355 -               .compatible = "mediatek,mt2712-pericfg",
 356 -               .data = clk_mt2712_peri_probe,
 357 -       }, {
 358                 .compatible = "mediatek,mt2712-mcucfg",
 359                 .data = clk_mt2712_mcu_probe,
 360         }, {
 361 @@ -1450,6 +1400,33 @@ static int clk_mt2712_probe(struct platf
 362         return r;
 363  }
 364
 365 +static const struct mtk_clk_desc infra_desc = {
 366 +       .clks = infra_clks,
 367 +       .num_clks = ARRAY_SIZE(infra_clks),
 368 +       .rst_desc = &clk_rst_desc[0],
 369 +};
 370 +
 371 +static const struct mtk_clk_desc peri_desc = {
 372 +       .clks = peri_clks,
 373 +       .num_clks = ARRAY_SIZE(peri_clks),
 374 +       .rst_desc = &clk_rst_desc[1],
 375 +};
 376 +
 377 +static const struct of_device_id of_match_clk_mt2712_simple[] = {
 378 +       { .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc },
 379 +       { .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, },
 380 +       { /* sentinel */ }
 381 +};
 382 +
 383 +static struct platform_driver clk_mt2712_simple_drv = {
 384 +       .probe = mtk_clk_simple_probe,
 385 +       .remove = mtk_clk_simple_remove,
 386 +       .driver = {
 387 +               .name = "clk-mt2712-simple",
 388 +               .of_match_table = of_match_clk_mt2712_simple,
 389 +       },
 390 +};
 391 +
 392  static struct platform_driver clk_mt2712_drv = {
 393         .probe = clk_mt2712_probe,
 394         .driver = {
 395 @@ -1460,7 +1437,11 @@ static struct platform_driver clk_mt2712
 396
 397  static int __init clk_mt2712_init(void)
 398  {
 399 -       return platform_driver_register(&clk_mt2712_drv);
 400 +       int ret = platform_driver_register(&clk_mt2712_drv);
 401 +
 402 +       if (ret)
 403 +               return ret;
 404 +       return platform_driver_register(&clk_mt2712_simple_drv);
 405  }
 406
 407  arch_initcall(clk_mt2712_init);
 408 --- a/drivers/clk/mediatek/clk-mt7622-aud.c
 409 +++ b/drivers/clk/mediatek/clk-mt7622-aud.c
 410 @@ -106,24 +106,22 @@ static const struct mtk_gate audio_clks[
 411         GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
 412  };
 413
 414 -static int clk_mt7622_audiosys_init(struct platform_device *pdev)
 415 +static const struct mtk_clk_desc audio_desc = {
 416 +       .clks = audio_clks,
 417 +       .num_clks = ARRAY_SIZE(audio_clks),
 418 +};
 419 +
 420 +static int clk_mt7622_aud_probe(struct platform_device *pdev)
 421  {
 422 -       struct clk_hw_onecell_data *clk_data;
 423 -       struct device_node *node = pdev->dev.of_node;
 424         int r;
 425
 426 -       clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
 427 -
 428 -       mtk_clk_register_gates(&pdev->dev, node, audio_clks,
 429 -                              ARRAY_SIZE(audio_clks), clk_data);
 430 -
 431 -       r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 432 +       r = mtk_clk_simple_probe(pdev);
 433         if (r) {
 434                 dev_err(&pdev->dev,
 435                         "could not register clock provider: %s: %d\n",
 436                         pdev->name, r);
 437
 438 -               goto err_clk_provider;
 439 +               return r;
 440         }
 441
 442         r = devm_of_platform_populate(&pdev->dev);
 443 @@ -133,40 +131,24 @@ static int clk_mt7622_audiosys_init(stru
 444         return 0;
 445
 446  err_plat_populate:
 447 -       of_clk_del_provider(node);
 448 -err_clk_provider:
 449 +       mtk_clk_simple_remove(pdev);
 450         return r;
 451  }
 452
 453 -static const struct of_device_id of_match_clk_mt7622_aud[] = {
 454 -       {
 455 -               .compatible = "mediatek,mt7622-audsys",
 456 -               .data = clk_mt7622_audiosys_init,
 457 -       }, {
 458 -               /* sentinel */
 459 -       }
 460 -};
 461 -
 462 -static int clk_mt7622_aud_probe(struct platform_device *pdev)
 463 +static int clk_mt7622_aud_remove(struct platform_device *pdev)
 464  {
 465 -       int (*clk_init)(struct platform_device *);
 466 -       int r;
 467 -
 468 -       clk_init = of_device_get_match_data(&pdev->dev);
 469 -       if (!clk_init)
 470 -               return -EINVAL;
 471 -
 472 -       r = clk_init(pdev);
 473 -       if (r)
 474 -               dev_err(&pdev->dev,
 475 -                       "could not register clock provider: %s: %d\n",
 476 -                       pdev->name, r);
 477 -
 478 -       return r;
 479 +       of_platform_depopulate(&pdev->dev);
 480 +       return mtk_clk_simple_remove(pdev);
 481  }
 482
 483 +static const struct of_device_id of_match_clk_mt7622_aud[] = {
 484 +       { .compatible = "mediatek,mt7622-audsys", .data = &audio_desc },
 485 +       { /* sentinel */ }
 486 +};
 487 +
 488  static struct platform_driver clk_mt7622_aud_drv = {
 489         .probe = clk_mt7622_aud_probe,
 490 +       .remove = clk_mt7622_aud_remove,
 491         .driver = {
 492                 .name = "clk-mt7622-aud",
 493                 .of_match_table = of_match_clk_mt7622_aud,
 494 --- a/drivers/clk/mediatek/clk-mt7622-eth.c
 495 +++ b/drivers/clk/mediatek/clk-mt7622-eth.c
 496 @@ -61,80 +61,26 @@ static const struct mtk_clk_rst_desc clk
 497         .rst_bank_nr = ARRAY_SIZE(rst_ofs),
 498  };
 499
 500 -static int clk_mt7622_ethsys_init(struct platform_device *pdev)
 501 -{
 502 -       struct clk_hw_onecell_data *clk_data;
 503 -       struct device_node *node = pdev->dev.of_node;
 504 -       int r;
 505 -
 506 -       clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
 507 -
 508 -       mtk_clk_register_gates(&pdev->dev, node, eth_clks,
 509 -                              ARRAY_SIZE(eth_clks), clk_data);
 510 -
 511 -       r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 512 -       if (r)
 513 -               dev_err(&pdev->dev,
 514 -                       "could not register clock provider: %s: %d\n",
 515 -                       pdev->name, r);
 516 -
 517 -       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 518 -
 519 -       return r;
 520 -}
 521 -
 522 -static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
 523 -{
 524 -       struct clk_hw_onecell_data *clk_data;
 525 -       struct device_node *node = pdev->dev.of_node;
 526 -       int r;
 527 -
 528 -       clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
 529 -
 530 -       mtk_clk_register_gates(&pdev->dev, node, sgmii_clks,
 531 -                              ARRAY_SIZE(sgmii_clks), clk_data);
 532 -
 533 -       r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 534 -       if (r)
 535 -               dev_err(&pdev->dev,
 536 -                       "could not register clock provider: %s: %d\n",
 537 -                       pdev->name, r);
 538 +static const struct mtk_clk_desc eth_desc = {
 539 +       .clks = eth_clks,
 540 +       .num_clks = ARRAY_SIZE(eth_clks),
 541 +       .rst_desc = &clk_rst_desc,
 542 +};
 543
 544 -       return r;
 545 -}
 546 +static const struct mtk_clk_desc sgmii_desc = {
 547 +       .clks = sgmii_clks,
 548 +       .num_clks = ARRAY_SIZE(sgmii_clks),
 549 +};
 550
 551  static const struct of_device_id of_match_clk_mt7622_eth[] = {
 552 -       {
 553 -               .compatible = "mediatek,mt7622-ethsys",
 554 -               .data = clk_mt7622_ethsys_init,
 555 -       }, {
 556 -               .compatible = "mediatek,mt7622-sgmiisys",
 557 -               .data = clk_mt7622_sgmiisys_init,
 558 -       }, {
 559 -               /* sentinel */
 560 -       }
 561 +       { .compatible = "mediatek,mt7622-ethsys", .data = &eth_desc },
 562 +       { .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc },
 563 +       { /* sentinel */ }
 564  };
 565
 566 -static int clk_mt7622_eth_probe(struct platform_device *pdev)
 567 -{
 568 -       int (*clk_init)(struct platform_device *);
 569 -       int r;
 570 -
 571 -       clk_init = of_device_get_match_data(&pdev->dev);
 572 -       if (!clk_init)
 573 -               return -EINVAL;
 574 -
 575 -       r = clk_init(pdev);
 576 -       if (r)
 577 -               dev_err(&pdev->dev,
 578 -                       "could not register clock provider: %s: %d\n",
 579 -                       pdev->name, r);
 580 -
 581 -       return r;
 582 -}
 583 -
 584  static struct platform_driver clk_mt7622_eth_drv = {
 585 -       .probe = clk_mt7622_eth_probe,
 586 +       .probe = mtk_clk_simple_probe,
 587 +       .remove = mtk_clk_simple_remove,
 588         .driver = {
 589                 .name = "clk-mt7622-eth",
 590                 .of_match_table = of_match_clk_mt7622_eth,
 591 --- a/drivers/clk/mediatek/clk-mt7622-hif.c
 592 +++ b/drivers/clk/mediatek/clk-mt7622-hif.c
 593 @@ -72,82 +72,27 @@ static const struct mtk_clk_rst_desc clk
 594         .rst_bank_nr = ARRAY_SIZE(rst_ofs),
 595  };
 596
 597 -static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
 598 -{
 599 -       struct clk_hw_onecell_data *clk_data;
 600 -       struct device_node *node = pdev->dev.of_node;
 601 -       int r;
 602 -
 603 -       clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
 604 -
 605 -       mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
 606 -                              ARRAY_SIZE(ssusb_clks), clk_data);
 607 -
 608 -       r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 609 -       if (r)
 610 -               dev_err(&pdev->dev,
 611 -                       "could not register clock provider: %s: %d\n",
 612 -                       pdev->name, r);
 613 -
 614 -       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 615 -
 616 -       return r;
 617 -}
 618 -
 619 -static int clk_mt7622_pciesys_init(struct platform_device *pdev)
 620 -{
 621 -       struct clk_hw_onecell_data *clk_data;
 622 -       struct device_node *node = pdev->dev.of_node;
 623 -       int r;
 624 -
 625 -       clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
 626 -
 627 -       mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
 628 -                              ARRAY_SIZE(pcie_clks), clk_data);
 629 -
 630 -       r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 631 -       if (r)
 632 -               dev_err(&pdev->dev,
 633 -                       "could not register clock provider: %s: %d\n",
 634 -                       pdev->name, r);
 635 -
 636 -       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 637 +static const struct mtk_clk_desc ssusb_desc = {
 638 +       .clks = ssusb_clks,
 639 +       .num_clks = ARRAY_SIZE(ssusb_clks),
 640 +       .rst_desc = &clk_rst_desc,
 641 +};
 642
 643 -       return r;
 644 -}
 645 +static const struct mtk_clk_desc pcie_desc = {
 646 +       .clks = pcie_clks,
 647 +       .num_clks = ARRAY_SIZE(pcie_clks),
 648 +       .rst_desc = &clk_rst_desc,
 649 +};
 650
 651  static const struct of_device_id of_match_clk_mt7622_hif[] = {
 652 -       {
 653 -               .compatible = "mediatek,mt7622-pciesys",
 654 -               .data = clk_mt7622_pciesys_init,
 655 -       }, {
 656 -               .compatible = "mediatek,mt7622-ssusbsys",
 657 -               .data = clk_mt7622_ssusbsys_init,
 658 -       }, {
 659 -               /* sentinel */
 660 -       }
 661 +       { .compatible = "mediatek,mt7622-pciesys", .data = &pcie_desc },
 662 +       { .compatible = "mediatek,mt7622-ssusbsys", .data = &ssusb_desc },
 663 +       { /* sentinel */ }
 664  };
 665
 666 -static int clk_mt7622_hif_probe(struct platform_device *pdev)
 667 -{
 668 -       int (*clk_init)(struct platform_device *);
 669 -       int r;
 670 -
 671 -       clk_init = of_device_get_match_data(&pdev->dev);
 672 -       if (!clk_init)
 673 -               return -EINVAL;
 674 -
 675 -       r = clk_init(pdev);
 676 -       if (r)
 677 -               dev_err(&pdev->dev,
 678 -                       "could not register clock provider: %s: %d\n",
 679 -                       pdev->name, r);
 680 -
 681 -       return r;
 682 -}
 683 -
 684  static struct platform_driver clk_mt7622_hif_drv = {
 685 -       .probe = clk_mt7622_hif_probe,
 686 +       .probe = mtk_clk_simple_probe,
 687 +       .remove = mtk_clk_simple_remove,
 688         .driver = {
 689                 .name = "clk-mt7622-hif",
 690                 .of_match_table = of_match_clk_mt7622_hif,
 691 --- a/drivers/clk/mediatek/clk-mt7629-hif.c
 692 +++ b/drivers/clk/mediatek/clk-mt7629-hif.c
 693 @@ -67,82 +67,27 @@ static const struct mtk_clk_rst_desc clk
 694         .rst_bank_nr = ARRAY_SIZE(rst_ofs),
 695  };
 696
 697 -static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
 698 -{
 699 -       struct clk_hw_onecell_data *clk_data;
 700 -       struct device_node *node = pdev->dev.of_node;
 701 -       int r;
 702 -
 703 -       clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
 704 -
 705 -       mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
 706 -                              ARRAY_SIZE(ssusb_clks), clk_data);
 707 -
 708 -       r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 709 -       if (r)
 710 -               dev_err(&pdev->dev,
 711 -                       "could not register clock provider: %s: %d\n",
 712 -                       pdev->name, r);
 713 -
 714 -       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 715 -
 716 -       return r;
 717 -}
 718 -
 719 -static int clk_mt7629_pciesys_init(struct platform_device *pdev)
 720 -{
 721 -       struct clk_hw_onecell_data *clk_data;
 722 -       struct device_node *node = pdev->dev.of_node;
 723 -       int r;
 724 -
 725 -       clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
 726 -
 727 -       mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
 728 -                              ARRAY_SIZE(pcie_clks), clk_data);
 729 -
 730 -       r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 731 -       if (r)
 732 -               dev_err(&pdev->dev,
 733 -                       "could not register clock provider: %s: %d\n",
 734 -                       pdev->name, r);
 735 -
 736 -       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 737 +static const struct mtk_clk_desc ssusb_desc = {
 738 +       .clks = ssusb_clks,
 739 +       .num_clks = ARRAY_SIZE(ssusb_clks),
 740 +       .rst_desc = &clk_rst_desc,
 741 +};
 742
 743 -       return r;
 744 -}
 745 +static const struct mtk_clk_desc pcie_desc = {
 746 +       .clks = pcie_clks,
 747 +       .num_clks = ARRAY_SIZE(pcie_clks),
 748 +       .rst_desc = &clk_rst_desc,
 749 +};
 750
 751  static const struct of_device_id of_match_clk_mt7629_hif[] = {
 752 -       {
 753 -               .compatible = "mediatek,mt7629-pciesys",
 754 -               .data = clk_mt7629_pciesys_init,
 755 -       }, {
 756 -               .compatible = "mediatek,mt7629-ssusbsys",
 757 -               .data = clk_mt7629_ssusbsys_init,
 758 -       }, {
 759 -               /* sentinel */
 760 -       }
 761 +       { .compatible = "mediatek,mt7629-pciesys", .data = &pcie_desc },
 762 +       { .compatible = "mediatek,mt7629-ssusbsys", .data = &ssusb_desc },
 763 +       { /* sentinel */ }
 764  };
 765
 766 -static int clk_mt7629_hif_probe(struct platform_device *pdev)
 767 -{
 768 -       int (*clk_init)(struct platform_device *);
 769 -       int r;
 770 -
 771 -       clk_init = of_device_get_match_data(&pdev->dev);
 772 -       if (!clk_init)
 773 -               return -EINVAL;
 774 -
 775 -       r = clk_init(pdev);
 776 -       if (r)
 777 -               dev_err(&pdev->dev,
 778 -                       "could not register clock provider: %s: %d\n",
 779 -                       pdev->name, r);
 780 -
 781 -       return r;
 782 -}
 783 -
 784  static struct platform_driver clk_mt7629_hif_drv = {
 785 -       .probe = clk_mt7629_hif_probe,
 786 +       .probe = mtk_clk_simple_probe,
 787 +       .remove = mtk_clk_simple_remove,
 788         .driver = {
 789                 .name = "clk-mt7629-hif",
 790                 .of_match_table = of_match_clk_mt7629_hif,