lantiq: Fix build after kernel 5.15.150
[openwrt/staging/nbd.git] / target / linux / lantiq / patches-5.15 / 0152-lantiq-VPE.patch
1 From 4d48a3d1ef6f8d036bd926e3c1f70b56fcc679b2 Mon Sep 17 00:00:00 2001
2 From: Stefan Koch <stefan.koch10@gmail.com>
3 Date: Thu, 20 Oct 2016 21:32:00 +0200
4 Subject: [PATCH] lantiq: vpe
5
6 Signed-off-by: Stefan Koch <stefan.koch10@gmail.com>
7 ---
8 arch/mips/Kconfig | 6 ++++
9 arch/mips/include/asm/mipsmtregs.h | 5 ++++
10 arch/mips/include/asm/vpe.h | 9 ++++++
11 arch/mips/kernel/vpe-mt.c | 47 ++++++++++++++++++++++++++++++
12 arch/mips/kernel/vpe.c | 35 ++++++++++++++++++++++
13 arch/mips/lantiq/prom.c | 4 +++
14 6 files changed, 106 insertions(+)
15
16 --- a/arch/mips/Kconfig
17 +++ b/arch/mips/Kconfig
18 @@ -2433,6 +2433,12 @@ config MIPS_VPE_LOADER
19 Includes a loader for loading an elf relocatable object
20 onto another VPE and running it.
21
22 +config IFX_VPE_EXT
23 + bool "IFX APRP Extensions"
24 + depends on MIPS_VPE_LOADER
25 + help
26 + IFX included extensions in APRP
27 +
28 config MIPS_VPE_LOADER_CMP
29 bool
30 default "y"
31 --- a/arch/mips/include/asm/mipsmtregs.h
32 +++ b/arch/mips/include/asm/mipsmtregs.h
33 @@ -32,6 +32,9 @@
34 #define read_c0_vpeconf1() __read_32bit_c0_register($1, 3)
35 #define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val)
36
37 +#define read_c0_vpeopt() __read_32bit_c0_register($1, 7)
38 +#define write_c0_vpeopt(val) __write_32bit_c0_register($1, 7, val)
39 +
40 #define read_c0_tcstatus() __read_32bit_c0_register($2, 1)
41 #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val)
42
43 @@ -378,6 +381,8 @@ do { \
44 #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val)
45 #define read_vpe_c0_vpeconf1() mftc0(1, 3)
46 #define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val)
47 +#define read_vpe_c0_vpeopt() mftc0(1, 7)
48 +#define write_vpe_c0_vpeopt(val) mttc0(1, 7, val)
49 #define read_vpe_c0_count() mftc0(9, 0)
50 #define write_vpe_c0_count(val) mttc0(9, 0, val)
51 #define read_vpe_c0_status() mftc0(12, 0)
52 --- a/arch/mips/include/asm/vpe.h
53 +++ b/arch/mips/include/asm/vpe.h
54 @@ -123,4 +123,13 @@ void cleanup_tc(struct tc *tc);
55
56 int __init vpe_module_init(void);
57 void __exit vpe_module_exit(void);
58 +
59 +/* For the explanation of the APIs please refer the section "MT APRP Kernel
60 + * Programming" in AR9 SW Architecture Specification
61 + */
62 +int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags);
63 +int32_t vpe1_sw_stop(uint32_t flags);
64 +uint32_t vpe1_get_load_addr(uint32_t flags);
65 +uint32_t vpe1_get_max_mem(uint32_t flags);
66 +
67 #endif /* _ASM_VPE_H */
68 --- a/arch/mips/kernel/vpe-mt.c
69 +++ b/arch/mips/kernel/vpe-mt.c
70 @@ -415,6 +415,8 @@ int __init vpe_module_init(void)
71 }
72
73 v->ntcs = hw_tcs - aprp_cpu_index();
74 + write_tc_c0_tcbind((read_tc_c0_tcbind() &
75 + ~TCBIND_CURVPE) | 1);
76
77 /* add the tc to the list of this vpe's tc's. */
78 list_add(&t->tc, &v->tc);
79 @@ -518,3 +520,47 @@ void __exit vpe_module_exit(void)
80 release_vpe(v);
81 }
82 }
83 +
84 +#ifdef CONFIG_IFX_VPE_EXT
85 +int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags)
86 +{
87 + enum vpe_state state;
88 + struct vpe *v = get_vpe(tclimit);
89 + struct vpe_notifications *not;
90 +
91 + if (tcmask || flags) {
92 + pr_warn("Currently tcmask and flags should be 0. Other values are not supported\n");
93 + return -1;
94 + }
95 +
96 + state = xchg(&v->state, VPE_STATE_INUSE);
97 + if (state != VPE_STATE_UNUSED) {
98 + vpe_stop(v);
99 +
100 + list_for_each_entry(not, &v->notify, list) {
101 + not->stop(tclimit);
102 + }
103 + }
104 +
105 + v->__start = (unsigned long)sw_start_addr;
106 +
107 + if (!vpe_run(v)) {
108 + pr_debug("VPE loader: VPE1 running successfully\n");
109 + return 0;
110 + }
111 + return -1;
112 +}
113 +EXPORT_SYMBOL(vpe1_sw_start);
114 +
115 +int32_t vpe1_sw_stop(uint32_t flags)
116 +{
117 + struct vpe *v = get_vpe(tclimit);
118 +
119 + if (!vpe_free(v)) {
120 + pr_debug("RP Stopped\n");
121 + return 0;
122 + } else
123 + return -1;
124 +}
125 +EXPORT_SYMBOL(vpe1_sw_stop);
126 +#endif
127 --- a/arch/mips/kernel/vpe.c
128 +++ b/arch/mips/kernel/vpe.c
129 @@ -49,6 +49,41 @@ struct vpe_control vpecontrol = {
130 .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list)
131 };
132
133 +#ifdef CONFIG_IFX_VPE_EXT
134 +unsigned int vpe1_load_addr;
135 +
136 +static int __init load_address(char *str)
137 +{
138 + get_option(&str, &vpe1_load_addr);
139 + return 1;
140 +}
141 +__setup("vpe1_load_addr=", load_address);
142 +
143 +static unsigned int vpe1_mem;
144 +static int __init vpe1mem(char *str)
145 +{
146 + vpe1_mem = memparse(str, &str);
147 + return 1;
148 +}
149 +__setup("vpe1_mem=", vpe1mem);
150 +
151 +uint32_t vpe1_get_load_addr(uint32_t flags)
152 +{
153 + return vpe1_load_addr;
154 +}
155 +EXPORT_SYMBOL(vpe1_get_load_addr);
156 +
157 +uint32_t vpe1_get_max_mem(uint32_t flags)
158 +{
159 + if (!vpe1_mem)
160 + return P_SIZE;
161 + else
162 + return vpe1_mem;
163 +}
164 +EXPORT_SYMBOL(vpe1_get_max_mem);
165 +
166 +#endif
167 +
168 /* get the vpe associated with this minor */
169 struct vpe *get_vpe(int minor)
170 {
171 --- a/arch/mips/lantiq/prom.c
172 +++ b/arch/mips/lantiq/prom.c
173 @@ -28,10 +28,14 @@ EXPORT_SYMBOL_GPL(ebu_lock);
174 */
175 static struct ltq_soc_info soc_info;
176
177 +/* for Multithreading (APRP), vpe.c will use it */
178 +unsigned long cp0_memsize;
179 +
180 const char *get_system_type(void)
181 {
182 return soc_info.sys_type;
183 }
184 +EXPORT_SYMBOL(ltq_soc_type);
185
186 int ltq_soc_type(void)
187 {