target/linux/ipq807x/patches-5.15/0012-v5.19-arm64-dts-qcom-align-dmas-in-I2C-SPI-UART-with-DT-sc.patch

   1 From 6f39b05b13e7be39919fd8d235bb0e63ecabf190 Mon Sep 17 00:00:00 2001
   2 From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
   3 Date: Tue, 5 Apr 2022 08:34:43 +0200
   4 Subject: [PATCH] arm64: dts: qcom: align dmas in I2C/SPI/UART with DT schema
   5
   6 The DT schema expects dma channels in tx-rx order.  No functional
   7 change.
   8
   9 Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  10 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  11 Link: https://lore.kernel.org/r/20220405063451.12011-2-krzysztof.kozlowski@linaro.org
  12 ---
  13  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 ++++++++--------
  14  1 file changed, 8 insertions(+), 8 deletions(-)
  15
  16 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  17 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  18 @@ -471,8 +471,8 @@
  19                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
  20                         clock-names = "iface", "core";
  21                         clock-frequency = <400000>;
  22 -                       dmas = <&blsp_dma 15>, <&blsp_dma 14>;
  23 -                       dma-names = "rx", "tx";
  24 +                       dmas = <&blsp_dma 14>, <&blsp_dma 15>;
  25 +                       dma-names = "tx", "rx";
  26                         pinctrl-0 = <&i2c_0_pins>;
  27                         pinctrl-names = "default";
  28                         status = "disabled";
  29 @@ -488,8 +488,8 @@
  30                                 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
  31                         clock-names = "iface", "core";
  32                         clock-frequency = <100000>;
  33 -                       dmas = <&blsp_dma 17>, <&blsp_dma 16>;
  34 -                       dma-names = "rx", "tx";
  35 +                       dmas = <&blsp_dma 16>, <&blsp_dma 17>;
  36 +                       dma-names = "tx", "rx";
  37                         status = "disabled";
  38                 };
  39
  40 @@ -503,8 +503,8 @@
  41                                  <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
  42                         clock-names = "iface", "core";
  43                         clock-frequency = <400000>;
  44 -                       dmas = <&blsp_dma 21>, <&blsp_dma 20>;
  45 -                       dma-names = "rx", "tx";
  46 +                       dmas = <&blsp_dma 20>, <&blsp_dma 21>;
  47 +                       dma-names = "tx", "rx";
  48                         status = "disabled";
  49                 };
  50
  51 @@ -518,8 +518,8 @@
  52                                  <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
  53                         clock-names = "iface", "core";
  54                         clock-frequency = <100000>;
  55 -                       dmas = <&blsp_dma 23>, <&blsp_dma 22>;
  56 -                       dma-names = "rx", "tx";
  57 +                       dmas = <&blsp_dma 22>, <&blsp_dma 23>;
  58 +                       dma-names = "tx", "rx";
  59                         status = "disabled";
  60                 };
  61