target/linux/ipq40xx/patches-6.1/850-soc-add-qualcomm-syscon.patch

   1 From: Christian Lamparter <chunkeey@googlemail.com>
   2 Subject: SoC: add qualcomm syscon
   3 --- a/drivers/soc/qcom/Kconfig
   4 +++ b/drivers/soc/qcom/Kconfig
   5 @@ -248,4 +248,11 @@ config QCOM_ICC_BWMON
   6           the fixed bandwidth votes from cpufreq (CPU nodes) thus achieve high
   7           memory throughput even with lower CPU frequencies.
   8
   9 +config QCOM_TCSR
  10 +       tristate "QCOM Top Control and Status Registers"
  11 +       depends on ARCH_QCOM
  12 +       help
  13 +         Say y here to enable TCSR support.  The TCSR provides control
  14 +         functions for various peripherals.
  15 +
  16  endmenu
  17 --- a/drivers/soc/qcom/Makefile
  18 +++ b/drivers/soc/qcom/Makefile
  19 @@ -29,3 +29,4 @@ obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
  20  obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
  21  obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) +=        kryo-l2-accessors.o
  22  obj-$(CONFIG_QCOM_ICC_BWMON)   += icc-bwmon.o
  23 +obj-$(CONFIG_QCOM_TCSR)                += qcom_tcsr.o
  24 --- /dev/null
  25 +++ b/drivers/soc/qcom/qcom_tcsr.c
  26 @@ -0,0 +1,98 @@
  27 +/*
  28 + * Copyright (c) 2014, The Linux foundation. All rights reserved.
  29 + *
  30 + * This program is free software; you can redistribute it and/or modify
  31 + * it under the terms of the GNU General Public License rev 2 and
  32 + * only rev 2 as published by the free Software foundation.
  33 + *
  34 + * This program is distributed in the hope that it will be useful,
  35 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  36 + * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE.  See the
  37 + * GNU General Public License for more details.
  38 + */
  39 +
  40 +#include <linux/clk.h>
  41 +#include <linux/err.h>
  42 +#include <linux/io.h>
  43 +#include <linux/module.h>
  44 +#include <linux/of.h>
  45 +#include <linux/of_platform.h>
  46 +#include <linux/platform_device.h>
  47 +
  48 +#define TCSR_USB_PORT_SEL      0xb0
  49 +#define TCSR_USB_HSPHY_CONFIG  0xC
  50 +
  51 +#define TCSR_ESS_INTERFACE_SEL_OFFSET   0x0
  52 +#define TCSR_ESS_INTERFACE_SEL_MASK     0xf
  53 +
  54 +#define TCSR_WIFI0_GLB_CFG_OFFSET      0x0
  55 +#define TCSR_WIFI1_GLB_CFG_OFFSET      0x4
  56 +#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2   0x4
  57 +
  58 +static int tcsr_probe(struct platform_device *pdev)
  59 +{
  60 +       struct resource *res;
  61 +       const struct device_node *node = pdev->dev.of_node;
  62 +       void __iomem *base;
  63 +       u32 val;
  64 +
  65 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  66 +       base = devm_ioremap_resource(&pdev->dev, res);
  67 +       if (IS_ERR(base))
  68 +               return PTR_ERR(base);
  69 +
  70 +       if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
  71 +               dev_err(&pdev->dev, "setting usb port select = %d\n", val);
  72 +               writel(val, base + TCSR_USB_PORT_SEL);
  73 +       }
  74 +
  75 +       if (!of_property_read_u32(node, "qcom,usb-hsphy-mode-select", &val)) {
  76 +               dev_info(&pdev->dev, "setting usb hs phy mode select = %x\n", val);
  77 +               writel(val, base + TCSR_USB_HSPHY_CONFIG);
  78 +       }
  79 +
  80 +       if (!of_property_read_u32(node, "qcom,ess-interface-select", &val)) {
  81 +               u32 tmp = 0;
  82 +               dev_info(&pdev->dev, "setting ess interface select = %x\n", val);
  83 +               tmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET);
  84 +               tmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK);
  85 +               tmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK);
  86 +               writel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET);
  87 +        }
  88 +
  89 +       if (!of_property_read_u32(node, "qcom,wifi_glb_cfg", &val)) {
  90 +               dev_info(&pdev->dev, "setting wifi_glb_cfg = %x\n", val);
  91 +               writel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET);
  92 +               writel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET);
  93 +       }
  94 +
  95 +       if (!of_property_read_u32(node, "qcom,wifi_noc_memtype_m0_m2", &val)) {
  96 +               dev_info(&pdev->dev,
  97 +                       "setting wifi_noc_memtype_m0_m2 = %x\n", val);
  98 +               writel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2);
  99 +       }
 100 +
 101 +       return 0;
 102 +}
 103 +
 104 +static const struct of_device_id tcsr_dt_match[] = {
 105 +       { .compatible = "qcom,tcsr", },
 106 +       { },
 107 +};
 108 +
 109 +MODULE_DEVICE_TABLE(of, tcsr_dt_match);
 110 +
 111 +static struct platform_driver tcsr_driver = {
 112 +       .driver = {
 113 +               .name           = "tcsr",
 114 +               .owner          = THIS_MODULE,
 115 +               .of_match_table = tcsr_dt_match,
 116 +       },
 117 +       .probe = tcsr_probe,
 118 +};
 119 +
 120 +module_platform_driver(tcsr_driver);
 121 +
 122 +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
 123 +MODULE_DESCRIPTION("QCOM TCSR driver");
 124 +MODULE_LICENSE("GPL v2");
 125 --- /dev/null
 126 +++ b/include/dt-bindings/soc/qcom,tcsr.h
 127 @@ -0,0 +1,48 @@
 128 +/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
 129 + *
 130 + * This program is free software; you can redistribute it and/or modify
 131 + * it under the terms of the GNU General Public License version 2 and
 132 + * only version 2 as published by the Free Software Foundation.
 133 + *
 134 + * This program is distributed in the hope that it will be useful,
 135 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 136 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 137 + * GNU General Public License for more details.
 138 + */
 139 +#ifndef __DT_BINDINGS_QCOM_TCSR_H
 140 +#define __DT_BINDINGS_QCOM_TCSR_H
 141 +
 142 +#define TCSR_USB_SELECT_USB3_P0                0x1
 143 +#define TCSR_USB_SELECT_USB3_P1                0x2
 144 +#define TCSR_USB_SELECT_USB3_DUAL      0x3
 145 +
 146 +/* IPQ40xx HS PHY Mode Select */
 147 +#define TCSR_USB_HSPHY_HOST_MODE       0x00E700E7
 148 +#define TCSR_USB_HSPHY_DEVICE_MODE     0x00C700E7
 149 +
 150 +/* IPQ40xx ess interface mode select */
 151 +#define TCSR_ESS_PSGMII              0
 152 +#define TCSR_ESS_PSGMII_RGMII5       1
 153 +#define TCSR_ESS_PSGMII_RMII0        2
 154 +#define TCSR_ESS_PSGMII_RMII1        4
 155 +#define TCSR_ESS_PSGMII_RMII0_RMII1  6
 156 +#define TCSR_ESS_PSGMII_RGMII4       9
 157 +
 158 +/*
 159 + * IPQ40xx WiFi Global Config
 160 + * Bit 30:AXID_EN
 161 + * Enable AXI master bus Axid translating to confirm all txn submitted by order
 162 + * Bit 24: Use locally generated socslv_wxi_bvalid
 163 + * 1:  use locally generate socslv_wxi_bvalid for performance.
 164 + * 0:  use SNOC socslv_wxi_bvalid.
 165 + */
 166 +#define TCSR_WIFI_GLB_CFG              0x41000000
 167 +
 168 +/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */
 169 +#define TCSR_WIFI_NOC_MEMTYPE_M0_M2    0x02222222
 170 +
 171 +/* TCSR A/B REG */
 172 +#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL     0
 173 +#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL     1
 174 +
 175 +#endif