target/linux/generic/backport-6.6/790-05-v6.9-net-dsa-mt7530-always-trap-frames-to-active-CPU-port.patch

   1 From 617b07e08bcb1f69a72a085a7d847d1ca2999830 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
   3 Date: Mon, 22 Jan 2024 08:35:52 +0300
   4 Subject: [PATCH 05/30] net: dsa: mt7530: always trap frames to active CPU port
   5  on MT7530
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 On the MT7530 switch, the CPU_PORT field indicates which CPU port to trap
  11 frames to, regardless of the affinity of the inbound user port.
  12
  13 When multiple CPU ports are in use, if the DSA conduit interface is down,
  14 trapped frames won't be passed to the conduit interface.
  15
  16 To make trapping frames work including this case, implement
  17 ds->ops->conduit_state_change() on this subdriver and set the CPU_PORT
  18 field to the numerically smallest CPU port whose conduit interface is up.
  19 Introduce the active_cpu_ports field to store the information of the active
  20 CPU ports. Correct the macros, CPU_PORT is bits 4 through 6 of the
  21 register.
  22
  23 Add a comment to explain frame trapping for this switch.
  24
  25 Currently, the driver doesn't support the use of multiple CPU ports so this
  26 is not necessarily a bug fix.
  27
  28 Suggested-by: Vladimir Oltean <olteanv@gmail.com>
  29 Suggested-by: Russell King (Oracle) <linux@armlinux.org.uk>
  30 Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
  31 Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
  32 Link: https://lore.kernel.org/r/20240122-for-netnext-mt7530-improvements-1-v3-1-042401f2b279@arinc9.com
  33 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  34 ---
  35  drivers/net/dsa/mt7530.c | 35 +++++++++++++++++++++++++++++++----
  36  drivers/net/dsa/mt7530.h |  6 ++++--
  37  2 files changed, 35 insertions(+), 6 deletions(-)
  38
  39 --- a/drivers/net/dsa/mt7530.c
  40 +++ b/drivers/net/dsa/mt7530.c
  41 @@ -1071,10 +1071,6 @@ mt753x_cpu_port_enable(struct dsa_switch
  42         mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
  43                    UNU_FFP(BIT(port)));
  44
  45 -       /* Set CPU port number */
  46 -       if (priv->id == ID_MT7530 || priv->id == ID_MT7621)
  47 -               mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
  48 -
  49         /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on
  50          * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that
  51          * is affine to the inbound user port.
  52 @@ -3128,6 +3124,36 @@ static int mt753x_set_mac_eee(struct dsa
  53         return 0;
  54  }
  55
  56 +static void
  57 +mt753x_conduit_state_change(struct dsa_switch *ds,
  58 +                           const struct net_device *conduit,
  59 +                           bool operational)
  60 +{
  61 +       struct dsa_port *cpu_dp = conduit->dsa_ptr;
  62 +       struct mt7530_priv *priv = ds->priv;
  63 +       int val = 0;
  64 +       u8 mask;
  65 +
  66 +       /* Set the CPU port to trap frames to for MT7530. Trapped frames will be
  67 +        * forwarded to the numerically smallest CPU port whose conduit
  68 +        * interface is up.
  69 +        */
  70 +       if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
  71 +               return;
  72 +
  73 +       mask = BIT(cpu_dp->index);
  74 +
  75 +       if (operational)
  76 +               priv->active_cpu_ports |= mask;
  77 +       else
  78 +               priv->active_cpu_ports &= ~mask;
  79 +
  80 +       if (priv->active_cpu_ports)
  81 +               val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports));
  82 +
  83 +       mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
  84 +}
  85 +
  86  static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
  87  {
  88         return 0;
  89 @@ -3183,6 +3209,7 @@ const struct dsa_switch_ops mt7530_switc
  90         .phylink_mac_link_up    = mt753x_phylink_mac_link_up,
  91         .get_mac_eee            = mt753x_get_mac_eee,
  92         .set_mac_eee            = mt753x_set_mac_eee,
  93 +       .master_state_change    = mt753x_conduit_state_change,
  94  };
  95  EXPORT_SYMBOL_GPL(mt7530_switch_ops);
  96
  97 --- a/drivers/net/dsa/mt7530.h
  98 +++ b/drivers/net/dsa/mt7530.h
  99 @@ -41,8 +41,8 @@ enum mt753x_id {
 100  #define  UNU_FFP(x)                    (((x) & 0xff) << 8)
 101  #define  UNU_FFP_MASK                  UNU_FFP(~0)
 102  #define  CPU_EN                                BIT(7)
 103 -#define  CPU_PORT(x)                   ((x) << 4)
 104 -#define  CPU_MASK                      (0xf << 4)
 105 +#define  CPU_PORT_MASK                 GENMASK(6, 4)
 106 +#define  CPU_PORT(x)                   FIELD_PREP(CPU_PORT_MASK, x)
 107  #define  MIRROR_EN                     BIT(3)
 108  #define  MIRROR_PORT(x)                        ((x) & 0x7)
 109  #define  MIRROR_MASK                   0x7
 110 @@ -780,6 +780,7 @@ struct mt753x_info {
 111   * @irq_domain:                IRQ domain of the switch irq_chip
 112   * @irq_enable:                IRQ enable bits, synced to SYS_INT_EN
 113   * @create_sgmii:      Pointer to function creating SGMII PCS instance(s)
 114 + * @active_cpu_ports:  Holding the active CPU ports
 115   */
 116  struct mt7530_priv {
 117         struct device           *dev;
 118 @@ -806,6 +807,7 @@ struct mt7530_priv {
 119         struct irq_domain *irq_domain;
 120         u32 irq_enable;
 121         int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii);
 122 +       u8 active_cpu_ports;
 123  };
 124
 125  struct mt7530_hw_vlan_entry {