target/linux/generic/backport-5.15/704-18-v5.19-net-mtk_eth_soc-partially-convert-to-phylink_pcs.patch

   1 From 14a44ab0330d290fade1403a920e299cc56d7300 Mon Sep 17 00:00:00 2001
   2 From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
   3 Date: Wed, 18 May 2022 15:55:28 +0100
   4 Subject: [PATCH 12/12] net: mtk_eth_soc: partially convert to phylink_pcs
   5
   6 Partially convert mtk_eth_soc to phylink_pcs, moving the configuration,
   7 link up and AN restart over. However, it seems mac_pcs_get_state()
   8 doesn't actually get the state from the PCS, so we can't convert that
   9 over without a better understanding of the hardware.
  10
  11 Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
  12 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  13 ---
  14  drivers/net/ethernet/mediatek/mtk_eth_soc.c | 49 ++++++++----------
  15  drivers/net/ethernet/mediatek/mtk_eth_soc.h |  7 ++-
  16  drivers/net/ethernet/mediatek/mtk_sgmii.c   | 55 +++++++++++----------
  17  3 files changed, 53 insertions(+), 58 deletions(-)
  18
  19 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  20 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  21 @@ -310,6 +310,25 @@ static void mtk_gmac0_rgmii_adjust(struc
  22         mtk_w32(eth, val, TRGMII_TCK_CTRL);
  23  }
  24
  25 +static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
  26 +                                             phy_interface_t interface)
  27 +{
  28 +       struct mtk_mac *mac = container_of(config, struct mtk_mac,
  29 +                                          phylink_config);
  30 +       struct mtk_eth *eth = mac->hw;
  31 +       unsigned int sid;
  32 +
  33 +       if (interface == PHY_INTERFACE_MODE_SGMII ||
  34 +           phy_interface_mode_is_8023z(interface)) {
  35 +               sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
  36 +                      0 : mac->id;
  37 +
  38 +               return mtk_sgmii_select_pcs(eth->sgmii, sid);
  39 +       }
  40 +
  41 +       return NULL;
  42 +}
  43 +
  44  static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
  45                            const struct phylink_link_state *state)
  46  {
  47 @@ -317,7 +336,7 @@ static void mtk_mac_config(struct phylin
  48                                            phylink_config);
  49         struct mtk_eth *eth = mac->hw;
  50         int val, ge_mode, err = 0;
  51 -       u32 sid, i;
  52 +       u32 i;
  53
  54         /* MT76x8 has no hardware settings between for the MAC */
  55         if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
  56 @@ -438,15 +457,6 @@ static void mtk_mac_config(struct phylin
  57                                    SYSCFG0_SGMII_MASK,
  58                                    ~(u32)SYSCFG0_SGMII_MASK);
  59
  60 -               /* Decide how GMAC and SGMIISYS be mapped */
  61 -               sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
  62 -                      0 : mac->id;
  63 -
  64 -               /* Setup SGMIISYS with the determined property */
  65 -               err = mtk_sgmii_config(eth->sgmii, sid, mode, state->interface);
  66 -               if (err)
  67 -                       goto init_err;
  68 -
  69                 /* Save the syscfg0 value for mac_finish */
  70                 mac->syscfg0 = val;
  71         } else if (phylink_autoneg_inband(mode)) {
  72 @@ -526,14 +536,6 @@ static void mtk_mac_pcs_get_state(struct
  73                 state->pause |= MLO_PAUSE_TX;
  74  }
  75
  76 -static void mtk_mac_an_restart(struct phylink_config *config)
  77 -{
  78 -       struct mtk_mac *mac = container_of(config, struct mtk_mac,
  79 -                                          phylink_config);
  80 -
  81 -       mtk_sgmii_restart_an(mac->hw, mac->id);
  82 -}
  83 -
  84  static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
  85                               phy_interface_t interface)
  86  {
  87 @@ -554,15 +556,6 @@ static void mtk_mac_link_up(struct phyli
  88                                            phylink_config);
  89         u32 mcr;
  90
  91 -       if (phy_interface_mode_is_8023z(interface)) {
  92 -               struct mtk_eth *eth = mac->hw;
  93 -
  94 -               /* Decide how GMAC and SGMIISYS be mapped */
  95 -               int sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
  96 -                          0 : mac->id;
  97 -               mtk_sgmii_link_up(eth->sgmii, sid, speed, duplex);
  98 -       }
  99 -
 100         mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
 101         mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 |
 102                  MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC |
 103 @@ -595,8 +588,8 @@ static void mtk_mac_link_up(struct phyli
 104
 105  static const struct phylink_mac_ops mtk_phylink_ops = {
 106         .validate = phylink_generic_validate,
 107 +       .mac_select_pcs = mtk_mac_select_pcs,
 108         .mac_pcs_get_state = mtk_mac_pcs_get_state,
 109 -       .mac_an_restart = mtk_mac_an_restart,
 110         .mac_config = mtk_mac_config,
 111         .mac_finish = mtk_mac_finish,
 112         .mac_link_down = mtk_mac_link_down,
 113 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 114 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 115 @@ -964,10 +964,12 @@ struct mtk_soc_data {
 116   * @regmap:            The register map pointing at the range used to setup
 117   *                     SGMII modes
 118   * @ana_rgc3:          The offset refers to register ANA_RGC3 related to regmap
 119 + * @pcs:               Phylink PCS structure
 120   */
 121  struct mtk_pcs {
 122         struct regmap   *regmap;
 123         u32             ana_rgc3;
 124 +       struct phylink_pcs pcs;
 125  };
 126
 127  /* struct mtk_sgmii -  This is the structure holding sgmii regmap and its
 128 @@ -1107,12 +1109,9 @@ void mtk_stats_update_mac(struct mtk_mac
 129  void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
 130  u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
 131
 132 +struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id);
 133  int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
 134                    u32 ana_rgc3);
 135 -int mtk_sgmii_config(struct mtk_sgmii *ss, int id, unsigned int mode,
 136 -                    phy_interface_t interface);
 137 -void mtk_sgmii_link_up(struct mtk_sgmii *ss, int id, int speed, int duplex);
 138 -void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id);
 139
 140  int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
 141  int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
 142 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
 143 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
 144 @@ -14,14 +14,16 @@
 145
 146  #include "mtk_eth_soc.h"
 147
 148 +static struct mtk_pcs *pcs_to_mtk_pcs(struct phylink_pcs *pcs)
 149 +{
 150 +       return container_of(pcs, struct mtk_pcs, pcs);
 151 +}
 152 +
 153  /* For SGMII interface mode */
 154  static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs)
 155  {
 156         unsigned int val;
 157
 158 -       if (!mpcs->regmap)
 159 -               return -EINVAL;
 160 -
 161         /* Setup the link timer and QPHY power up inside SGMIISYS */
 162         regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
 163                      SGMII_LINK_TIMER_DEFAULT);
 164 @@ -50,9 +52,6 @@ static int mtk_pcs_setup_mode_force(stru
 165  {
 166         unsigned int val;
 167
 168 -       if (!mpcs->regmap)
 169 -               return -EINVAL;
 170 -
 171         regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
 172         val &= ~RG_PHY_SPEED_MASK;
 173         if (interface == PHY_INTERFACE_MODE_2500BASEX)
 174 @@ -78,10 +77,12 @@ static int mtk_pcs_setup_mode_force(stru
 175         return 0;
 176  }
 177
 178 -int mtk_sgmii_config(struct mtk_sgmii *ss, int id, unsigned int mode,
 179 -                    phy_interface_t interface)
 180 +static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
 181 +                         phy_interface_t interface,
 182 +                         const unsigned long *advertising,
 183 +                         bool permit_pause_to_mac)
 184  {
 185 -       struct mtk_pcs *mpcs = &ss->pcs[id];
 186 +       struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
 187         int err = 0;
 188
 189         /* Setup SGMIISYS with the determined property */
 190 @@ -93,22 +94,25 @@ int mtk_sgmii_config(struct mtk_sgmii *s
 191         return err;
 192  }
 193
 194 -static void mtk_pcs_restart_an(struct mtk_pcs *mpcs)
 195 +static void mtk_pcs_restart_an(struct phylink_pcs *pcs)
 196  {
 197 +       struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
 198         unsigned int val;
 199
 200 -       if (!mpcs->regmap)
 201 -               return;
 202 -
 203         regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
 204         val |= SGMII_AN_RESTART;
 205         regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
 206  }
 207
 208 -static void mtk_pcs_link_up(struct mtk_pcs *mpcs, int speed, int duplex)
 209 +static void mtk_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
 210 +                           phy_interface_t interface, int speed, int duplex)
 211  {
 212 +       struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
 213         unsigned int val;
 214
 215 +       if (!phy_interface_mode_is_8023z(interface))
 216 +               return;
 217 +
 218         /* SGMII force duplex setting */
 219         regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
 220         val &= ~SGMII_DUPLEX_FULL;
 221 @@ -118,11 +122,11 @@ static void mtk_pcs_link_up(struct mtk_p
 222         regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
 223  }
 224
 225 -/* For 1000BASE-X and 2500BASE-X interface modes */
 226 -void mtk_sgmii_link_up(struct mtk_sgmii *ss, int id, int speed, int duplex)
 227 -{
 228 -       mtk_pcs_link_up(&ss->pcs[id], speed, duplex);
 229 -}
 230 +static const struct phylink_pcs_ops mtk_pcs_ops = {
 231 +       .pcs_config = mtk_pcs_config,
 232 +       .pcs_an_restart = mtk_pcs_restart_an,
 233 +       .pcs_link_up = mtk_pcs_link_up,
 234 +};
 235
 236  int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
 237  {
 238 @@ -139,18 +143,17 @@ int mtk_sgmii_init(struct mtk_sgmii *ss,
 239                 of_node_put(np);
 240                 if (IS_ERR(ss->pcs[i].regmap))
 241                         return PTR_ERR(ss->pcs[i].regmap);
 242 +
 243 +               ss->pcs[i].pcs.ops = &mtk_pcs_ops;
 244         }
 245
 246         return 0;
 247  }
 248
 249 -void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id)
 250 +struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id)
 251  {
 252 -       unsigned int sid;
 253 -
 254 -       /* Decide how GMAC and SGMIISYS be mapped */
 255 -       sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
 256 -              0 : mac_id;
 257 +       if (!ss->pcs[id].regmap)
 258 +               return NULL;
 259
 260 -       mtk_pcs_restart_an(&eth->sgmii->pcs[sid]);
 261 +       return &ss->pcs[id].pcs;
 262  }