target/linux/sunxi/patches-5.4/440-add-h6-pwm.patch

   1 --- a/drivers/pwm/pwm-sun4i.c
   2 +++ b/drivers/pwm/pwm-sun4i.c
   3 @@ -3,6 +3,10 @@
   4   * Driver for Allwinner sun4i Pulse Width Modulation Controller
   5   *
   6   * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
   7 + *
   8 + * Limitations:
   9 + * - When outputing the source clock directly, the PWM logic will be bypassed
  10 + *   and the currently running period is not guaranteed to be completed
  11   */
  12
  13  #include <linux/bitops.h>
  14 @@ -16,6 +20,7 @@
  15  #include <linux/of_device.h>
  16  #include <linux/platform_device.h>
  17  #include <linux/pwm.h>
  18 +#include <linux/reset.h>
  19  #include <linux/slab.h>
  20  #include <linux/spinlock.h>
  21  #include <linux/time.h>
  22 @@ -72,12 +77,15 @@ static const u32 prescaler_table[] = {
  23
  24  struct sun4i_pwm_data {
  25         bool has_prescaler_bypass;
  26 +       bool has_direct_mod_clk_output;
  27         unsigned int npwm;
  28  };
  29
  30  struct sun4i_pwm_chip {
  31         struct pwm_chip chip;
  32 +       struct clk *bus_clk;
  33         struct clk *clk;
  34 +       struct reset_control *rst;
  35         void __iomem *base;
  36         spinlock_t ctrl_lock;
  37         const struct sun4i_pwm_data *data;
  38 @@ -115,6 +123,20 @@ static void sun4i_pwm_get_state(struct p
  39
  40         val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
  41
  42 +       /*
  43 +        * PWM chapter in H6 manual has a diagram which explains that if bypass
  44 +        * bit is set, no other setting has any meaning. Even more, experiment
  45 +        * proved that also enable bit is ignored in this case.
  46 +        */
  47 +       if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
  48 +           sun4i_pwm->data->has_direct_mod_clk_output) {
  49 +               state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
  50 +               state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
  51 +               state->polarity = PWM_POLARITY_NORMAL;
  52 +               state->enabled = true;
  53 +               return;
  54 +       }
  55 +
  56         if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
  57             sun4i_pwm->data->has_prescaler_bypass)
  58                 prescaler = 1;
  59 @@ -146,13 +168,24 @@ static void sun4i_pwm_get_state(struct p
  60
  61  static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
  62                                const struct pwm_state *state,
  63 -                              u32 *dty, u32 *prd, unsigned int *prsclr)
  64 +                              u32 *dty, u32 *prd, unsigned int *prsclr,
  65 +                              bool *bypass)
  66  {
  67         u64 clk_rate, div = 0;
  68         unsigned int pval, prescaler = 0;
  69
  70         clk_rate = clk_get_rate(sun4i_pwm->clk);
  71
  72 +       *bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
  73 +                 state->enabled &&
  74 +                 (state->period * clk_rate >= NSEC_PER_SEC) &&
  75 +                 (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
  76 +                 (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
  77 +
  78 +       /* Skip calculation of other parameters if we bypass them */
  79 +       if (*bypass)
  80 +               return 0;
  81 +
  82         if (sun4i_pwm->data->has_prescaler_bypass) {
  83                 /* First, test without any prescaler when available */
  84                 prescaler = PWM_PRESCAL_MASK;
  85 @@ -200,10 +233,11 @@ static int sun4i_pwm_apply(struct pwm_ch
  86  {
  87         struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
  88         struct pwm_state cstate;
  89 -       u32 ctrl;
  90 +       u32 ctrl, duty, period, val;
  91         int ret;
  92 -       unsigned int delay_us;
  93 +       unsigned int delay_us, prescaler;
  94         unsigned long now;
  95 +       bool bypass;
  96
  97         pwm_get_state(pwm, &cstate);
  98
  99 @@ -218,43 +252,50 @@ static int sun4i_pwm_apply(struct pwm_ch
 100         spin_lock(&sun4i_pwm->ctrl_lock);
 101         ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 102
 103 -       if ((cstate.period != state->period) ||
 104 -           (cstate.duty_cycle != state->duty_cycle)) {
 105 -               u32 period, duty, val;
 106 -               unsigned int prescaler;
 107 +       ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
 108 +                                 &bypass);
 109 +       if (ret) {
 110 +               dev_err(chip->dev, "period exceeds the maximum value\n");
 111 +               spin_unlock(&sun4i_pwm->ctrl_lock);
 112 +               if (!cstate.enabled)
 113 +                       clk_disable_unprepare(sun4i_pwm->clk);
 114 +               return ret;
 115 +       }
 116
 117 -               ret = sun4i_pwm_calculate(sun4i_pwm, state,
 118 -                                         &duty, &period, &prescaler);
 119 -               if (ret) {
 120 -                       dev_err(chip->dev, "period exceeds the maximum value\n");
 121 +       if (sun4i_pwm->data->has_direct_mod_clk_output) {
 122 +               if (bypass) {
 123 +                       ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
 124 +                       /* We can skip other parameter */
 125 +                       sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
 126                         spin_unlock(&sun4i_pwm->ctrl_lock);
 127 -                       if (!cstate.enabled)
 128 -                               clk_disable_unprepare(sun4i_pwm->clk);
 129 -                       return ret;
 130 +                       return 0;
 131 +               } else {
 132 +                       ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
 133                 }
 134 +       }
 135
 136 -               if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
 137 -                       /* Prescaler changed, the clock has to be gated */
 138 -                       ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 139 -                       sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
 140 -
 141 -                       ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
 142 -                       ctrl |= BIT_CH(prescaler, pwm->hwpwm);
 143 -               }
 144 +       if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
 145 +               /* Prescaler changed, the clock has to be gated */
 146 +               ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 147 +               sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
 148
 149 -               val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
 150 -               sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
 151 -               sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
 152 -                       usecs_to_jiffies(cstate.period / 1000 + 1);
 153 -               sun4i_pwm->needs_delay[pwm->hwpwm] = true;
 154 +               ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
 155 +               ctrl |= BIT_CH(prescaler, pwm->hwpwm);
 156         }
 157
 158 +       val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
 159 +       sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
 160 +       sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
 161 +               usecs_to_jiffies(cstate.period / 1000 + 1);
 162 +       sun4i_pwm->needs_delay[pwm->hwpwm] = true;
 163 +
 164         if (state->polarity != PWM_POLARITY_NORMAL)
 165                 ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
 166         else
 167                 ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
 168
 169         ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 170 +
 171         if (state->enabled) {
 172                 ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
 173         } else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
 174 @@ -320,6 +361,12 @@ static const struct sun4i_pwm_data sun4i
 175         .npwm = 1,
 176  };
 177
 178 +static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
 179 +       .has_prescaler_bypass = true,
 180 +       .has_direct_mod_clk_output = true,
 181 +       .npwm = 2,
 182 +};
 183 +
 184  static const struct of_device_id sun4i_pwm_dt_ids[] = {
 185         {
 186                 .compatible = "allwinner,sun4i-a10-pwm",
 187 @@ -337,6 +384,9 @@ static const struct of_device_id sun4i_p
 188                 .compatible = "allwinner,sun8i-h3-pwm",
 189                 .data = &sun4i_pwm_single_bypass,
 190         }, {
 191 +               .compatible = "allwinner,sun50i-h6-pwm",
 192 +               .data = &sun50i_h6_pwm_data,
 193 +       }, {
 194                 /* sentinel */
 195         },
 196  };
 197 @@ -361,9 +411,69 @@ static int sun4i_pwm_probe(struct platfo
 198         if (IS_ERR(pwm->base))
 199                 return PTR_ERR(pwm->base);
 200
 201 -       pwm->clk = devm_clk_get(&pdev->dev, NULL);
 202 -       if (IS_ERR(pwm->clk))
 203 +       /*
 204 +        * All hardware variants need a source clock that is divided and
 205 +        * then feeds the counter that defines the output wave form. In the
 206 +        * device tree this clock is either unnamed or called "mod".
 207 +        * Some variants (e.g. H6) need another clock to access the
 208 +        * hardware registers; this is called "bus".
 209 +        * So we request "mod" first (and ignore the corner case that a
 210 +        * parent provides a "mod" clock while the right one would be the
 211 +        * unnamed one of the PWM device) and if this is not found we fall
 212 +        * back to the first clock of the PWM.
 213 +        */
 214 +       pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
 215 +       if (IS_ERR(pwm->clk)) {
 216 +               if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
 217 +                       dev_err(&pdev->dev, "get mod clock failed %pe\n",
 218 +                               pwm->clk);
 219                 return PTR_ERR(pwm->clk);
 220 +       }
 221 +
 222 +       if (!pwm->clk) {
 223 +               pwm->clk = devm_clk_get(&pdev->dev, NULL);
 224 +               if (IS_ERR(pwm->clk)) {
 225 +                       if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
 226 +                               dev_err(&pdev->dev, "get unnamed clock failed %pe\n",
 227 +                                       pwm->clk);
 228 +                       return PTR_ERR(pwm->clk);
 229 +               }
 230 +       }
 231 +
 232 +       pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
 233 +       if (IS_ERR(pwm->bus_clk)) {
 234 +               if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
 235 +                       dev_err(&pdev->dev, "get bus clock failed %pe\n",
 236 +                               pwm->bus_clk);
 237 +               return PTR_ERR(pwm->bus_clk);
 238 +       }
 239 +
 240 +       pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
 241 +       if (IS_ERR(pwm->rst)) {
 242 +               if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
 243 +                       dev_err(&pdev->dev, "get reset failed %pe\n",
 244 +                               pwm->rst);
 245 +               return PTR_ERR(pwm->rst);
 246 +       }
 247 +
 248 +       /* Deassert reset */
 249 +       ret = reset_control_deassert(pwm->rst);
 250 +       if (ret) {
 251 +               dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
 252 +                       ERR_PTR(ret));
 253 +               return ret;
 254 +       }
 255 +
 256 +       /*
 257 +        * We're keeping the bus clock on for the sake of simplicity.
 258 +        * Actually it only needs to be on for hardware register accesses.
 259 +        */
 260 +       ret = clk_prepare_enable(pwm->bus_clk);
 261 +       if (ret) {
 262 +               dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
 263 +                       ERR_PTR(ret));
 264 +               goto err_bus;
 265 +       }
 266
 267         pwm->chip.dev = &pdev->dev;
 268         pwm->chip.ops = &sun4i_pwm_ops;
 269 @@ -377,19 +487,34 @@ static int sun4i_pwm_probe(struct platfo
 270         ret = pwmchip_add(&pwm->chip);
 271         if (ret < 0) {
 272                 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
 273 -               return ret;
 274 +               goto err_pwm_add;
 275         }
 276
 277         platform_set_drvdata(pdev, pwm);
 278
 279         return 0;
 280 +
 281 +err_pwm_add:
 282 +       clk_disable_unprepare(pwm->bus_clk);
 283 +err_bus:
 284 +       reset_control_assert(pwm->rst);
 285 +
 286 +       return ret;
 287  }
 288
 289  static int sun4i_pwm_remove(struct platform_device *pdev)
 290  {
 291         struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
 292 +       int ret;
 293 +
 294 +       ret = pwmchip_remove(&pwm->chip);
 295 +       if (ret)
 296 +               return ret;
 297
 298 -       return pwmchip_remove(&pwm->chip);
 299 +       clk_disable_unprepare(pwm->bus_clk);
 300 +       reset_control_assert(pwm->rst);
 301 +
 302 +       return 0;
 303  }
 304
 305  static struct platform_driver sun4i_pwm_driver = {