target/linux/mvebu/patches-5.4/803-Revert-cpufreq-armada-37xx-Fix-setting-TBG-parent-fo.patch

   1 From 35639bac13927d1476398b740b11cbed0ee3ddb2 Mon Sep 17 00:00:00 2001
   2 From: Robert Marko <robert.marko@sartura.hr>
   3 Date: Tue, 18 May 2021 13:24:30 +0200
   4 Subject: [PATCH] Revert "cpufreq: armada-37xx: Fix setting TBG parent for load
   5  levels"
   6
   7 This reverts commit a13b110e7c9e0dc2edcc7a19d4255fc88abd83cc.
   8
   9 This patch actually corrects the things so that 1 or 1.2GHz models would
  10 actually get scaled to their native frequency.
  11
  12 However, due to a AVS setting voltages too low this will cause random
  13 crashes on 1.2GHz models.
  14
  15 So, until a new safe for everybody voltage is agreed on
  16 lets revert the patch.
  17
  18 Signed-off-by: Robert Marko <robert.marko@sartura.hr>
  19 ---
  20  drivers/cpufreq/armada-37xx-cpufreq.c | 35 +++++++++------------------
  21  1 file changed, 12 insertions(+), 23 deletions(-)
  22
  23 --- a/drivers/cpufreq/armada-37xx-cpufreq.c
  24 +++ b/drivers/cpufreq/armada-37xx-cpufreq.c
  25 @@ -25,10 +25,6 @@
  26
  27  #include "cpufreq-dt.h"
  28
  29 -/* Clk register set */
  30 -#define ARMADA_37XX_CLK_TBG_SEL                0
  31 -#define ARMADA_37XX_CLK_TBG_SEL_CPU_OFF        22
  32 -
  33  /* Power management in North Bridge register set */
  34  #define ARMADA_37XX_NB_L0L1    0x18
  35  #define ARMADA_37XX_NB_L2L3    0x1C
  36 @@ -126,15 +122,10 @@ static struct armada_37xx_dvfs *armada_3
  37   * will be configured then the DVFS will be enabled.
  38   */
  39  static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
  40 -                                                struct regmap *clk_base, u8 *divider)
  41 +                                                struct clk *clk, u8 *divider)
  42  {
  43 -       u32 cpu_tbg_sel;
  44         int load_lvl;
  45 -
  46 -       /* Determine to which TBG clock is CPU connected */
  47 -       regmap_read(clk_base, ARMADA_37XX_CLK_TBG_SEL, &cpu_tbg_sel);
  48 -       cpu_tbg_sel >>= ARMADA_37XX_CLK_TBG_SEL_CPU_OFF;
  49 -       cpu_tbg_sel &= ARMADA_37XX_NB_TBG_SEL_MASK;
  50 +       struct clk *parent;
  51
  52         for (load_lvl = 0; load_lvl < LOAD_LEVEL_NR; load_lvl++) {
  53                 unsigned int reg, mask, val, offset = 0;
  54 @@ -153,11 +144,6 @@ static void __init armada37xx_cpufreq_dv
  55                 mask = (ARMADA_37XX_NB_CLK_SEL_MASK
  56                         << ARMADA_37XX_NB_CLK_SEL_OFF);
  57
  58 -               /* Set TBG index, for all levels we use the same TBG */
  59 -               val = cpu_tbg_sel << ARMADA_37XX_NB_TBG_SEL_OFF;
  60 -               mask = (ARMADA_37XX_NB_TBG_SEL_MASK
  61 -                       << ARMADA_37XX_NB_TBG_SEL_OFF);
  62 -
  63                 /*
  64                  * Set cpu divider based on the pre-computed array in
  65                  * order to have balanced step.
  66 @@ -176,6 +162,14 @@ static void __init armada37xx_cpufreq_dv
  67
  68                 regmap_update_bits(base, reg, mask, val);
  69         }
  70 +
  71 +       /*
  72 +        * Set cpu clock source, for all the level we keep the same
  73 +        * clock source that the one already configured. For this one
  74 +        * we need to use the clock framework
  75 +        */
  76 +       parent = clk_get_parent(clk);
  77 +       clk_set_parent(clk, parent);
  78  }
  79
  80  /*
  81 @@ -401,16 +395,11 @@ static int __init armada37xx_cpufreq_dri
  82         struct platform_device *pdev;
  83         unsigned long freq;
  84         unsigned int cur_frequency, base_frequency;
  85 -       struct regmap *nb_clk_base, *nb_pm_base, *avs_base;
  86 +       struct regmap *nb_pm_base, *avs_base;
  87         struct device *cpu_dev;
  88         int load_lvl, ret;
  89         struct clk *clk, *parent;
  90
  91 -       nb_clk_base =
  92 -               syscon_regmap_lookup_by_compatible("marvell,armada-3700-periph-clock-nb");
  93 -       if (IS_ERR(nb_clk_base))
  94 -               return -ENODEV;
  95 -
  96         nb_pm_base =
  97                 syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
  98
  99 @@ -487,7 +476,7 @@ static int __init armada37xx_cpufreq_dri
 100         armada37xx_cpufreq_avs_configure(avs_base, dvfs);
 101         armada37xx_cpufreq_avs_setup(avs_base, dvfs);
 102
 103 -       armada37xx_cpufreq_dvfs_setup(nb_pm_base, nb_clk_base, dvfs->divider);
 104 +       armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider);
 105         clk_put(clk);
 106
 107         for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;