layerscape: add patches-5.4
[openwrt/staging/mkresin.git] / target / linux / layerscape / patches-5.4 / 804-crypto-0026-crypto-caam-qi2-add-OPR-Order-Preservation-support.patch
1 From 70eb620ed6d38e171e5619313e99d31688d25010 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Horia=20Geant=C4=83?= <horia.geanta@nxp.com>
3 Date: Wed, 10 Oct 2018 16:07:50 +0300
4 Subject: [PATCH] crypto: caam/qi2 - add OPR (Order Preservation) support
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 During driver upstreaming OPR was removed due to lacking users.
10 Add OPR back, since in LSDK / LSDK-based ADKs there is at least
11 one user (ASF / VortiQa IPsec).
12
13 Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
14 ---
15 drivers/crypto/caam/dpseci.c | 85 ++++++++++++++++++++++++++++++++++++++++
16 drivers/crypto/caam/dpseci.h | 26 +++++++++++-
17 drivers/crypto/caam/dpseci_cmd.h | 51 ++++++++++++++++++++++++
18 3 files changed, 160 insertions(+), 2 deletions(-)
19
20 --- a/drivers/crypto/caam/dpseci.c
21 +++ b/drivers/crypto/caam/dpseci.c
22 @@ -5,6 +5,7 @@
23 */
24
25 #include <linux/fsl/mc.h>
26 +#include <soc/fsl/dpaa2-io.h>
27 #include "dpseci.h"
28 #include "dpseci_cmd.h"
29
30 @@ -675,6 +676,90 @@ int dpseci_get_api_version(struct fsl_mc
31
32 return 0;
33 }
34 +
35 +/**
36 + * dpseci_set_opr() - Set Order Restoration configuration
37 + * @mc_io: Pointer to MC portal's I/O object
38 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
39 + * @token: Token of DPSECI object
40 + * @index: The queue index
41 + * @options: Configuration mode options; can be OPR_OPT_CREATE or
42 + * OPR_OPT_RETIRE
43 + * @cfg: Configuration options for the OPR
44 + *
45 + * Return: '0' on success, error code otherwise
46 + */
47 +int dpseci_set_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index,
48 + u8 options, struct opr_cfg *cfg)
49 +{
50 + struct fsl_mc_command cmd = { 0 };
51 + struct dpseci_cmd_opr *cmd_params;
52 +
53 + cmd.header = mc_encode_cmd_header(
54 + DPSECI_CMDID_SET_OPR,
55 + cmd_flags,
56 + token);
57 + cmd_params = (struct dpseci_cmd_opr *)cmd.params;
58 + cmd_params->index = index;
59 + cmd_params->options = options;
60 + cmd_params->oloe = cfg->oloe;
61 + cmd_params->oeane = cfg->oeane;
62 + cmd_params->olws = cfg->olws;
63 + cmd_params->oa = cfg->oa;
64 + cmd_params->oprrws = cfg->oprrws;
65 +
66 + return mc_send_command(mc_io, &cmd);
67 +}
68 +
69 +/**
70 + * dpseci_get_opr() - Retrieve Order Restoration config and query
71 + * @mc_io: Pointer to MC portal's I/O object
72 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
73 + * @token: Token of DPSECI object
74 + * @index: The queue index
75 + * @cfg: Returned OPR configuration
76 + * @qry: Returned OPR query
77 + *
78 + * Return: '0' on success, error code otherwise
79 + */
80 +int dpseci_get_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index,
81 + struct opr_cfg *cfg, struct opr_qry *qry)
82 +{
83 + struct fsl_mc_command cmd = { 0 };
84 + struct dpseci_cmd_opr *cmd_params;
85 + struct dpseci_rsp_get_opr *rsp_params;
86 + int err;
87 +
88 + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_OPR,
89 + cmd_flags,
90 + token);
91 + cmd_params = (struct dpseci_cmd_opr *)cmd.params;
92 + cmd_params->index = index;
93 + err = mc_send_command(mc_io, &cmd);
94 + if (err)
95 + return err;
96 +
97 + rsp_params = (struct dpseci_rsp_get_opr *)cmd.params;
98 + qry->rip = dpseci_get_field(rsp_params->flags, OPR_RIP);
99 + qry->enable = dpseci_get_field(rsp_params->flags, OPR_ENABLE);
100 + cfg->oloe = rsp_params->oloe;
101 + cfg->oeane = rsp_params->oeane;
102 + cfg->olws = rsp_params->olws;
103 + cfg->oa = rsp_params->oa;
104 + cfg->oprrws = rsp_params->oprrws;
105 + qry->nesn = le16_to_cpu(rsp_params->nesn);
106 + qry->ndsn = le16_to_cpu(rsp_params->ndsn);
107 + qry->ea_tseq = le16_to_cpu(rsp_params->ea_tseq);
108 + qry->tseq_nlis = dpseci_get_field(rsp_params->tseq_nlis, OPR_TSEQ_NLIS);
109 + qry->ea_hseq = le16_to_cpu(rsp_params->ea_hseq);
110 + qry->hseq_nlis = dpseci_get_field(rsp_params->hseq_nlis, OPR_HSEQ_NLIS);
111 + qry->ea_hptr = le16_to_cpu(rsp_params->ea_hptr);
112 + qry->ea_tptr = le16_to_cpu(rsp_params->ea_tptr);
113 + qry->opr_vid = le16_to_cpu(rsp_params->opr_vid);
114 + qry->opr_id = le16_to_cpu(rsp_params->opr_id);
115 +
116 + return 0;
117 +}
118
119 /**
120 * dpseci_set_congestion_notification() - Set congestion group
121 --- a/drivers/crypto/caam/dpseci.h
122 +++ b/drivers/crypto/caam/dpseci.h
123 @@ -12,6 +12,8 @@
124 */
125
126 struct fsl_mc_io;
127 +struct opr_cfg;
128 +struct opr_qry;
129
130 /**
131 * General DPSECI macros
132 @@ -38,9 +40,21 @@ int dpseci_close(struct fsl_mc_io *mc_io
133 #define DPSECI_OPT_HAS_CG 0x000020
134
135 /**
136 + * Enable the Order Restoration support
137 + */
138 +#define DPSECI_OPT_HAS_OPR 0x000040
139 +
140 +/**
141 + * Order Point Records are shared for the entire DPSECI
142 + */
143 +#define DPSECI_OPT_OPR_SHARED 0x000080
144 +
145 +/**
146 * struct dpseci_cfg - Structure representing DPSECI configuration
147 - * @options: Any combination of the following flags:
148 + * @options: Any combination of the following options:
149 * DPSECI_OPT_HAS_CG
150 + * DPSECI_OPT_HAS_OPR
151 + * DPSECI_OPT_OPR_SHARED
152 * @num_tx_queues: num of queues towards the SEC
153 * @num_rx_queues: num of queues back from the SEC
154 * @priorities: Priorities for the SEC hardware processing;
155 @@ -93,8 +107,10 @@ int dpseci_clear_irq_status(struct fsl_m
156 * @id: DPSECI object ID
157 * @num_tx_queues: number of queues towards the SEC
158 * @num_rx_queues: number of queues back from the SEC
159 - * @options: any combination of the following flags:
160 + * @options: any combination of the following options:
161 * DPSECI_OPT_HAS_CG
162 + * DPSECI_OPT_HAS_OPR
163 + * DPSECI_OPT_OPR_SHARED
164 */
165 struct dpseci_attr {
166 int id;
167 @@ -301,6 +317,12 @@ int dpseci_get_sec_counters(struct fsl_m
168 int dpseci_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
169 u16 *major_ver, u16 *minor_ver);
170
171 +int dpseci_set_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index,
172 + u8 options, struct opr_cfg *cfg);
173 +
174 +int dpseci_get_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index,
175 + struct opr_cfg *cfg, struct opr_qry *qry);
176 +
177 /**
178 * enum dpseci_congestion_unit - DPSECI congestion units
179 * @DPSECI_CONGESTION_UNIT_BYTES: bytes units
180 --- a/drivers/crypto/caam/dpseci_cmd.h
181 +++ b/drivers/crypto/caam/dpseci_cmd.h
182 @@ -54,6 +54,8 @@
183 #define DPSECI_CMDID_GET_TX_QUEUE DPSECI_CMD_V1(0x197)
184 #define DPSECI_CMDID_GET_SEC_ATTR DPSECI_CMD_V2(0x198)
185 #define DPSECI_CMDID_GET_SEC_COUNTERS DPSECI_CMD_V1(0x199)
186 +#define DPSECI_CMDID_SET_OPR DPSECI_CMD_V1(0x19A)
187 +#define DPSECI_CMDID_GET_OPR DPSECI_CMD_V1(0x19B)
188 #define DPSECI_CMDID_SET_CONGESTION_NOTIFICATION DPSECI_CMD_V1(0x170)
189 #define DPSECI_CMDID_GET_CONGESTION_NOTIFICATION DPSECI_CMD_V1(0x171)
190
191 @@ -189,6 +191,55 @@ struct dpseci_rsp_get_api_version {
192 __le16 minor;
193 };
194
195 +struct dpseci_cmd_opr {
196 + __le16 pad;
197 + u8 index;
198 + u8 options;
199 + u8 pad1[7];
200 + u8 oloe;
201 + u8 oeane;
202 + u8 olws;
203 + u8 oa;
204 + u8 oprrws;
205 +};
206 +
207 +#define DPSECI_OPR_RIP_SHIFT 0
208 +#define DPSECI_OPR_RIP_SIZE 1
209 +#define DPSECI_OPR_ENABLE_SHIFT 1
210 +#define DPSECI_OPR_ENABLE_SIZE 1
211 +#define DPSECI_OPR_TSEQ_NLIS_SHIFT 0
212 +#define DPSECI_OPR_TSEQ_NLIS_SIZE 1
213 +#define DPSECI_OPR_HSEQ_NLIS_SHIFT 0
214 +#define DPSECI_OPR_HSEQ_NLIS_SIZE 1
215 +
216 +struct dpseci_rsp_get_opr {
217 + __le64 pad;
218 + u8 flags;
219 + u8 pad0[2];
220 + u8 oloe;
221 + u8 oeane;
222 + u8 olws;
223 + u8 oa;
224 + u8 oprrws;
225 + __le16 nesn;
226 + __le16 pad1;
227 + __le16 ndsn;
228 + __le16 pad2;
229 + __le16 ea_tseq;
230 + u8 tseq_nlis;
231 + u8 pad3;
232 + __le16 ea_hseq;
233 + u8 hseq_nlis;
234 + u8 pad4;
235 + __le16 ea_hptr;
236 + __le16 pad5;
237 + __le16 ea_tptr;
238 + __le16 pad6;
239 + __le16 opr_vid;
240 + __le16 pad7;
241 + __le16 opr_id;
242 +};
243 +
244 #define DPSECI_CGN_DEST_TYPE_SHIFT 0
245 #define DPSECI_CGN_DEST_TYPE_SIZE 4
246 #define DPSECI_CGN_UNITS_SHIFT 4