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[openwrt/staging/mkresin.git] / target / linux / layerscape / patches-5.4 / 801-audio-0027-MLK-15140-1-ASoC-fsl_sai-support-latest-sai-module.patch
1 From 21cf15cd000ba45bc02b8bfcf59df1e13bfdb803 Mon Sep 17 00:00:00 2001
2 From: Shengjiu Wang <shengjiu.wang@freescale.com>
3 Date: Thu, 22 Jun 2017 15:39:24 +0800
4 Subject: [PATCH] MLK-15140-1: ASoC: fsl_sai: support latest sai module
5
6 The version of sai is upgrate in imx8mq, which add two register
7 in beginning, there is VERID and PARAM. the driver need to be
8 update
9
10 Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
11 Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
12 ---
13 sound/soc/fsl/fsl_sai.c | 273 ++++++++++++++++++++++++++++--------------------
14 sound/soc/fsl/fsl_sai.h | 43 ++++----
15 2 files changed, 180 insertions(+), 136 deletions(-)
16
17 --- a/sound/soc/fsl/fsl_sai.c
18 +++ b/sound/soc/fsl/fsl_sai.c
19 @@ -43,6 +43,7 @@ static struct fsl_sai_soc_data fsl_sai_i
20 .fifos = 1,
21 .fifo_depth = 32,
22 .flags = 0,
23 + .reg_offset = 0,
24 };
25
26 static struct fsl_sai_soc_data fsl_sai_imx6ul = {
27 @@ -51,6 +52,7 @@ static struct fsl_sai_soc_data fsl_sai_i
28 .fifos = 1,
29 .fifo_depth = 32,
30 .flags = 0,
31 + .reg_offset = 0,
32 };
33
34 static struct fsl_sai_soc_data fsl_sai_imx7ulp = {
35 @@ -59,6 +61,16 @@ static struct fsl_sai_soc_data fsl_sai_i
36 .fifos = 2,
37 .fifo_depth = 16,
38 .flags = SAI_FLAG_PMQOS,
39 + .reg_offset = 0,
40 +};
41 +
42 +static struct fsl_sai_soc_data fsl_sai_imx8mq = {
43 + .imx = true,
44 + .dataline = 0xff,
45 + .fifos = 8,
46 + .fifo_depth = 32,
47 + .flags = 0,
48 + .reg_offset = 8,
49 };
50
51 static const unsigned int fsl_sai_rates[] = {
52 @@ -75,6 +87,7 @@ static const struct snd_pcm_hw_constrain
53 static irqreturn_t fsl_sai_isr(int irq, void *devid)
54 {
55 struct fsl_sai *sai = (struct fsl_sai *)devid;
56 + unsigned char offset = sai->soc->reg_offset;
57 struct device *dev = &sai->pdev->dev;
58 u32 flags, xcsr, mask;
59 bool irq_none = true;
60 @@ -87,7 +100,7 @@ static irqreturn_t fsl_sai_isr(int irq,
61 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
62
63 /* Tx IRQ */
64 - regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
65 + regmap_read(sai->regmap, FSL_SAI_TCSR(offset), &xcsr);
66 flags = xcsr & mask;
67
68 if (flags)
69 @@ -117,11 +130,11 @@ static irqreturn_t fsl_sai_isr(int irq,
70 xcsr &= ~FSL_SAI_CSR_xF_MASK;
71
72 if (flags)
73 - regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);
74 + regmap_write(sai->regmap, FSL_SAI_TCSR(offset), flags | xcsr);
75
76 irq_rx:
77 /* Rx IRQ */
78 - regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr);
79 + regmap_read(sai->regmap, FSL_SAI_RCSR(offset), &xcsr);
80 flags = xcsr & mask;
81
82 if (flags)
83 @@ -151,7 +164,7 @@ irq_rx:
84 xcsr &= ~FSL_SAI_CSR_xF_MASK;
85
86 if (flags)
87 - regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr);
88 + regmap_write(sai->regmap, FSL_SAI_RCSR(offset), flags | xcsr);
89
90 out:
91 if (irq_none)
92 @@ -175,6 +188,7 @@ static int fsl_sai_set_dai_sysclk_tr(str
93 int clk_id, unsigned int freq, int fsl_dir)
94 {
95 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
96 + unsigned char offset = sai->soc->reg_offset;
97 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
98 u32 val_cr2 = 0;
99
100 @@ -195,7 +209,7 @@ static int fsl_sai_set_dai_sysclk_tr(str
101 return -EINVAL;
102 }
103
104 - regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
105 + regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, offset),
106 FSL_SAI_CR2_MSEL_MASK, val_cr2);
107
108 return 0;
109 @@ -228,6 +242,7 @@ static int fsl_sai_set_dai_fmt_tr(struct
110 unsigned int fmt, int fsl_dir)
111 {
112 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
113 + unsigned char offset = sai->soc->reg_offset;
114 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
115 u32 val_cr2 = 0, val_cr4 = 0;
116
117 @@ -324,9 +339,9 @@ static int fsl_sai_set_dai_fmt_tr(struct
118 return -EINVAL;
119 }
120
121 - regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
122 + regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, offset),
123 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
124 - regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
125 + regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, offset),
126 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
127 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
128
129 @@ -362,6 +377,7 @@ static int fsl_sai_set_dai_fmt(struct sn
130 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
131 {
132 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
133 + unsigned char offset = sai->soc->reg_offset;
134 unsigned long clk_rate;
135 u32 savediv = 0, ratio, savesub = freq;
136 u32 id;
137 @@ -424,17 +440,17 @@ static int fsl_sai_set_bclk(struct snd_s
138 */
139 if ((sai->synchronous[TX] && !sai->synchronous[RX]) ||
140 (!tx && !sai->synchronous[RX])) {
141 - regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
142 + regmap_update_bits(sai->regmap, FSL_SAI_RCR2(offset),
143 FSL_SAI_CR2_MSEL_MASK,
144 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
145 - regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
146 + regmap_update_bits(sai->regmap, FSL_SAI_RCR2(offset),
147 FSL_SAI_CR2_DIV_MASK, savediv - 1);
148 } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) ||
149 (tx && !sai->synchronous[TX])) {
150 - regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
151 + regmap_update_bits(sai->regmap, FSL_SAI_TCR2(offset),
152 FSL_SAI_CR2_MSEL_MASK,
153 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
154 - regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
155 + regmap_update_bits(sai->regmap, FSL_SAI_TCR2(offset),
156 FSL_SAI_CR2_DIV_MASK, savediv - 1);
157 }
158
159 @@ -449,6 +465,7 @@ static int fsl_sai_hw_params(struct snd_
160 struct snd_soc_dai *cpu_dai)
161 {
162 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
163 + unsigned char offset = sai->soc->reg_offset;
164 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
165 unsigned int channels = params_channels(params);
166 u32 word_width = params_width(params);
167 @@ -501,49 +518,35 @@ static int fsl_sai_hw_params(struct snd_
168
169 if (!sai->slave_mode[tx]) {
170 if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
171 - regmap_update_bits(sai->regmap, FSL_SAI_TCR4,
172 + regmap_update_bits(sai->regmap, FSL_SAI_TCR4(offset),
173 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
174 val_cr4);
175 - regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
176 + regmap_update_bits(sai->regmap, FSL_SAI_TCR5(offset),
177 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
178 FSL_SAI_CR5_FBT_MASK, val_cr5);
179 } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
180 - regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
181 + regmap_update_bits(sai->regmap, FSL_SAI_RCR4(offset),
182 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
183 val_cr4);
184 - regmap_update_bits(sai->regmap, FSL_SAI_RCR5,
185 + regmap_update_bits(sai->regmap, FSL_SAI_RCR5(offset),
186 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
187 FSL_SAI_CR5_FBT_MASK, val_cr5);
188 }
189 }
190
191 if (sai->soc->dataline != 0x1) {
192 - switch (sai->dataline[tx]) {
193 - case 0x0:
194 - break;
195 - case 0x1:
196 - regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
197 - FSL_SAI_CR4_FCOMB_SOFT | FSL_SAI_CR4_FCOMB_SHIFT, 0);
198 - break;
199 - case 0x2:
200 - regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
201 - FSL_SAI_CR4_FCOMB_SOFT | FSL_SAI_CR4_FCOMB_SHIFT,
202 - FSL_SAI_CR4_FCOMB_SOFT | FSL_SAI_CR4_FCOMB_SHIFT);
203 - break;
204 - case 0x3:
205 - regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
206 - FSL_SAI_CR4_FCOMB_SOFT | FSL_SAI_CR4_FCOMB_SHIFT,
207 - FSL_SAI_CR4_FCOMB_SOFT);
208 - break;
209 - default:
210 - break;
211 - }
212 + if (sai->dataline[tx] <= 1)
213 + regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, offset),
214 + FSL_SAI_CR4_FCOMB_MASK, 0);
215 + else
216 + regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, offset),
217 + FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT);
218 }
219
220 - regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
221 + regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, offset),
222 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
223 val_cr4);
224 - regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
225 + regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, offset),
226 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
227 FSL_SAI_CR5_FBT_MASK, val_cr5);
228 regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
229 @@ -571,6 +574,7 @@ static int fsl_sai_trigger(struct snd_pc
230 struct snd_soc_dai *cpu_dai)
231 {
232 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
233 + unsigned char offset = sai->soc->reg_offset;
234 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
235 u8 channels = substream->runtime->channels;
236 u32 xcsr, count = 100;
237 @@ -581,9 +585,9 @@ static int fsl_sai_trigger(struct snd_pc
238 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
239 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
240 */
241 - regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC,
242 + regmap_update_bits(sai->regmap, FSL_SAI_TCR2(offset), FSL_SAI_CR2_SYNC,
243 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
244 - regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
245 + regmap_update_bits(sai->regmap, FSL_SAI_RCR2(offset), FSL_SAI_CR2_SYNC,
246 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
247
248 /*
249 @@ -599,49 +603,50 @@ static int fsl_sai_trigger(struct snd_pc
250 if (tx)
251 udelay(10);
252
253 - regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
254 + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset),
255 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
256 - regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
257 +
258 + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset),
259 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
260 - regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
261 + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset),
262 FSL_SAI_CSR_SE, FSL_SAI_CSR_SE);
263 if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
264 - regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx)),
265 + regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), offset),
266 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
267 } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
268 - regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx)),
269 + regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), offset),
270 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
271 }
272
273 - regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
274 + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset),
275 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
276 break;
277 case SNDRV_PCM_TRIGGER_STOP:
278 case SNDRV_PCM_TRIGGER_SUSPEND:
279 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
280 - regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
281 + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset),
282 FSL_SAI_CSR_FRDE, 0);
283 - regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
284 + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, offset),
285 FSL_SAI_CSR_xIE_MASK, 0);
286
287 /* Check if the opposite FRDE is also disabled */
288 - regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr);
289 + regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, offset), &xcsr);
290 if (!(xcsr & FSL_SAI_CSR_FRDE)) {
291 /* Disable both directions and reset their FIFOs */
292 - regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
293 + regmap_update_bits(sai->regmap, FSL_SAI_TCSR(offset),
294 FSL_SAI_CSR_TERE, 0);
295 - regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
296 + regmap_update_bits(sai->regmap, FSL_SAI_RCSR(offset),
297 FSL_SAI_CSR_TERE, 0);
298
299 /* TERE will remain set till the end of current frame */
300 do {
301 udelay(10);
302 - regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr);
303 + regmap_read(sai->regmap, FSL_SAI_xCSR(tx, offset), &xcsr);
304 } while (--count && xcsr & FSL_SAI_CSR_TERE);
305
306 - regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
307 + regmap_update_bits(sai->regmap, FSL_SAI_TCSR(offset),
308 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
309 - regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
310 + regmap_update_bits(sai->regmap, FSL_SAI_RCSR(offset),
311 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
312
313 /*
314 @@ -654,12 +659,12 @@ static int fsl_sai_trigger(struct snd_pc
315 if (!sai->slave_mode[tx]) {
316 /* Software Reset for both Tx and Rx */
317 regmap_write(sai->regmap,
318 - FSL_SAI_TCSR, FSL_SAI_CSR_SR);
319 + FSL_SAI_TCSR(offset), FSL_SAI_CSR_SR);
320 regmap_write(sai->regmap,
321 - FSL_SAI_RCSR, FSL_SAI_CSR_SR);
322 + FSL_SAI_RCSR(offset), FSL_SAI_CSR_SR);
323 /* Clear SR bit to finish the reset */
324 - regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
325 - regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
326 + regmap_write(sai->regmap, FSL_SAI_TCSR(offset), 0);
327 + regmap_write(sai->regmap, FSL_SAI_RCSR(offset), 0);
328 }
329 }
330 break;
331 @@ -674,6 +679,7 @@ static int fsl_sai_startup(struct snd_pc
332 struct snd_soc_dai *cpu_dai)
333 {
334 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
335 + unsigned char offset = sai->soc->reg_offset;
336 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
337 int ret;
338
339 @@ -682,7 +688,8 @@ static int fsl_sai_startup(struct snd_pc
340 else
341 sai->is_stream_opened[tx] = true;
342
343 - regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE0|FSL_SAI_CR3_TRCE1,
344 + regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, offset),
345 + FSL_SAI_CR3_TRCE_MASK,
346 FSL_SAI_CR3_TRCE(sai->dataline[tx]));
347
348 ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
349 @@ -695,12 +702,14 @@ static void fsl_sai_shutdown(struct snd_
350 struct snd_soc_dai *cpu_dai)
351 {
352 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
353 + unsigned char offset = sai->soc->reg_offset;
354 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
355
356 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);
357
358 if (sai->is_stream_opened[tx]) {
359 - regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE0 | FSL_SAI_CR3_TRCE1, 0);
360 + regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, offset),
361 + FSL_SAI_CR3_TRCE_MASK, 0);
362 sai->is_stream_opened[tx] = false;
363 }
364 }
365 @@ -719,17 +728,18 @@ static const struct snd_soc_dai_ops fsl_
366 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
367 {
368 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
369 + unsigned char offset = sai->soc->reg_offset;
370
371 /* Software Reset for both Tx and Rx */
372 - regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
373 - regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
374 + regmap_write(sai->regmap, FSL_SAI_TCSR(offset), FSL_SAI_CSR_SR);
375 + regmap_write(sai->regmap, FSL_SAI_RCSR(offset), FSL_SAI_CSR_SR);
376 /* Clear SR bit to finish the reset */
377 - regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
378 - regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
379 + regmap_write(sai->regmap, FSL_SAI_TCSR(offset), 0);
380 + regmap_write(sai->regmap, FSL_SAI_RCSR(offset), 0);
381
382 - regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
383 + regmap_update_bits(sai->regmap, FSL_SAI_TCR1(offset), FSL_SAI_CR1_RFW_MASK,
384 sai->soc->fifo_depth - FSL_SAI_MAXBURST_TX);
385 - regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
386 + regmap_update_bits(sai->regmap, FSL_SAI_RCR1(offset), FSL_SAI_CR1_RFW_MASK,
387 FSL_SAI_MAXBURST_RX - 1);
388
389 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
390 @@ -767,41 +777,55 @@ static const struct snd_soc_component_dr
391 .name = "fsl-sai",
392 };
393
394 -static struct reg_default fsl_sai_reg_defaults[] = {
395 - {FSL_SAI_TCR1, 0},
396 - {FSL_SAI_TCR2, 0},
397 - {FSL_SAI_TCR3, 0},
398 - {FSL_SAI_TCR4, 0},
399 - {FSL_SAI_TCR5, 0},
400 +static struct reg_default fsl_sai_v2_reg_defaults[] = {
401 + {FSL_SAI_TCR1(0), 0},
402 + {FSL_SAI_TCR2(0), 0},
403 + {FSL_SAI_TCR3(0), 0},
404 + {FSL_SAI_TCR4(0), 0},
405 + {FSL_SAI_TCR5(0), 0},
406 + {FSL_SAI_TDR0, 0},
407 + {FSL_SAI_TDR1, 0},
408 + {FSL_SAI_TMR, 0},
409 + {FSL_SAI_RCR1(0), 0},
410 + {FSL_SAI_RCR2(0), 0},
411 + {FSL_SAI_RCR3(0), 0},
412 + {FSL_SAI_RCR4(0), 0},
413 + {FSL_SAI_RCR5(0), 0},
414 + {FSL_SAI_RMR, 0},
415 +};
416 +
417 +static struct reg_default fsl_sai_v3_reg_defaults[] = {
418 + {FSL_SAI_TCR1(8), 0},
419 + {FSL_SAI_TCR2(8), 0},
420 + {FSL_SAI_TCR3(8), 0},
421 + {FSL_SAI_TCR4(8), 0},
422 + {FSL_SAI_TCR5(8), 0},
423 {FSL_SAI_TDR0, 0},
424 {FSL_SAI_TDR1, 0},
425 {FSL_SAI_TMR, 0},
426 - {FSL_SAI_RCR1, 0},
427 - {FSL_SAI_RCR2, 0},
428 - {FSL_SAI_RCR3, 0},
429 - {FSL_SAI_RCR4, 0},
430 - {FSL_SAI_RCR5, 0},
431 + {FSL_SAI_RCR1(8), 0},
432 + {FSL_SAI_RCR2(8), 0},
433 + {FSL_SAI_RCR3(8), 0},
434 + {FSL_SAI_RCR4(8), 0},
435 + {FSL_SAI_RCR5(8), 0},
436 {FSL_SAI_RMR, 0},
437 };
438
439 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
440 {
441 + struct fsl_sai *sai = dev_get_drvdata(dev);
442 + unsigned char offset = sai->soc->reg_offset;
443 +
444 + if (reg >= FSL_SAI_TCSR(offset) && reg <= FSL_SAI_TCR5(offset))
445 + return true;
446 +
447 + if (reg >= FSL_SAI_RCSR(offset) && reg <= FSL_SAI_RCR5(offset))
448 + return true;
449 +
450 switch (reg) {
451 - case FSL_SAI_TCSR:
452 - case FSL_SAI_TCR1:
453 - case FSL_SAI_TCR2:
454 - case FSL_SAI_TCR3:
455 - case FSL_SAI_TCR4:
456 - case FSL_SAI_TCR5:
457 case FSL_SAI_TFR0:
458 case FSL_SAI_TFR1:
459 case FSL_SAI_TMR:
460 - case FSL_SAI_RCSR:
461 - case FSL_SAI_RCR1:
462 - case FSL_SAI_RCR2:
463 - case FSL_SAI_RCR3:
464 - case FSL_SAI_RCR4:
465 - case FSL_SAI_RCR5:
466 case FSL_SAI_RDR0:
467 case FSL_SAI_RDR1:
468 case FSL_SAI_RFR0:
469 @@ -815,9 +839,13 @@ static bool fsl_sai_readable_reg(struct
470
471 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
472 {
473 + struct fsl_sai *sai = dev_get_drvdata(dev);
474 + unsigned char offset = sai->soc->reg_offset;
475 +
476 + if (reg == FSL_SAI_TCSR(offset) || reg == FSL_SAI_RCSR(offset))
477 + return true;
478 +
479 switch (reg) {
480 - case FSL_SAI_TCSR:
481 - case FSL_SAI_RCSR:
482 case FSL_SAI_TFR0:
483 case FSL_SAI_TFR1:
484 case FSL_SAI_RFR0:
485 @@ -832,22 +860,19 @@ static bool fsl_sai_volatile_reg(struct
486
487 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
488 {
489 + struct fsl_sai *sai = dev_get_drvdata(dev);
490 + unsigned char offset = sai->soc->reg_offset;
491 +
492 + if (reg >= FSL_SAI_TCSR(offset) && reg <= FSL_SAI_TCR5(offset))
493 + return true;
494 +
495 + if (reg >= FSL_SAI_RCSR(offset) && reg <= FSL_SAI_RCR5(offset))
496 + return true;
497 +
498 switch (reg) {
499 - case FSL_SAI_TCSR:
500 - case FSL_SAI_TCR1:
501 - case FSL_SAI_TCR2:
502 - case FSL_SAI_TCR3:
503 - case FSL_SAI_TCR4:
504 - case FSL_SAI_TCR5:
505 case FSL_SAI_TDR0:
506 case FSL_SAI_TDR1:
507 case FSL_SAI_TMR:
508 - case FSL_SAI_RCSR:
509 - case FSL_SAI_RCR1:
510 - case FSL_SAI_RCR2:
511 - case FSL_SAI_RCR3:
512 - case FSL_SAI_RCR4:
513 - case FSL_SAI_RCR5:
514 case FSL_SAI_RMR:
515 return true;
516 default:
517 @@ -855,14 +880,28 @@ static bool fsl_sai_writeable_reg(struct
518 }
519 }
520
521 -static const struct regmap_config fsl_sai_regmap_config = {
522 +static const struct regmap_config fsl_sai_v2_regmap_config = {
523 .reg_bits = 32,
524 .reg_stride = 4,
525 .val_bits = 32,
526
527 .max_register = FSL_SAI_RMR,
528 - .reg_defaults = fsl_sai_reg_defaults,
529 - .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults),
530 + .reg_defaults = fsl_sai_v2_reg_defaults,
531 + .num_reg_defaults = ARRAY_SIZE(fsl_sai_v2_reg_defaults),
532 + .readable_reg = fsl_sai_readable_reg,
533 + .volatile_reg = fsl_sai_volatile_reg,
534 + .writeable_reg = fsl_sai_writeable_reg,
535 + .cache_type = REGCACHE_FLAT,
536 +};
537 +
538 +static const struct regmap_config fsl_sai_v3_regmap_config = {
539 + .reg_bits = 32,
540 + .reg_stride = 4,
541 + .val_bits = 32,
542 +
543 + .max_register = FSL_SAI_RMR,
544 + .reg_defaults = fsl_sai_v3_reg_defaults,
545 + .num_reg_defaults = ARRAY_SIZE(fsl_sai_v3_reg_defaults),
546 .readable_reg = fsl_sai_readable_reg,
547 .volatile_reg = fsl_sai_volatile_reg,
548 .writeable_reg = fsl_sai_writeable_reg,
549 @@ -874,6 +913,7 @@ static const struct of_device_id fsl_sai
550 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx },
551 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6ul },
552 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp },
553 + { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq },
554 { /* sentinel */ }
555 };
556 MODULE_DEVICE_TABLE(of, fsl_sai_ids);
557 @@ -889,7 +929,8 @@ static int fsl_sai_probe(struct platform
558 char tmp[8];
559 int irq, ret, i;
560 int index;
561 - unsigned long irqflag = 0;
562 + struct regmap_config fsl_sai_regmap_config = fsl_sai_v2_regmap_config;
563 + unsigned long irqflags = 0;
564
565 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
566 if (!sai)
567 @@ -909,6 +950,9 @@ static int fsl_sai_probe(struct platform
568 if (IS_ERR(base))
569 return PTR_ERR(base);
570
571 + if (sai->soc->reg_offset == 8)
572 + fsl_sai_regmap_config = fsl_sai_v3_regmap_config;
573 +
574 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
575 "bus", base, &fsl_sai_regmap_config);
576
577 @@ -963,11 +1007,11 @@ static int fsl_sai_probe(struct platform
578 }
579
580 /* SAI shared interrupt */
581 - if (of_property_read_bool(np, "shared-interrupt"))
582 - irqflag = IRQF_SHARED;
583 + if (of_property_read_bool(np, "fsl,shared-interrupt"))
584 + irqflags = IRQF_SHARED;
585
586 - ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, irqflag,
587 - np->name, sai);
588 + ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, irqflags, np->name,
589 + sai);
590 if (ret) {
591 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
592 return ret;
593 @@ -1091,6 +1135,7 @@ static int fsl_sai_runtime_suspend(struc
594 static int fsl_sai_runtime_resume(struct device *dev)
595 {
596 struct fsl_sai *sai = dev_get_drvdata(dev);
597 + unsigned char offset = sai->soc->reg_offset;
598 int ret;
599
600 ret = clk_prepare_enable(sai->bus_clk);
601 @@ -1116,11 +1161,11 @@ static int fsl_sai_runtime_resume(struct
602 PM_QOS_CPU_DMA_LATENCY, 0);
603
604 regcache_cache_only(sai->regmap, false);
605 - regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
606 - regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
607 + regmap_write(sai->regmap, FSL_SAI_TCSR(offset), FSL_SAI_CSR_SR);
608 + regmap_write(sai->regmap, FSL_SAI_RCSR(offset), FSL_SAI_CSR_SR);
609 usleep_range(1000, 2000);
610 - regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
611 - regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
612 + regmap_write(sai->regmap, FSL_SAI_TCSR(offset), 0);
613 + regmap_write(sai->regmap, FSL_SAI_RCSR(offset), 0);
614
615 ret = regcache_sync(sai->regmap);
616 if (ret)
617 --- a/sound/soc/fsl/fsl_sai.h
618 +++ b/sound/soc/fsl/fsl_sai.h
619 @@ -14,38 +14,36 @@
620 SNDRV_PCM_FMTBIT_S32_LE)
621
622 /* SAI Register Map Register */
623 -#define FSL_SAI_TCSR 0x00 /* SAI Transmit Control */
624 -#define FSL_SAI_TCR1 0x04 /* SAI Transmit Configuration 1 */
625 -#define FSL_SAI_TCR2 0x08 /* SAI Transmit Configuration 2 */
626 -#define FSL_SAI_TCR3 0x0c /* SAI Transmit Configuration 3 */
627 -#define FSL_SAI_TCR4 0x10 /* SAI Transmit Configuration 4 */
628 -#define FSL_SAI_TCR5 0x14 /* SAI Transmit Configuration 5 */
629 +#define FSL_SAI_TCSR(offset) (0x00 + offset) /* SAI Transmit Control */
630 +#define FSL_SAI_TCR1(offset) (0x04 + offset) /* SAI Transmit Configuration 1 */
631 +#define FSL_SAI_TCR2(offset) (0x08 + offset) /* SAI Transmit Configuration 2 */
632 +#define FSL_SAI_TCR3(offset) (0x0c + offset) /* SAI Transmit Configuration 3 */
633 +#define FSL_SAI_TCR4(offset) (0x10 + offset) /* SAI Transmit Configuration 4 */
634 +#define FSL_SAI_TCR5(offset) (0x14 + offset) /* SAI Transmit Configuration 5 */
635 #define FSL_SAI_TDR0 0x20 /* SAI Transmit Data */
636 #define FSL_SAI_TDR1 0x24 /* SAI Transmit Data */
637 #define FSL_SAI_TFR0 0x40 /* SAI Transmit FIFO */
638 #define FSL_SAI_TFR1 0x44 /* SAI Transmit FIFO */
639 #define FSL_SAI_TFR 0x40 /* SAI Transmit FIFO */
640 #define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */
641 -#define FSL_SAI_RCSR 0x80 /* SAI Receive Control */
642 -#define FSL_SAI_RCR1 0x84 /* SAI Receive Configuration 1 */
643 -#define FSL_SAI_RCR2 0x88 /* SAI Receive Configuration 2 */
644 -#define FSL_SAI_RCR3 0x8c /* SAI Receive Configuration 3 */
645 -#define FSL_SAI_RCR4 0x90 /* SAI Receive Configuration 4 */
646 -#define FSL_SAI_RCR5 0x94 /* SAI Receive Configuration 5 */
647 +#define FSL_SAI_RCSR(offset) (0x80 + offset) /* SAI Receive Control */
648 +#define FSL_SAI_RCR1(offset) (0x84 + offset) /* SAI Receive Configuration 1 */
649 +#define FSL_SAI_RCR2(offset) (0x88 + offset) /* SAI Receive Configuration 2 */
650 +#define FSL_SAI_RCR3(offset) (0x8c + offset) /* SAI Receive Configuration 3 */
651 +#define FSL_SAI_RCR4(offset) (0x90 + offset) /* SAI Receive Configuration 4 */
652 +#define FSL_SAI_RCR5(offset) (0x94 + offset) /* SAI Receive Configuration 5 */
653 #define FSL_SAI_RDR0 0xa0 /* SAI Receive Data */
654 #define FSL_SAI_RDR1 0xa4 /* SAI Receive Data */
655 #define FSL_SAI_RFR0 0xc0 /* SAI Receive FIFO */
656 #define FSL_SAI_RFR1 0xc4 /* SAI Receive FIFO */
657 #define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */
658
659 -#define FSL_SAI_xCSR(tx) (tx ? FSL_SAI_TCSR : FSL_SAI_RCSR)
660 -#define FSL_SAI_xCR1(tx) (tx ? FSL_SAI_TCR1 : FSL_SAI_RCR1)
661 -#define FSL_SAI_xCR2(tx) (tx ? FSL_SAI_TCR2 : FSL_SAI_RCR2)
662 -#define FSL_SAI_xCR3(tx) (tx ? FSL_SAI_TCR3 : FSL_SAI_RCR3)
663 -#define FSL_SAI_xCR4(tx) (tx ? FSL_SAI_TCR4 : FSL_SAI_RCR4)
664 -#define FSL_SAI_xCR5(tx) (tx ? FSL_SAI_TCR5 : FSL_SAI_RCR5)
665 -#define FSL_SAI_xDR(tx) (tx ? FSL_SAI_TDR : FSL_SAI_RDR)
666 -#define FSL_SAI_xFR(tx) (tx ? FSL_SAI_TFR : FSL_SAI_RFR)
667 +#define FSL_SAI_xCSR(tx, off) (tx ? FSL_SAI_TCSR(off) : FSL_SAI_RCSR(off))
668 +#define FSL_SAI_xCR1(tx, off) (tx ? FSL_SAI_TCR1(off) : FSL_SAI_RCR1(off))
669 +#define FSL_SAI_xCR2(tx, off) (tx ? FSL_SAI_TCR2(off) : FSL_SAI_RCR2(off))
670 +#define FSL_SAI_xCR3(tx, off) (tx ? FSL_SAI_TCR3(off) : FSL_SAI_RCR3(off))
671 +#define FSL_SAI_xCR4(tx, off) (tx ? FSL_SAI_TCR4(off) : FSL_SAI_RCR4(off))
672 +#define FSL_SAI_xCR5(tx, off) (tx ? FSL_SAI_TCR5(off) : FSL_SAI_RCR5(off))
673 #define FSL_SAI_xMR(tx) (tx ? FSL_SAI_TMR : FSL_SAI_RMR)
674
675 /* SAI Transmit/Receive Control Register */
676 @@ -87,8 +85,7 @@
677 #define FSL_SAI_CR2_DIV_MASK 0xff
678
679 /* SAI Transmit and Receive Configuration 3 Register */
680 -#define FSL_SAI_CR3_TRCE0 BIT(16)
681 -#define FSL_SAI_CR3_TRCE1 BIT(17)
682 +#define FSL_SAI_CR3_TRCE_MASK (0xff << 16)
683 #define FSL_SAI_CR3_TRCE(x) (x << 16)
684 #define FSL_SAI_CR3_WDFL(x) (x)
685 #define FSL_SAI_CR3_WDFL_MASK 0x1f
686 @@ -98,6 +95,7 @@
687 #define FSL_SAI_CR4_FCONT BIT(28)
688 #define FSL_SAI_CR4_FCOMB_SHIFT BIT(26)
689 #define FSL_SAI_CR4_FCOMB_SOFT BIT(27)
690 +#define FSL_SAI_CR4_FCOMB_MASK (0x3 << 26)
691 #define FSL_SAI_CR4_FPACK_8 (0x2 << 24)
692 #define FSL_SAI_CR4_FPACK_16 (0x3 << 24)
693 #define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16)
694 @@ -147,6 +145,7 @@ struct fsl_sai_soc_data {
695 unsigned int fifos;
696 unsigned int dataline;
697 unsigned int flags;
698 + unsigned char reg_offset;
699 bool imx;
700 };
701
Staging tree of Mathias Kresin