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layerscape: update kernel patches
[openwrt/staging/mkresin.git] / target / linux / layerscape / patches-4.9 / 401-mtd-spi-nor-support-layerscape.patch
1 From a3757157751a8a5302ee5e11faf828dc5db02018 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 10:53:50 +0800
4 Subject: [PATCH] mtd: spi-nor: support layerscape
5
6 This is a integrated patch for layerscape qspi support.
7
8 Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
9 Signed-off-by: Yunhui Cui <B56489@freescale.com>
10 Signed-off-by: mar.krzeminski <mar.krzeminski@gmail.com>
11 Signed-off-by: Alison Wang <b18965@freescale.com>
12 Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com>
13 Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
14 Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
15 Signed-off-by: Alexander Kurz <akurz@blala.de>
16 Signed-off-by: L. D. Pinney <ldpinney@gmail.com>
17 Signed-off-by: Ash Benz <ash.benz@bk.ru>
18 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
19 ---
20 drivers/mtd/mtdchar.c | 2 +-
21 drivers/mtd/spi-nor/fsl-quadspi.c | 327 +++++++++++++++++++++++++++++++-------
22 drivers/mtd/spi-nor/spi-nor.c | 136 ++++++++++++++--
23 include/linux/mtd/spi-nor.h | 14 +-
24 4 files changed, 409 insertions(+), 70 deletions(-)
25
26 diff --git a/drivers/mtd/mtdchar.c b/drivers/mtd/mtdchar.c
27 index 2a47a3f0..4f21401d 100644
28 --- a/drivers/mtd/mtdchar.c
29 +++ b/drivers/mtd/mtdchar.c
30 @@ -451,7 +451,7 @@ static int mtdchar_readoob(struct file *file, struct mtd_info *mtd,
31 * data. For our userspace tools it is important to dump areas
32 * with ECC errors!
33 * For kernel internal usage it also might return -EUCLEAN
34 - * to signal the caller that a bitflip has occured and has
35 + * to signal the caller that a bitflip has occurred and has
36 * been corrected by the ECC algorithm.
37 *
38 * Note: currently the standard NAND function, nand_read_oob_std,
39 diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
40 index 5c82e4ef..33ecc27a 100644
41 --- a/drivers/mtd/spi-nor/fsl-quadspi.c
42 +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
43 @@ -41,6 +41,8 @@
44 #define QUADSPI_QUIRK_TKT253890 (1 << 2)
45 /* Controller cannot wake up from wait mode, TKT245618 */
46 #define QUADSPI_QUIRK_TKT245618 (1 << 3)
47 +/* QSPI_AMBA_BASE is internally added by SOC design */
48 +#define QUADSPI_AMBA_BASE_INTERNAL (0x10000)
49
50 /* The registers */
51 #define QUADSPI_MCR 0x00
52 @@ -193,7 +195,7 @@
53 #define QUADSPI_LUT_NUM 64
54
55 /* SEQID -- we can have 16 seqids at most. */
56 -#define SEQID_QUAD_READ 0
57 +#define SEQID_READ 0
58 #define SEQID_WREN 1
59 #define SEQID_WRDI 2
60 #define SEQID_RDSR 3
61 @@ -205,15 +207,22 @@
62 #define SEQID_RDCR 9
63 #define SEQID_EN4B 10
64 #define SEQID_BRWR 11
65 +#define SEQID_RDAR_OR_RD_EVCR 12
66 +#define SEQID_WRAR 13
67 +#define SEQID_WD_EVCR 14
68
69 #define QUADSPI_MIN_IOMAP SZ_4M
70
71 +#define FLASH_VENDOR_SPANSION_FS "s25fs"
72 +#define SPANSION_S25FS_FAMILY (1 << 1)
73 +
74 enum fsl_qspi_devtype {
75 FSL_QUADSPI_VYBRID,
76 FSL_QUADSPI_IMX6SX,
77 FSL_QUADSPI_IMX7D,
78 FSL_QUADSPI_IMX6UL,
79 FSL_QUADSPI_LS1021A,
80 + FSL_QUADSPI_LS2080A,
81 };
82
83 struct fsl_qspi_devtype_data {
84 @@ -224,7 +233,7 @@ struct fsl_qspi_devtype_data {
85 int driver_data;
86 };
87
88 -static struct fsl_qspi_devtype_data vybrid_data = {
89 +static const struct fsl_qspi_devtype_data vybrid_data = {
90 .devtype = FSL_QUADSPI_VYBRID,
91 .rxfifo = 128,
92 .txfifo = 64,
93 @@ -232,7 +241,7 @@ static struct fsl_qspi_devtype_data vybrid_data = {
94 .driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
95 };
96
97 -static struct fsl_qspi_devtype_data imx6sx_data = {
98 +static const struct fsl_qspi_devtype_data imx6sx_data = {
99 .devtype = FSL_QUADSPI_IMX6SX,
100 .rxfifo = 128,
101 .txfifo = 512,
102 @@ -241,7 +250,7 @@ static struct fsl_qspi_devtype_data imx6sx_data = {
103 | QUADSPI_QUIRK_TKT245618,
104 };
105
106 -static struct fsl_qspi_devtype_data imx7d_data = {
107 +static const struct fsl_qspi_devtype_data imx7d_data = {
108 .devtype = FSL_QUADSPI_IMX7D,
109 .rxfifo = 512,
110 .txfifo = 512,
111 @@ -250,7 +259,7 @@ static struct fsl_qspi_devtype_data imx7d_data = {
112 | QUADSPI_QUIRK_4X_INT_CLK,
113 };
114
115 -static struct fsl_qspi_devtype_data imx6ul_data = {
116 +static const struct fsl_qspi_devtype_data imx6ul_data = {
117 .devtype = FSL_QUADSPI_IMX6UL,
118 .rxfifo = 128,
119 .txfifo = 512,
120 @@ -267,6 +276,14 @@ static struct fsl_qspi_devtype_data ls1021a_data = {
121 .driver_data = 0,
122 };
123
124 +static struct fsl_qspi_devtype_data ls2080a_data = {
125 + .devtype = FSL_QUADSPI_LS2080A,
126 + .rxfifo = 128,
127 + .txfifo = 64,
128 + .ahb_buf_size = 1024,
129 + .driver_data = QUADSPI_AMBA_BASE_INTERNAL | QUADSPI_QUIRK_TKT253890,
130 +};
131 +
132 #define FSL_QSPI_MAX_CHIP 4
133 struct fsl_qspi {
134 struct spi_nor nor[FSL_QSPI_MAX_CHIP];
135 @@ -282,6 +299,7 @@ struct fsl_qspi {
136 u32 nor_size;
137 u32 nor_num;
138 u32 clk_rate;
139 + u32 ddr_smp;
140 unsigned int chip_base_addr; /* We may support two chips. */
141 bool has_second_chip;
142 bool big_endian;
143 @@ -309,6 +327,23 @@ static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
144 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
145 }
146
147 +static inline int has_added_amba_base_internal(struct fsl_qspi *q)
148 +{
149 + return q->devtype_data->driver_data & QUADSPI_AMBA_BASE_INTERNAL;
150 +}
151 +
152 +static u32 fsl_get_nor_vendor(struct spi_nor *nor)
153 +{
154 + u32 vendor_id;
155 +
156 + if (nor->vendor) {
157 + if (memcmp(nor->vendor, FLASH_VENDOR_SPANSION_FS,
158 + sizeof(FLASH_VENDOR_SPANSION_FS) - 1))
159 + vendor_id = SPANSION_S25FS_FAMILY;
160 + }
161 + return vendor_id;
162 +}
163 +
164 /*
165 * R/W functions for big- or little-endian registers:
166 * The qSPI controller's endian is independent of the CPU core's endian.
167 @@ -331,6 +366,31 @@ static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
168 return ioread32(addr);
169 }
170
171 +static inline u32 *u8tou32(u32 *dest, const u8 *src, size_t n)
172 +{
173 + size_t i;
174 + *dest = 0;
175 +
176 + n = n > 4 ? 4 : n;
177 + for (i = 0; i < n; i++)
178 + *dest |= *src++ << i * 8;
179 +
180 + return dest;
181 +
182 +}
183 +
184 +static inline u8 *u32tou8(u8 *dest, const u32 *src, size_t n)
185 +{
186 + size_t i;
187 + u8 *xdest = dest;
188 +
189 + n = n > 4 ? 4 : n;
190 + for (i = 0; i < n; i++)
191 + *xdest++ = *src >> i * 8;
192 +
193 + return dest;
194 +}
195 +
196 /*
197 * An IC bug makes us to re-arrange the 32-bit data.
198 * The following chips, such as IMX6SLX, have fixed this bug.
199 @@ -373,8 +433,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
200 void __iomem *base = q->iobase;
201 int rxfifo = q->devtype_data->rxfifo;
202 u32 lut_base;
203 - u8 cmd, addrlen, dummy;
204 int i;
205 + u32 vendor;
206 +
207 + struct spi_nor *nor = &q->nor[0];
208 + u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
209 + u8 read_op = nor->read_opcode;
210 + u8 read_dm = nor->read_dummy;
211 +
212 + vendor = fsl_get_nor_vendor(nor);
213
214 fsl_qspi_unlock_lut(q);
215
216 @@ -382,25 +449,51 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
217 for (i = 0; i < QUADSPI_LUT_NUM; i++)
218 qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
219
220 - /* Quad Read */
221 - lut_base = SEQID_QUAD_READ * 4;
222 -
223 - if (q->nor_size <= SZ_16M) {
224 - cmd = SPINOR_OP_READ_1_1_4;
225 - addrlen = ADDR24BIT;
226 - dummy = 8;
227 - } else {
228 - /* use the 4-byte address */
229 - cmd = SPINOR_OP_READ_1_1_4;
230 - addrlen = ADDR32BIT;
231 - dummy = 8;
232 - }
233 -
234 - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
235 + /* Read */
236 + lut_base = SEQID_READ * 4;
237 +
238 + if (nor->flash_read == SPI_NOR_FAST) {
239 + qspi_writel(q, LUT0(CMD, PAD1, read_op) |
240 + LUT1(ADDR, PAD1, addrlen),
241 + base + QUADSPI_LUT(lut_base));
242 + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
243 + LUT1(FSL_READ, PAD1, rxfifo),
244 + base + QUADSPI_LUT(lut_base + 1));
245 + } else if (nor->flash_read == SPI_NOR_QUAD) {
246 + if (q->nor_size == 0x4000000) {
247 + read_op = 0xEC;
248 + qspi_writel(q,
249 + LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD4, addrlen),
250 + base + QUADSPI_LUT(lut_base));
251 + qspi_writel(q,
252 + LUT0(MODE, PAD4, 0xff) | LUT1(DUMMY, PAD4, read_dm),
253 + base + QUADSPI_LUT(lut_base + 1));
254 + qspi_writel(q,
255 + LUT0(FSL_READ, PAD4, rxfifo),
256 + base + QUADSPI_LUT(lut_base + 2));
257 + } else {
258 + qspi_writel(q, LUT0(CMD, PAD1, read_op) |
259 + LUT1(ADDR, PAD1, addrlen),
260 + base + QUADSPI_LUT(lut_base));
261 + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
262 + LUT1(FSL_READ, PAD4, rxfifo),
263 + base + QUADSPI_LUT(lut_base + 1));
264 + }
265 + } else if (nor->flash_read == SPI_NOR_DDR_QUAD) {
266 + /* read mode : 1-4-4, such as Spansion s25fl128s. */
267 + qspi_writel(q, LUT0(CMD, PAD1, read_op)
268 + | LUT1(ADDR_DDR, PAD4, addrlen),
269 base + QUADSPI_LUT(lut_base));
270 - qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
271 +
272 + qspi_writel(q, LUT0(MODE_DDR, PAD4, 0xff)
273 + | LUT1(DUMMY, PAD1, read_dm),
274 base + QUADSPI_LUT(lut_base + 1));
275
276 + qspi_writel(q, LUT0(FSL_READ_DDR, PAD4, rxfifo)
277 + | LUT1(JMP_ON_CS, PAD1, 0),
278 + base + QUADSPI_LUT(lut_base + 2));
279 + }
280 +
281 /* Write enable */
282 lut_base = SEQID_WREN * 4;
283 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
284 @@ -409,16 +502,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
285 /* Page Program */
286 lut_base = SEQID_PP * 4;
287
288 - if (q->nor_size <= SZ_16M) {
289 - cmd = SPINOR_OP_PP;
290 - addrlen = ADDR24BIT;
291 - } else {
292 - /* use the 4-byte address */
293 - cmd = SPINOR_OP_PP;
294 - addrlen = ADDR32BIT;
295 - }
296 -
297 - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
298 + qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
299 + LUT1(ADDR, PAD1, addrlen),
300 base + QUADSPI_LUT(lut_base));
301 qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
302 base + QUADSPI_LUT(lut_base + 1));
303 @@ -432,10 +517,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
304 /* Erase a sector */
305 lut_base = SEQID_SE * 4;
306
307 - cmd = q->nor[0].erase_opcode;
308 - addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;
309 -
310 - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
311 + qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
312 + LUT1(ADDR, PAD1, addrlen),
313 base + QUADSPI_LUT(lut_base));
314
315 /* Erase the whole chip */
316 @@ -476,6 +559,44 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
317 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
318 base + QUADSPI_LUT(lut_base));
319
320 +
321 + /*
322 + * Flash Micron and Spansion command confilict
323 + * use the same value 0x65. But it indicates different meaning.
324 + */
325 + lut_base = SEQID_RDAR_OR_RD_EVCR * 4;
326 +
327 + if (vendor == SPANSION_S25FS_FAMILY) {
328 + /*
329 + * Read any device register.
330 + * Used for Spansion S25FS-S family flash only.
331 + */
332 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
333 + LUT1(ADDR, PAD1, ADDR24BIT),
334 + base + QUADSPI_LUT(lut_base));
335 + qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
336 + base + QUADSPI_LUT(lut_base + 1));
337 + } else {
338 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RD_EVCR),
339 + base + QUADSPI_LUT(lut_base));
340 + }
341 +
342 + /*
343 + * Write any device register.
344 + * Used for Spansion S25FS-S family flash only.
345 + */
346 + lut_base = SEQID_WRAR * 4;
347 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_WRAR) |
348 + LUT1(ADDR, PAD1, ADDR24BIT),
349 + base + QUADSPI_LUT(lut_base));
350 + qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1),
351 + base + QUADSPI_LUT(lut_base + 1));
352 +
353 + /* Write EVCR register */
354 + lut_base = SEQID_WD_EVCR * 4;
355 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WD_EVCR),
356 + base + QUADSPI_LUT(lut_base));
357 +
358 fsl_qspi_lock_lut(q);
359 }
360
361 @@ -483,8 +604,24 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
362 static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
363 {
364 switch (cmd) {
365 + case SPINOR_OP_READ_1_4_4_D:
366 + case SPINOR_OP_READ4_1_4_4_D:
367 + case SPINOR_OP_READ4_1_1_4:
368 case SPINOR_OP_READ_1_1_4:
369 - return SEQID_QUAD_READ;
370 + case SPINOR_OP_READ_FAST:
371 + case SPINOR_OP_READ4_FAST:
372 + return SEQID_READ;
373 + /*
374 + * Spansion & Micron use the same command value 0x65
375 + * Spansion: SPINOR_OP_SPANSION_RDAR, read any register.
376 + * Micron: SPINOR_OP_RD_EVCR,
377 + * read enhanced volatile configuration register.
378 + * case SPINOR_OP_RD_EVCR:
379 + */
380 + case SPINOR_OP_SPANSION_RDAR:
381 + return SEQID_RDAR_OR_RD_EVCR;
382 + case SPINOR_OP_SPANSION_WRAR:
383 + return SEQID_WRAR;
384 case SPINOR_OP_WREN:
385 return SEQID_WREN;
386 case SPINOR_OP_WRDI:
387 @@ -496,6 +633,7 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
388 case SPINOR_OP_CHIP_ERASE:
389 return SEQID_CHIP_ERASE;
390 case SPINOR_OP_PP:
391 + case SPINOR_OP_PP_4B:
392 return SEQID_PP;
393 case SPINOR_OP_RDID:
394 return SEQID_RDID;
395 @@ -507,6 +645,8 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
396 return SEQID_EN4B;
397 case SPINOR_OP_BRWR:
398 return SEQID_BRWR;
399 + case SPINOR_OP_WD_EVCR:
400 + return SEQID_WD_EVCR;
401 default:
402 if (cmd == q->nor[0].erase_opcode)
403 return SEQID_SE;
404 @@ -531,8 +671,11 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
405 /* save the reg */
406 reg = qspi_readl(q, base + QUADSPI_MCR);
407
408 - qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
409 - base + QUADSPI_SFAR);
410 + if (has_added_amba_base_internal(q))
411 + qspi_writel(q, q->chip_base_addr + addr, base + QUADSPI_SFAR);
412 + else
413 + qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
414 + base + QUADSPI_SFAR);
415 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
416 base + QUADSPI_RBCT);
417 qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
418 @@ -582,10 +725,10 @@ static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
419 q->chip_base_addr, tmp);
420
421 if (len >= 4) {
422 - *((u32 *)rxbuf) = tmp;
423 + u32tou8(rxbuf, &tmp, 4);
424 rxbuf += 4;
425 } else {
426 - memcpy(rxbuf, &tmp, len);
427 + u32tou8(rxbuf, &tmp, len);
428 break;
429 }
430
431 @@ -619,11 +762,12 @@ static inline void fsl_qspi_invalid(struct fsl_qspi *q)
432 }
433
434 static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
435 - u8 opcode, unsigned int to, u32 *txbuf,
436 + u8 opcode, unsigned int to, u8 *txbuf,
437 unsigned count)
438 {
439 int ret, i, j;
440 u32 tmp;
441 + u8 byts;
442
443 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
444 q->chip_base_addr, to, count);
445 @@ -633,10 +777,13 @@ static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
446 qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
447
448 /* fill the TX data to the FIFO */
449 + byts = count;
450 for (j = 0, i = ((count + 3) / 4); j < i; j++) {
451 - tmp = fsl_qspi_endian_xchg(q, *txbuf);
452 + u8tou32(&tmp, txbuf, byts);
453 + tmp = fsl_qspi_endian_xchg(q, tmp);
454 qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
455 - txbuf++;
456 + txbuf += 4;
457 + byts -= 4;
458 }
459
460 /* fill the TXFIFO upto 16 bytes for i.MX7d */
461 @@ -657,11 +804,43 @@ static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
462 {
463 int nor_size = q->nor_size;
464 void __iomem *base = q->iobase;
465 + u32 mem_base;
466 +
467 + if (has_added_amba_base_internal(q))
468 + mem_base = 0x0;
469 + else
470 + mem_base = q->memmap_phy;
471 +
472 + qspi_writel(q, nor_size + mem_base, base + QUADSPI_SFA1AD);
473 + qspi_writel(q, nor_size * 2 + mem_base, base + QUADSPI_SFA2AD);
474 + qspi_writel(q, nor_size * 3 + mem_base, base + QUADSPI_SFB1AD);
475 + qspi_writel(q, nor_size * 4 + mem_base, base + QUADSPI_SFB2AD);
476 +}
477 +
478 +/*
479 + * enable controller ddr quad mode to support different
480 + * vender flashes ddr quad mode.
481 + */
482 +static void set_ddr_quad_mode(struct fsl_qspi *q)
483 +{
484 + u32 reg, reg2;
485 +
486 + reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
487 +
488 + /* Firstly, disable the module */
489 + qspi_writel(q, reg | QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
490 +
491 + /* Set the Sampling Register for DDR */
492 + reg2 = qspi_readl(q, q->iobase + QUADSPI_SMPR);
493 + reg2 &= ~QUADSPI_SMPR_DDRSMP_MASK;
494 + reg2 |= (((q->ddr_smp) << QUADSPI_SMPR_DDRSMP_SHIFT) &
495 + QUADSPI_SMPR_DDRSMP_MASK);
496 + qspi_writel(q, reg2, q->iobase + QUADSPI_SMPR);
497 +
498 + /* Enable the module again (enable the DDR too) */
499 + reg |= QUADSPI_MCR_DDR_EN_MASK;
500 + qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
501
502 - qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
503 - qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
504 - qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
505 - qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
506 }
507
508 /*
509 @@ -704,6 +883,11 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
510 seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
511 qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
512 q->iobase + QUADSPI_BFGENCR);
513 +
514 + /* enable the DDR quad read */
515 + if (q->nor->flash_read == SPI_NOR_DDR_QUAD)
516 + set_ddr_quad_mode(q);
517 +
518 }
519
520 /* This function was used to prepare and enable QSPI clock */
521 @@ -822,6 +1006,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = {
522 { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
523 { .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
524 { .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
525 + { .compatible = "fsl,ls2080a-qspi", .data = (void *)&ls2080a_data, },
526 { /* sentinel */ }
527 };
528 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
529 @@ -835,8 +1020,12 @@ static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
530 {
531 int ret;
532 struct fsl_qspi *q = nor->priv;
533 + u32 to = 0;
534
535 - ret = fsl_qspi_runcmd(q, opcode, 0, len);
536 + if (opcode == SPINOR_OP_SPANSION_RDAR)
537 + u8tou32(&to, nor->cmd_buf, 4);
538 +
539 + ret = fsl_qspi_runcmd(q, opcode, to, len);
540 if (ret)
541 return ret;
542
543 @@ -848,9 +1037,13 @@ static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
544 {
545 struct fsl_qspi *q = nor->priv;
546 int ret;
547 + u32 to = 0;
548 +
549 + if (opcode == SPINOR_OP_SPANSION_WRAR)
550 + u8tou32(&to, nor->cmd_buf, 4);
551
552 if (!buf) {
553 - ret = fsl_qspi_runcmd(q, opcode, 0, 1);
554 + ret = fsl_qspi_runcmd(q, opcode, to, 1);
555 if (ret)
556 return ret;
557
558 @@ -859,7 +1052,7 @@ static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
559
560 } else if (len > 0) {
561 ret = fsl_qspi_nor_write(q, nor, opcode, 0,
562 - (u32 *)buf, len);
563 + buf, len);
564 if (ret > 0)
565 return 0;
566 } else {
567 @@ -875,7 +1068,7 @@ static ssize_t fsl_qspi_write(struct spi_nor *nor, loff_t to,
568 {
569 struct fsl_qspi *q = nor->priv;
570 ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
571 - (u32 *)buf, len);
572 + (u8 *)buf, len);
573
574 /* invalid the data in the AHB buffer. */
575 fsl_qspi_invalid(q);
576 @@ -922,7 +1115,7 @@ static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from,
577 len);
578
579 /* Read out the data directly from the AHB buffer.*/
580 - memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
581 + memcpy_toio(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
582 len);
583
584 return len;
585 @@ -980,6 +1173,8 @@ static int fsl_qspi_probe(struct platform_device *pdev)
586 struct spi_nor *nor;
587 struct mtd_info *mtd;
588 int ret, i = 0;
589 + int find_node;
590 + enum read_mode mode = SPI_NOR_QUAD;
591
592 q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
593 if (!q)
594 @@ -1027,6 +1222,12 @@ static int fsl_qspi_probe(struct platform_device *pdev)
595 goto clk_failed;
596 }
597
598 + /* find ddrsmp value */
599 + ret = of_property_read_u32(dev->of_node, "fsl,ddr-sampling-point",
600 + &q->ddr_smp);
601 + if (ret)
602 + q->ddr_smp = 0;
603 +
604 /* find the irq */
605 ret = platform_get_irq(pdev, 0);
606 if (ret < 0) {
607 @@ -1050,6 +1251,7 @@ static int fsl_qspi_probe(struct platform_device *pdev)
608
609 mutex_init(&q->lock);
610
611 + find_node = 0;
612 /* iterate the subnodes. */
613 for_each_available_child_of_node(dev->of_node, np) {
614 /* skip the holes */
615 @@ -1076,18 +1278,25 @@ static int fsl_qspi_probe(struct platform_device *pdev)
616 ret = of_property_read_u32(np, "spi-max-frequency",
617 &q->clk_rate);
618 if (ret < 0)
619 - goto mutex_failed;
620 + continue;
621
622 /* set the chip address for READID */
623 fsl_qspi_set_base_addr(q, nor);
624
625 - ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD);
626 + ret = of_property_read_bool(np, "m25p,fast-read");
627 + mode = (ret) ? SPI_NOR_FAST : SPI_NOR_QUAD;
628 + /* Can we enable the DDR Quad Read? */
629 + ret = of_property_read_bool(np, "ddr-quad-read");
630 if (ret)
631 - goto mutex_failed;
632 + mode = SPI_NOR_DDR_QUAD;
633 +
634 + ret = spi_nor_scan(nor, NULL, mode);
635 + if (ret)
636 + continue;
637
638 ret = mtd_device_register(mtd, NULL, 0);
639 if (ret)
640 - goto mutex_failed;
641 + continue;
642
643 /* Set the correct NOR size now. */
644 if (q->nor_size == 0) {
645 @@ -1110,8 +1319,12 @@ static int fsl_qspi_probe(struct platform_device *pdev)
646 nor->page_size = q->devtype_data->txfifo;
647
648 i++;
649 + find_node++;
650 }
651
652 + if (find_node == 0)
653 + goto mutex_failed;
654 +
655 /* finish the rest init. */
656 ret = fsl_qspi_nor_setup_last(q);
657 if (ret)
658 diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
659 index 793d321d..190e0e45 100644
660 --- a/drivers/mtd/spi-nor/spi-nor.c
661 +++ b/drivers/mtd/spi-nor/spi-nor.c
662 @@ -40,6 +40,13 @@
663 #define SPI_NOR_MAX_ID_LEN 6
664 #define SPI_NOR_MAX_ADDR_WIDTH 4
665
666 +#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f
667 +/* Added for S25FS-S family flash */
668 +#define SPINOR_CONFIG_REG3_OFFSET 0x800004
669 +#define CR3V_4KB_ERASE_UNABLE 0x8
670 +#define SPINOR_S25FS_FAMILY_ID 0x81
671 +
672 +
673 struct flash_info {
674 char *name;
675
676 @@ -68,7 +75,8 @@ struct flash_info {
677 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
678 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
679 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
680 -#define USE_FSR BIT(7) /* use flag status register */
681 +#define USE_FSR BIT(13) /* use flag status register */
682 +#define SPI_NOR_DDR_QUAD_READ BIT(7) /* Flash supports DDR Quad Read */
683 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
684 #define SPI_NOR_HAS_TB BIT(9) /*
685 * Flash SR has Top/Bottom (TB) protect
686 @@ -85,9 +93,11 @@ struct flash_info {
687 * Use dedicated 4byte address op codes
688 * to support memory size above 128Mib.
689 */
690 +#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
691 };
692
693 #define JEDEC_MFR(info) ((info)->id[0])
694 +#define EXT_ID(info) ((info)->id[5])
695
696 static const struct flash_info *spi_nor_match_id(const char *name);
697
698 @@ -132,7 +142,7 @@ static int read_fsr(struct spi_nor *nor)
699 /*
700 * Read configuration register, returning its value in the
701 * location. Return the configuration register value.
702 - * Returns negative if error occured.
703 + * Returns negative if error occurred.
704 */
705 static int read_cr(struct spi_nor *nor)
706 {
707 @@ -160,6 +170,8 @@ static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
708 case SPI_NOR_DUAL:
709 case SPI_NOR_QUAD:
710 return 8;
711 + case SPI_NOR_DDR_QUAD:
712 + return 6;
713 case SPI_NOR_NORMAL:
714 return 0;
715 }
716 @@ -961,6 +973,8 @@ static const struct flash_info spi_nor_ids[] = {
717
718 /* ESMT */
719 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
720 + { "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
721 + { "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) },
722
723 /* Everspin */
724 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
725 @@ -1014,12 +1028,15 @@ static const struct flash_info spi_nor_ids[] = {
726 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
727 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
728 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
729 + { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
730 + { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
731 + { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
732 { "mx25u3235f", INFO(0xc22536, 0, 64 * 1024, 64, 0) },
733 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
734 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
735 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
736 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
737 - { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
738 + { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K) },
739 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
740 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
741 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
742 @@ -1033,10 +1050,11 @@ static const struct flash_info spi_nor_ids[] = {
743 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
744 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
745 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
746 + { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
747 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
748 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
749 - { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
750 - { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
751 + { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
752 + { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
753
754 /* PMC */
755 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
756 @@ -1054,8 +1072,11 @@ static const struct flash_info spi_nor_ids[] = {
757 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
758 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
759 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
760 - { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
761 + { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, 0)},
762 + { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ
763 + | SPI_NOR_DDR_QUAD_READ) },
764 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
765 + { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)},
766 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
767 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
768 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
769 @@ -1130,6 +1151,9 @@ static const struct flash_info spi_nor_ids[] = {
770 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
771 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
772 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
773 + { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
774 + { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
775 + { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
776 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
777 {
778 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
779 @@ -1192,6 +1216,53 @@ static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
780 id[0], id[1], id[2]);
781 return ERR_PTR(-ENODEV);
782 }
783 +/*
784 + * The S25FS-S family physical sectors may be configured as a
785 + * hybrid combination of eight 4-kB parameter sectors
786 + * at the top or bottom of the address space with all
787 + * but one of the remaining sectors being uniform size.
788 + * The Parameter Sector Erase commands (20h or 21h) must
789 + * be used to erase the 4-kB parameter sectors individually.
790 + * The Sector (uniform sector) Erase commands (D8h or DCh)
791 + * must be used to erase any of the remaining
792 + * sectors, including the portion of highest or lowest address
793 + * sector that is not overlaid by the parameter sectors.
794 + * The uniform sector erase command has no effect on parameter sectors.
795 + */
796 +static int spansion_s25fs_disable_4kb_erase(struct spi_nor *nor)
797 +{
798 + struct fsl_qspi *q;
799 + u32 cr3v_addr = SPINOR_CONFIG_REG3_OFFSET;
800 + u8 cr3v = 0x0;
801 + int ret = 0x0;
802 +
803 + q = nor->priv;
804 +
805 + nor->cmd_buf[2] = cr3v_addr >> 16;
806 + nor->cmd_buf[1] = cr3v_addr >> 8;
807 + nor->cmd_buf[0] = cr3v_addr >> 0;
808 +
809 + ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
810 + if (ret)
811 + return ret;
812 + if (cr3v & CR3V_4KB_ERASE_UNABLE)
813 + return 0;
814 + ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
815 + if (ret)
816 + return ret;
817 + cr3v = CR3V_4KB_ERASE_UNABLE;
818 + nor->program_opcode = SPINOR_OP_SPANSION_WRAR;
819 + nor->write(nor, cr3v_addr, 1, &cr3v);
820 +
821 + ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
822 + if (ret)
823 + return ret;
824 + if (!(cr3v & CR3V_4KB_ERASE_UNABLE))
825 + return -EPERM;
826 +
827 + return 0;
828 +}
829 +
830
831 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
832 size_t *retlen, u_char *buf)
833 @@ -1411,7 +1482,7 @@ static int macronix_quad_enable(struct spi_nor *nor)
834 * Write status Register and configuration register with 2 bytes
835 * The first byte will be written to the status register, while the
836 * second byte will be written to the configuration register.
837 - * Return negative if error occured.
838 + * Return negative if error occurred.
839 */
840 static int write_sr_cr(struct spi_nor *nor, u16 val)
841 {
842 @@ -1459,6 +1530,24 @@ static int spansion_quad_enable(struct spi_nor *nor)
843 return 0;
844 }
845
846 +static int set_ddr_quad_mode(struct spi_nor *nor, const struct flash_info *info)
847 +{
848 + int status;
849 +
850 + switch (JEDEC_MFR(info)) {
851 + case SNOR_MFR_SPANSION:
852 + status = spansion_quad_enable(nor);
853 + if (status) {
854 + dev_err(nor->dev, "Spansion DDR quad-read not enabled\n");
855 + return status;
856 + }
857 + return status;
858 + default:
859 + return -EINVAL;
860 + }
861 +}
862 +
863 +
864 static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
865 {
866 int status;
867 @@ -1604,9 +1693,25 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
868 write_sr(nor, 0);
869 spi_nor_wait_till_ready(nor);
870 }
871 + if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
872 + ret = read_sr(nor);
873 + ret &= SPI_NOR_MICRON_WRITE_ENABLE;
874 +
875 + write_enable(nor);
876 + write_sr(nor, ret);
877 + }
878 +
879 + if (EXT_ID(info) == SPINOR_S25FS_FAMILY_ID) {
880 + ret = spansion_s25fs_disable_4kb_erase(nor);
881 + if (ret)
882 + return ret;
883 + }
884 +
885
886 if (!mtd->name)
887 mtd->name = dev_name(dev);
888 + if (info->name)
889 + nor->vendor = info->name;
890 mtd->priv = nor;
891 mtd->type = MTD_NORFLASH;
892 mtd->writesize = 1;
893 @@ -1639,6 +1744,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
894 nor->flags |= SNOR_F_USE_FSR;
895 if (info->flags & SPI_NOR_HAS_TB)
896 nor->flags |= SNOR_F_HAS_SR_TB;
897 + if (info->flags & NO_CHIP_ERASE)
898 + nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
899
900 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
901 /* prefer "small sector" erase if possible */
902 @@ -1676,9 +1783,15 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
903 /* Some devices cannot do fast-read, no matter what DT tells us */
904 if (info->flags & SPI_NOR_NO_FR)
905 nor->flash_read = SPI_NOR_NORMAL;
906 -
907 - /* Quad/Dual-read mode takes precedence over fast/normal */
908 - if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
909 + /* DDR Quad/Quad/Dual-read mode takes precedence over fast/normal */
910 + if (mode == SPI_NOR_DDR_QUAD && info->flags & SPI_NOR_DDR_QUAD_READ) {
911 + ret = set_ddr_quad_mode(nor, info);
912 + if (ret) {
913 + dev_err(dev, "DDR quad mode not supported\n");
914 + return ret;
915 + }
916 + nor->flash_read = SPI_NOR_DDR_QUAD;
917 + } else if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
918 ret = set_quad_mode(nor, info);
919 if (ret) {
920 dev_err(dev, "quad mode not supported\n");
921 @@ -1691,6 +1804,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
922
923 /* Default commands */
924 switch (nor->flash_read) {
925 + case SPI_NOR_DDR_QUAD:
926 + nor->read_opcode = SPINOR_OP_READ4_1_4_4_D;
927 + break;
928 case SPI_NOR_QUAD:
929 nor->read_opcode = SPINOR_OP_READ_1_1_4;
930 break;
931 diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
932 index f2a71803..5003ff64 100644
933 --- a/include/linux/mtd/spi-nor.h
934 +++ b/include/linux/mtd/spi-nor.h
935 @@ -31,10 +31,10 @@
936
937 /*
938 * Note on opcode nomenclature: some opcodes have a format like
939 - * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
940 + * SPINOR_OP_FUNCTION{4,}_x_y_z{_D}. The numbers x, y,and z stand for the number
941 * of I/O lines used for the opcode, address, and data (respectively). The
942 * FUNCTION has an optional suffix of '4', to represent an opcode which
943 - * requires a 4-byte (32-bit) address.
944 + * requires a 4-byte (32-bit) address. The suffix of 'D' stands for the
945 */
946
947 /* Flash opcodes. */
948 @@ -46,7 +46,9 @@
949 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
950 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
951 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
952 +#define SPINOR_OP_READ_1_4_4_D 0xed /* Read data bytes (DDR Quad SPI) */
953 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
954 +#define SPINOR_OP_READ4_1_4_4_D 0xee /* Read data bytes (DDR Quad SPI) */
955 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
956 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
957 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
958 @@ -62,9 +64,11 @@
959 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
960 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
961 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
962 +#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
963 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
964 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
965 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
966 +#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
967 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
968 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
969 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
970 @@ -94,6 +98,10 @@
971 /* Used for Spansion flashes only. */
972 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
973
974 +/* Used for Spansion S25FS-S family flash only. */
975 +#define SPINOR_OP_SPANSION_RDAR 0x65 /* Read any device register */
976 +#define SPINOR_OP_SPANSION_WRAR 0x71 /* Write any device register */
977 +
978 /* Used for Micron flashes only. */
979 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
980 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
981 @@ -124,6 +132,7 @@ enum read_mode {
982 SPI_NOR_FAST,
983 SPI_NOR_DUAL,
984 SPI_NOR_QUAD,
985 + SPI_NOR_DDR_QUAD,
986 };
987
988 #define SPI_NOR_MAX_CMD_SIZE 8
989 @@ -189,6 +198,7 @@ struct spi_nor {
990 bool sst_write_second;
991 u32 flags;
992 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
993 + char *vendor;
994
995 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
996 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
997 --
998 2.14.1
999
Staging tree of Mathias Kresin