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ar71xx: ar934x_nfc: increase DMA retry count
[openwrt/staging/mkresin.git] / target / linux / ar71xx / files / drivers / mtd / nand / ar934x_nfc.c
1 /*
2 * Driver for the built-in NAND controller of the Atheros AR934x SoCs
3 *
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/nand.h>
17 #include <linux/mtd/partitions.h>
18 #include <linux/platform_device.h>
19 #include <linux/delay.h>
20 #include <linux/slab.h>
21
22 #include <linux/platform/ar934x_nfc.h>
23
24 #define AR934X_NFC_REG_CMD 0x00
25 #define AR934X_NFC_REG_CTRL 0x04
26 #define AR934X_NFC_REG_STATUS 0x08
27 #define AR934X_NFC_REG_INT_MASK 0x0c
28 #define AR934X_NFC_REG_INT_STATUS 0x10
29 #define AR934X_NFC_REG_ECC_CTRL 0x14
30 #define AR934X_NFC_REG_ECC_OFFSET 0x18
31 #define AR934X_NFC_REG_ADDR0_0 0x1c
32 #define AR934X_NFC_REG_ADDR0_1 0x24
33 #define AR934X_NFC_REG_ADDR1_0 0x20
34 #define AR934X_NFC_REG_ADDR1_1 0x28
35 #define AR934X_NFC_REG_SPARE_SIZE 0x30
36 #define AR934X_NFC_REG_PROTECT 0x38
37 #define AR934X_NFC_REG_LOOKUP_EN 0x40
38 #define AR934X_NFC_REG_LOOKUP(_x) (0x44 + (_i) * 4)
39 #define AR934X_NFC_REG_DMA_ADDR 0x64
40 #define AR934X_NFC_REG_DMA_COUNT 0x68
41 #define AR934X_NFC_REG_DMA_CTRL 0x6c
42 #define AR934X_NFC_REG_MEM_CTRL 0x80
43 #define AR934X_NFC_REG_DATA_SIZE 0x84
44 #define AR934X_NFC_REG_READ_STATUS 0x88
45 #define AR934X_NFC_REG_TIME_SEQ 0x8c
46 #define AR934X_NFC_REG_TIMINGS_ASYN 0x90
47 #define AR934X_NFC_REG_TIMINGS_SYN 0x94
48 #define AR934X_NFC_REG_FIFO_DATA 0x98
49 #define AR934X_NFC_REG_TIME_MODE 0x9c
50 #define AR934X_NFC_REG_DMA_ADDR_OFFS 0xa0
51 #define AR934X_NFC_REG_FIFO_INIT 0xb0
52 #define AR934X_NFC_REG_GEN_SEQ_CTRL 0xb4
53
54 #define AR934X_NFC_CMD_CMD_SEQ_S 0
55 #define AR934X_NFC_CMD_CMD_SEQ_M 0x3f
56 #define AR934X_NFC_CMD_SEQ_1C 0x00
57 #define AR934X_NFC_CMD_SEQ_ERASE 0x0e
58 #define AR934X_NFC_CMD_SEQ_12 0x0c
59 #define AR934X_NFC_CMD_SEQ_1C1AXR 0x21
60 #define AR934X_NFC_CMD_SEQ_S 0x24
61 #define AR934X_NFC_CMD_SEQ_1C3AXR 0x27
62 #define AR934X_NFC_CMD_SEQ_1C5A1CXR 0x2a
63 #define AR934X_NFC_CMD_SEQ_18 0x32
64 #define AR934X_NFC_CMD_INPUT_SEL_SIU 0
65 #define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6)
66 #define AR934X_NFC_CMD_ADDR_SEL_0 0
67 #define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7)
68 #define AR934X_NFC_CMD_CMD0_S 8
69 #define AR934X_NFC_CMD_CMD0_M 0xff
70 #define AR934X_NFC_CMD_CMD1_S 16
71 #define AR934X_NFC_CMD_CMD1_M 0xff
72 #define AR934X_NFC_CMD_CMD2_S 24
73 #define AR934X_NFC_CMD_CMD2_M 0xff
74
75 #define AR934X_NFC_CTRL_ADDR_CYCLE0_M 0x7
76 #define AR934X_NFC_CTRL_ADDR_CYCLE0_S 0
77 #define AR934X_NFC_CTRL_SPARE_EN BIT(3)
78 #define AR934X_NFC_CTRL_INT_EN BIT(4)
79 #define AR934X_NFC_CTRL_ECC_EN BIT(5)
80 #define AR934X_NFC_CTRL_BLOCK_SIZE_S 6
81 #define AR934X_NFC_CTRL_BLOCK_SIZE_M 0x3
82 #define AR934X_NFC_CTRL_BLOCK_SIZE_32 0
83 #define AR934X_NFC_CTRL_BLOCK_SIZE_64 1
84 #define AR934X_NFC_CTRL_BLOCK_SIZE_128 2
85 #define AR934X_NFC_CTRL_BLOCK_SIZE_256 3
86 #define AR934X_NFC_CTRL_PAGE_SIZE_S 8
87 #define AR934X_NFC_CTRL_PAGE_SIZE_M 0x7
88 #define AR934X_NFC_CTRL_PAGE_SIZE_256 0
89 #define AR934X_NFC_CTRL_PAGE_SIZE_512 1
90 #define AR934X_NFC_CTRL_PAGE_SIZE_1024 2
91 #define AR934X_NFC_CTRL_PAGE_SIZE_2048 3
92 #define AR934X_NFC_CTRL_PAGE_SIZE_4096 4
93 #define AR934X_NFC_CTRL_PAGE_SIZE_8192 5
94 #define AR934X_NFC_CTRL_PAGE_SIZE_16384 6
95 #define AR934X_NFC_CTRL_CUSTOM_SIZE_EN BIT(11)
96 #define AR934X_NFC_CTRL_IO_WIDTH_8BITS 0
97 #define AR934X_NFC_CTRL_IO_WIDTH_16BITS BIT(12)
98 #define AR934X_NFC_CTRL_LOOKUP_EN BIT(13)
99 #define AR934X_NFC_CTRL_PROT_EN BIT(14)
100 #define AR934X_NFC_CTRL_WORK_MODE_ASYNC 0
101 #define AR934X_NFC_CTRL_WORK_MODE_SYNC BIT(15)
102 #define AR934X_NFC_CTRL_ADDR0_AUTO_INC BIT(16)
103 #define AR934X_NFC_CTRL_ADDR1_AUTO_INC BIT(17)
104 #define AR934X_NFC_CTRL_ADDR_CYCLE1_M 0x7
105 #define AR934X_NFC_CTRL_ADDR_CYCLE1_S 18
106 #define AR934X_NFC_CTRL_SMALL_PAGE BIT(21)
107
108 #define AR934X_NFC_DMA_CTRL_DMA_START BIT(7)
109 #define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE 0
110 #define AR934X_NFC_DMA_CTRL_DMA_DIR_READ BIT(6)
111 #define AR934X_NFC_DMA_CTRL_DMA_MODE_SG BIT(5)
112 #define AR934X_NFC_DMA_CTRL_DMA_BURST_S 2
113 #define AR934X_NFC_DMA_CTRL_DMA_BURST_0 0
114 #define AR934X_NFC_DMA_CTRL_DMA_BURST_1 1
115 #define AR934X_NFC_DMA_CTRL_DMA_BURST_2 2
116 #define AR934X_NFC_DMA_CTRL_DMA_BURST_3 3
117 #define AR934X_NFC_DMA_CTRL_DMA_BURST_4 4
118 #define AR934X_NFC_DMA_CTRL_DMA_BURST_5 5
119 #define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1)
120 #define AR934X_NFC_DMA_CTRL_DMA_READY BIT(0)
121
122 #define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x))
123 #define AR934X_NFC_INT_CMD_END BIT(1)
124
125 /* default timing values */
126 #define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff
127 #define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22
128 #define AR934X_NFC_TIMINGS_SYN_DEFAULT 0xf
129
130 #define AR934X_NFC_ID_BUF_SIZE 8
131 #define AR934X_NFC_DEV_READY_TIMEOUT 25 /* msecs */
132 #define AR934X_NFC_DMA_READY_TIMEOUT 25 /* msecs */
133 #define AR934X_NFC_DONE_TIMEOUT 1000
134 #define AR934X_NFC_DMA_RETRIES 20
135
136 #define AR934X_NFC_USE_IRQ true
137 #define AR934X_NFC_IRQ_MASK AR934X_NFC_INT_DEV_RDY(0)
138
139 #define AR934X_NFC_GENSEQ_SMALL_PAGE_READ 0x30043
140
141 #undef AR934X_NFC_DEBUG_DATA
142 #undef AR934X_NFC_DEBUG
143
144 struct ar934x_nfc;
145
146 static inline __attribute__ ((format (printf, 2, 3)))
147 void _nfc_dbg(struct ar934x_nfc *nfc, const char *fmt, ...)
148 {
149 }
150
151 #ifdef AR934X_NFC_DEBUG
152 #define nfc_dbg(_nfc, fmt, ...) \
153 dev_info((_nfc)->parent, fmt, ##__VA_ARGS__)
154 #else
155 #define nfc_dbg(_nfc, fmt, ...) \
156 _nfc_dbg((_nfc), fmt, ##__VA_ARGS__)
157 #endif /* AR934X_NFC_DEBUG */
158
159 #ifdef AR934X_NFC_DEBUG_DATA
160 static void
161 nfc_debug_data(const char *label, void *data, int len)
162 {
163 print_hex_dump(KERN_WARNING, label, DUMP_PREFIX_OFFSET, 16, 1,
164 data, len, 0);
165 }
166 #else
167 static inline void
168 nfc_debug_data(const char *label, void *data, int len) {}
169 #endif /* AR934X_NFC_DEBUG_DATA */
170
171 struct ar934x_nfc {
172 struct mtd_info mtd;
173 struct nand_chip nand_chip;
174 struct device *parent;
175 void __iomem *base;
176 void (*select_chip)(int chip_no);
177 int irq;
178 wait_queue_head_t irq_waitq;
179
180 bool spurious_irq_expected;
181 u32 irq_status;
182
183 u32 ctrl_reg;
184 bool small_page;
185 unsigned int addr_count0;
186 unsigned int addr_count1;
187
188 u8 *buf;
189 dma_addr_t buf_dma;
190 unsigned int buf_size;
191 int buf_index;
192
193 int erase1_page_addr;
194
195 int rndout_page_addr;
196 int rndout_read_cmd;
197
198 int seqin_page_addr;
199 int seqin_column;
200 int seqin_read_cmd;
201 };
202
203 static void ar934x_nfc_restart(struct ar934x_nfc *nfc);
204
205 static inline void
206 ar934x_nfc_wr(struct ar934x_nfc *nfc, unsigned reg, u32 val)
207 {
208 __raw_writel(val, nfc->base + reg);
209 }
210
211 static inline u32
212 ar934x_nfc_rr(struct ar934x_nfc *nfc, unsigned reg)
213 {
214 return __raw_readl(nfc->base + reg);
215 }
216
217 static inline struct ar934x_nfc_platform_data *
218 ar934x_nfc_get_platform_data(struct ar934x_nfc *nfc)
219 {
220 return nfc->parent->platform_data;
221 }
222
223 static inline struct
224 ar934x_nfc *mtd_to_ar934x_nfc(struct mtd_info *mtd)
225 {
226 return container_of(mtd, struct ar934x_nfc, mtd);
227 }
228
229 static inline bool ar934x_nfc_use_irq(struct ar934x_nfc *nfc)
230 {
231 return AR934X_NFC_USE_IRQ;
232 }
233
234 static inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc *nfc, u32 cmd_reg)
235 {
236 wmb();
237
238 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CMD, cmd_reg);
239 /* flush write */
240 ar934x_nfc_rr(nfc, AR934X_NFC_REG_CMD);
241 }
242
243 static bool
244 __ar934x_nfc_dev_ready(struct ar934x_nfc *nfc)
245 {
246 u32 status;
247
248 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS);
249 return (status & 0xff) == 0xff;
250 }
251
252 static inline bool
253 __ar934x_nfc_is_dma_ready(struct ar934x_nfc *nfc)
254 {
255 u32 status;
256
257 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL);
258 return (status & AR934X_NFC_DMA_CTRL_DMA_READY) != 0;
259 }
260
261 static int
262 ar934x_nfc_wait_dev_ready(struct ar934x_nfc *nfc)
263 {
264 unsigned long timeout;
265
266 timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT);
267 do {
268 if (__ar934x_nfc_dev_ready(nfc))
269 return 0;
270 } while time_before(jiffies, timeout);
271
272 nfc_dbg(nfc, "timeout waiting for device ready, status:%08x int:%08x\n",
273 ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS),
274 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS));
275 return -ETIMEDOUT;
276 }
277
278 static int
279 ar934x_nfc_wait_dma_ready(struct ar934x_nfc *nfc)
280 {
281 unsigned long timeout;
282
283 timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT);
284 do {
285 if (__ar934x_nfc_is_dma_ready(nfc))
286 return 0;
287 } while time_before(jiffies, timeout);
288
289 nfc_dbg(nfc, "timeout waiting for DMA ready, dma_ctrl:%08x\n",
290 ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL));
291 return -ETIMEDOUT;
292 }
293
294 static int
295 ar934x_nfc_wait_irq(struct ar934x_nfc *nfc)
296 {
297 long timeout;
298 int ret;
299
300 timeout = wait_event_timeout(nfc->irq_waitq,
301 (nfc->irq_status & AR934X_NFC_IRQ_MASK) != 0,
302 msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT));
303
304 ret = 0;
305 if (!timeout) {
306 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, 0);
307 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
308 /* flush write */
309 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
310
311 nfc_dbg(nfc,
312 "timeout waiting for interrupt, status:%08x\n",
313 nfc->irq_status);
314 ret = -ETIMEDOUT;
315 }
316
317 nfc->irq_status = 0;
318 return ret;
319 }
320
321 static int
322 ar934x_nfc_wait_done(struct ar934x_nfc *nfc)
323 {
324 int ret;
325
326 if (ar934x_nfc_use_irq(nfc))
327 ret = ar934x_nfc_wait_irq(nfc);
328 else
329 ret = ar934x_nfc_wait_dev_ready(nfc);
330
331 if (ret)
332 return ret;
333
334 return ar934x_nfc_wait_dma_ready(nfc);
335 }
336
337 static int
338 ar934x_nfc_alloc_buf(struct ar934x_nfc *nfc, unsigned size)
339 {
340 nfc->buf = dma_alloc_coherent(nfc->parent, size,
341 &nfc->buf_dma, GFP_KERNEL);
342 if (nfc->buf == NULL) {
343 dev_err(nfc->parent, "no memory for DMA buffer\n");
344 return -ENOMEM;
345 }
346
347 nfc->buf_size = size;
348 nfc_dbg(nfc, "buf:%p size:%u\n", nfc->buf, nfc->buf_size);
349
350 return 0;
351 }
352
353 static void
354 ar934x_nfc_free_buf(struct ar934x_nfc *nfc)
355 {
356 dma_free_coherent(nfc->parent, nfc->buf_size, nfc->buf, nfc->buf_dma);
357 }
358
359 static void
360 ar934x_nfc_get_addr(struct ar934x_nfc *nfc, int column, int page_addr,
361 u32 *addr0, u32 *addr1)
362 {
363 u32 a0, a1;
364
365 a0 = 0;
366 a1 = 0;
367
368 if (column == -1) {
369 /* ERASE1 */
370 a0 = (page_addr & 0xffff) << 16;
371 a1 = (page_addr >> 16) & 0xf;
372 } else if (page_addr != -1) {
373 /* SEQIN, READ0, etc.. */
374
375 /* TODO: handle 16bit bus width */
376 if (nfc->small_page) {
377 a0 = column & 0xff;
378 a0 |= (page_addr & 0xff) << 8;
379 a0 |= ((page_addr >> 8) & 0xff) << 16;
380 a0 |= ((page_addr >> 16) & 0xff) << 24;
381 } else {
382 a0 = column & 0x0FFF;
383 a0 |= (page_addr & 0xffff) << 16;
384
385 if (nfc->addr_count0 > 4)
386 a1 = (page_addr >> 16) & 0xf;
387 }
388 }
389
390 *addr0 = a0;
391 *addr1 = a1;
392 }
393
394 static void
395 ar934x_nfc_send_cmd(struct ar934x_nfc *nfc, unsigned command)
396 {
397 u32 cmd_reg;
398
399 cmd_reg = AR934X_NFC_CMD_INPUT_SEL_SIU | AR934X_NFC_CMD_ADDR_SEL_0 |
400 AR934X_NFC_CMD_SEQ_1C;
401 cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
402
403 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
404 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
405
406 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
407 ar934x_nfc_wait_dev_ready(nfc);
408 }
409
410 static void
411 ar934x_nfc_do_rw_command(struct ar934x_nfc *nfc, int column, int page_addr,
412 int len, u32 cmd_reg, u32 ctrl_reg, bool write)
413 {
414 u32 addr0, addr1;
415 u32 dma_ctrl;
416 int dir;
417 int err;
418 int retries = 0;
419
420 WARN_ON(len & 3);
421
422 if (WARN_ON(len > nfc->buf_size))
423 dev_err(nfc->parent, "len=%d > buf_size=%d", len, nfc->buf_size);
424
425 if (write) {
426 dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE;
427 dir = DMA_TO_DEVICE;
428 } else {
429 dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_READ;
430 dir = DMA_FROM_DEVICE;
431 }
432
433 ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
434
435 dma_ctrl |= AR934X_NFC_DMA_CTRL_DMA_START |
436 (AR934X_NFC_DMA_CTRL_DMA_BURST_3 <<
437 AR934X_NFC_DMA_CTRL_DMA_BURST_S);
438
439 cmd_reg |= AR934X_NFC_CMD_INPUT_SEL_DMA | AR934X_NFC_CMD_ADDR_SEL_0;
440 ctrl_reg |= AR934X_NFC_CTRL_INT_EN;
441
442 nfc_dbg(nfc, "%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\n",
443 (write) ? "write" : "read",
444 addr0, addr1, len, cmd_reg, dma_ctrl, ctrl_reg);
445
446 retry:
447 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
448 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
449 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
450 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR, nfc->buf_dma);
451 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_COUNT, len);
452 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DATA_SIZE, len);
453 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
454 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_CTRL, dma_ctrl);
455
456 if (ar934x_nfc_use_irq(nfc)) {
457 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, AR934X_NFC_IRQ_MASK);
458 /* flush write */
459 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
460 }
461
462 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
463 err = ar934x_nfc_wait_done(nfc);
464 if (err) {
465 dev_dbg(nfc->parent, "%s operation stuck at page %d\n",
466 (write) ? "write" : "read", page_addr);
467
468 ar934x_nfc_restart(nfc);
469 if (retries++ < AR934X_NFC_DMA_RETRIES)
470 goto retry;
471
472 dev_err(nfc->parent, "%s operation failed on page %d\n",
473 (write) ? "write" : "read", page_addr);
474 }
475 }
476
477 static void
478 ar934x_nfc_send_readid(struct ar934x_nfc *nfc, unsigned command)
479 {
480 u32 cmd_reg;
481
482 nfc_dbg(nfc, "readid, cmd:%02x\n", command);
483
484 cmd_reg = AR934X_NFC_CMD_SEQ_1C1AXR;
485 cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
486
487 ar934x_nfc_do_rw_command(nfc, -1, -1, AR934X_NFC_ID_BUF_SIZE, cmd_reg,
488 nfc->ctrl_reg, false);
489
490 nfc_debug_data("[id] ", nfc->buf, AR934X_NFC_ID_BUF_SIZE);
491 }
492
493 static void
494 ar934x_nfc_send_read(struct ar934x_nfc *nfc, unsigned command, int column,
495 int page_addr, int len, bool oob)
496 {
497 u32 cmd_reg;
498
499 nfc_dbg(nfc, "read, column=%d page=%d len=%d oob:%d\n",
500 column, page_addr, len, oob);
501
502 cmd_reg = (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
503
504 if (nfc->small_page) {
505 cmd_reg |= AR934X_NFC_CMD_SEQ_18;
506 } else {
507 cmd_reg |= NAND_CMD_READSTART << AR934X_NFC_CMD_CMD1_S;
508 cmd_reg |= AR934X_NFC_CMD_SEQ_1C5A1CXR;
509 }
510
511 ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
512 cmd_reg, nfc->ctrl_reg, false);
513
514 nfc_debug_data("[data] ", nfc->buf, len);
515 }
516
517 static void
518 ar934x_nfc_send_erase(struct ar934x_nfc *nfc, unsigned command, int column,
519 int page_addr)
520 {
521 u32 addr0, addr1;
522 u32 ctrl_reg;
523 u32 cmd_reg;
524
525 ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
526
527 ctrl_reg = nfc->ctrl_reg;
528 if (nfc->small_page) {
529 /* override number of address cycles for the erase command */
530 ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M <<
531 AR934X_NFC_CTRL_ADDR_CYCLE0_S);
532 ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M <<
533 AR934X_NFC_CTRL_ADDR_CYCLE1_S);
534 ctrl_reg &= ~(AR934X_NFC_CTRL_SMALL_PAGE);
535 ctrl_reg |= (nfc->addr_count0 + 1) <<
536 AR934X_NFC_CTRL_ADDR_CYCLE0_S;
537 }
538
539 cmd_reg = NAND_CMD_ERASE1 << AR934X_NFC_CMD_CMD0_S;
540 cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
541 cmd_reg |= AR934X_NFC_CMD_SEQ_ERASE;
542
543 nfc_dbg(nfc, "erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\n",
544 page_addr, addr0, addr1, cmd_reg, ctrl_reg);
545
546 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
547 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
548 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
549 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
550
551 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
552 ar934x_nfc_wait_dev_ready(nfc);
553 }
554
555 static void
556 ar934x_nfc_send_write(struct ar934x_nfc *nfc, unsigned command, int column,
557 int page_addr, int len)
558 {
559 u32 cmd_reg;
560
561 nfc_dbg(nfc, "write, column=%d page=%d len=%d\n",
562 column, page_addr, len);
563
564 nfc_debug_data("[data] ", nfc->buf, len);
565
566 cmd_reg = NAND_CMD_SEQIN << AR934X_NFC_CMD_CMD0_S;
567 cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
568 cmd_reg |= AR934X_NFC_CMD_SEQ_12;
569
570 ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
571 cmd_reg, nfc->ctrl_reg, true);
572 }
573
574 static void
575 ar934x_nfc_read_status(struct ar934x_nfc *nfc)
576 {
577 u32 cmd_reg;
578 u32 status;
579
580 cmd_reg = NAND_CMD_STATUS << AR934X_NFC_CMD_CMD0_S;
581 cmd_reg |= AR934X_NFC_CMD_SEQ_S;
582
583 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
584 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
585
586 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
587 ar934x_nfc_wait_dev_ready(nfc);
588
589 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_READ_STATUS);
590
591 nfc_dbg(nfc, "read status, cmd:%08x status:%02x\n",
592 cmd_reg, (status & 0xff));
593
594 nfc->buf[0 ^ 3] = status;
595 }
596
597 static void
598 ar934x_nfc_cmdfunc(struct mtd_info *mtd, unsigned int command, int column,
599 int page_addr)
600 {
601 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
602
603 if (command != NAND_CMD_PAGEPROG)
604 nfc->buf_index = 0;
605
606 switch (command) {
607 case NAND_CMD_RESET:
608 ar934x_nfc_send_cmd(nfc, command);
609 break;
610
611 case NAND_CMD_READID:
612 ar934x_nfc_send_readid(nfc, command);
613 break;
614
615 case NAND_CMD_READ0:
616 case NAND_CMD_READ1:
617 if (nfc->small_page) {
618 ar934x_nfc_send_read(nfc, command, column, page_addr,
619 mtd->writesize + mtd->oobsize,
620 false);
621 } else {
622 ar934x_nfc_send_read(nfc, command, 0, page_addr,
623 mtd->writesize + mtd->oobsize,
624 false);
625 nfc->buf_index = column;
626 nfc->rndout_page_addr = page_addr;
627 nfc->rndout_read_cmd = command;
628 }
629 break;
630
631 case NAND_CMD_READOOB:
632 if (nfc->small_page)
633 ar934x_nfc_send_read(nfc, NAND_CMD_READOOB,
634 column, page_addr,
635 mtd->oobsize,
636 true);
637 else
638 ar934x_nfc_send_read(nfc, NAND_CMD_READ0,
639 mtd->writesize, page_addr,
640 mtd->oobsize,
641 true);
642 break;
643
644 case NAND_CMD_RNDOUT:
645 if (WARN_ON(nfc->small_page))
646 break;
647
648 /* emulate subpage read */
649 ar934x_nfc_send_read(nfc, nfc->rndout_read_cmd, 0,
650 nfc->rndout_page_addr,
651 mtd->writesize + mtd->oobsize, false);
652 nfc->buf_index = column;
653 break;
654
655 case NAND_CMD_ERASE1:
656 nfc->erase1_page_addr = page_addr;
657 break;
658
659 case NAND_CMD_ERASE2:
660 ar934x_nfc_send_erase(nfc, command, -1, nfc->erase1_page_addr);
661 break;
662
663 case NAND_CMD_STATUS:
664 ar934x_nfc_read_status(nfc);
665 break;
666
667 case NAND_CMD_SEQIN:
668 if (nfc->small_page) {
669 /* output read command */
670 if (column >= mtd->writesize) {
671 column -= mtd->writesize;
672 nfc->seqin_read_cmd = NAND_CMD_READOOB;
673 } else if (column < 256) {
674 nfc->seqin_read_cmd = NAND_CMD_READ0;
675 } else {
676 column -= 256;
677 nfc->seqin_read_cmd = NAND_CMD_READ1;
678 }
679 } else {
680 nfc->seqin_read_cmd = NAND_CMD_READ0;
681 }
682 nfc->seqin_column = column;
683 nfc->seqin_page_addr = page_addr;
684 break;
685
686 case NAND_CMD_PAGEPROG:
687 if (nfc->small_page)
688 ar934x_nfc_send_cmd(nfc, nfc->seqin_read_cmd);
689
690 ar934x_nfc_send_write(nfc, command, nfc->seqin_column,
691 nfc->seqin_page_addr,
692 nfc->buf_index);
693 break;
694
695 default:
696 dev_err(nfc->parent,
697 "unsupported command: %x, column:%d page_addr=%d\n",
698 command, column, page_addr);
699 break;
700 }
701 }
702
703 static int
704 ar934x_nfc_dev_ready(struct mtd_info *mtd)
705 {
706 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
707
708 return __ar934x_nfc_dev_ready(nfc);
709 }
710
711 static void
712 ar934x_nfc_select_chip(struct mtd_info *mtd, int chip_no)
713 {
714 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
715
716 if (nfc->select_chip)
717 nfc->select_chip(chip_no);
718 }
719
720 static u8
721 ar934x_nfc_read_byte(struct mtd_info *mtd)
722 {
723 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
724 unsigned int buf_index;
725 u8 data;
726
727 WARN_ON(nfc->buf_index >= nfc->buf_size);
728
729 buf_index = nfc->buf_index ^ 3;
730 data = nfc->buf[buf_index];
731 nfc->buf_index++;
732
733 return data;
734 }
735
736 static void
737 ar934x_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
738 {
739 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
740 int i;
741
742 WARN_ON(nfc->buf_index + len > nfc->buf_size);
743
744 for (i = 0; i < len; i++) {
745 nfc->buf[nfc->buf_index ^ 3] = buf[i];
746 nfc->buf_index++;
747 }
748 }
749
750 static void
751 ar934x_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
752 {
753 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
754 int buf_index;
755 int i;
756
757 WARN_ON(nfc->buf_index + len > nfc->buf_size);
758
759 buf_index = nfc->buf_index;
760
761 for (i = 0; i < len; i++) {
762 buf[i] = nfc->buf[buf_index ^ 3];
763 buf_index++;
764 }
765
766 nfc->buf_index = buf_index;
767 }
768
769 static int
770 ar934x_nfc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
771 {
772 int i;
773
774 for (i = 0; i < len; i++)
775 if (buf[i] != ar934x_nfc_read_byte(mtd))
776 return -EFAULT;
777
778 return 0;
779 }
780
781 static void
782 ar934x_nfc_hw_init(struct ar934x_nfc *nfc)
783 {
784 struct ar934x_nfc_platform_data *pdata;
785
786 pdata = ar934x_nfc_get_platform_data(nfc);
787 if (pdata->hw_reset) {
788 pdata->hw_reset(true);
789 pdata->hw_reset(false);
790 }
791
792 /*
793 * setup timings
794 * TODO: make it configurable via platform data
795 */
796 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIME_SEQ,
797 AR934X_NFC_TIME_SEQ_DEFAULT);
798 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_ASYN,
799 AR934X_NFC_TIMINGS_ASYN_DEFAULT);
800 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_SYN,
801 AR934X_NFC_TIMINGS_SYN_DEFAULT);
802
803 /* disable WP on all chips, and select chip 0 */
804 ar934x_nfc_wr(nfc, AR934X_NFC_REG_MEM_CTRL, 0xff00);
805
806 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR_OFFS, 0);
807
808 /* initialize Control register */
809 nfc->ctrl_reg = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
810 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
811
812 if (nfc->small_page) {
813 /* Setup generic sequence register for small page reads. */
814 ar934x_nfc_wr(nfc, AR934X_NFC_REG_GEN_SEQ_CTRL,
815 AR934X_NFC_GENSEQ_SMALL_PAGE_READ);
816 }
817 }
818
819 static void
820 ar934x_nfc_restart(struct ar934x_nfc *nfc)
821 {
822 u32 ctrl_reg;
823
824 if (nfc->select_chip)
825 nfc->select_chip(-1);
826
827 ctrl_reg = nfc->ctrl_reg;
828 ar934x_nfc_hw_init(nfc);
829 nfc->ctrl_reg = ctrl_reg;
830
831 if (nfc->select_chip)
832 nfc->select_chip(0);
833
834 ar934x_nfc_send_cmd(nfc, NAND_CMD_RESET);
835 }
836
837 static irqreturn_t
838 ar934x_nfc_irq_handler(int irq, void *data)
839 {
840 struct ar934x_nfc *nfc = data;
841 u32 status;
842
843 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
844
845 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
846 /* flush write */
847 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
848
849 status &= ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
850 if (status) {
851 nfc_dbg(nfc, "got IRQ, status:%08x\n", status);
852
853 nfc->irq_status = status;
854 nfc->spurious_irq_expected = true;
855 wake_up(&nfc->irq_waitq);
856 } else {
857 if (nfc->spurious_irq_expected) {
858 nfc->spurious_irq_expected = false;
859 } else {
860 dev_warn(nfc->parent, "spurious interrupt\n");
861 }
862 }
863
864 return IRQ_HANDLED;
865 }
866
867 static int __devinit
868 ar934x_nfc_init_tail(struct mtd_info *mtd)
869 {
870 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
871 struct nand_chip *chip = &nfc->nand_chip;
872 u32 ctrl;
873 u32 t;
874 int err;
875
876 switch (mtd->oobsize) {
877 case 16:
878 case 64:
879 case 128:
880 ar934x_nfc_wr(nfc, AR934X_NFC_REG_SPARE_SIZE, mtd->oobsize);
881 break;
882
883 default:
884 dev_err(nfc->parent, "unsupported OOB size: %d bytes\n",
885 mtd->oobsize);
886 return -ENXIO;
887 }
888
889 ctrl = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
890
891 switch (mtd->erasesize / mtd->writesize) {
892 case 32:
893 t = AR934X_NFC_CTRL_BLOCK_SIZE_32;
894 break;
895
896 case 64:
897 t = AR934X_NFC_CTRL_BLOCK_SIZE_64;
898 break;
899
900 case 128:
901 t = AR934X_NFC_CTRL_BLOCK_SIZE_128;
902 break;
903
904 case 256:
905 t = AR934X_NFC_CTRL_BLOCK_SIZE_256;
906 break;
907
908 default:
909 dev_err(nfc->parent, "unsupported block size: %u\n",
910 mtd->erasesize / mtd->writesize);
911 return -ENXIO;
912 }
913
914 ctrl |= t << AR934X_NFC_CTRL_BLOCK_SIZE_S;
915
916 switch (mtd->writesize) {
917 case 256:
918 nfc->small_page = 1;
919 t = AR934X_NFC_CTRL_PAGE_SIZE_256;
920 break;
921
922 case 512:
923 nfc->small_page = 1;
924 t = AR934X_NFC_CTRL_PAGE_SIZE_512;
925 break;
926
927 case 1024:
928 t = AR934X_NFC_CTRL_PAGE_SIZE_1024;
929 break;
930
931 case 2048:
932 t = AR934X_NFC_CTRL_PAGE_SIZE_2048;
933 break;
934
935 case 4096:
936 t = AR934X_NFC_CTRL_PAGE_SIZE_4096;
937 break;
938
939 case 8192:
940 t = AR934X_NFC_CTRL_PAGE_SIZE_8192;
941 break;
942
943 case 16384:
944 t = AR934X_NFC_CTRL_PAGE_SIZE_16384;
945 break;
946
947 default:
948 dev_err(nfc->parent, "unsupported write size: %d bytes\n",
949 mtd->writesize);
950 return -ENXIO;
951 }
952
953 ctrl |= t << AR934X_NFC_CTRL_PAGE_SIZE_S;
954
955 if (nfc->small_page) {
956 ctrl |= AR934X_NFC_CTRL_SMALL_PAGE;
957
958 if (chip->chipsize > (32 << 20)) {
959 nfc->addr_count0 = 4;
960 nfc->addr_count1 = 3;
961 } else if (chip->chipsize > (2 << 16)) {
962 nfc->addr_count0 = 3;
963 nfc->addr_count1 = 2;
964 } else {
965 nfc->addr_count0 = 2;
966 nfc->addr_count1 = 1;
967 }
968 } else {
969 if (chip->chipsize > (128 << 20)) {
970 nfc->addr_count0 = 5;
971 nfc->addr_count1 = 3;
972 } else if (chip->chipsize > (8 << 16)) {
973 nfc->addr_count0 = 4;
974 nfc->addr_count1 = 2;
975 } else {
976 nfc->addr_count0 = 3;
977 nfc->addr_count1 = 1;
978 }
979 }
980
981 ctrl |= nfc->addr_count0 << AR934X_NFC_CTRL_ADDR_CYCLE0_S;
982 ctrl |= nfc->addr_count1 << AR934X_NFC_CTRL_ADDR_CYCLE1_S;
983
984 nfc->ctrl_reg = ctrl;
985 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
986
987 ar934x_nfc_free_buf(nfc);
988 err = ar934x_nfc_alloc_buf(nfc, mtd->writesize + mtd->oobsize);
989
990 return err;
991 }
992
993 static int __devinit
994 ar934x_nfc_probe(struct platform_device *pdev)
995 {
996 static const char *part_probes[] = { "cmdlinepart", NULL, };
997 struct ar934x_nfc_platform_data *pdata;
998 struct ar934x_nfc *nfc;
999 struct resource *res;
1000 struct mtd_info *mtd;
1001 struct nand_chip *nand;
1002 struct mtd_part_parser_data ppdata;
1003 int ret;
1004
1005 pdata = pdev->dev.platform_data;
1006 if (pdata == NULL) {
1007 dev_err(&pdev->dev, "no platform data defined\n");
1008 return -EINVAL;
1009 }
1010
1011 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1012 if (!res) {
1013 dev_err(&pdev->dev, "failed to get I/O memory\n");
1014 return -EINVAL;
1015 }
1016
1017 nfc = kzalloc(sizeof(struct ar934x_nfc), GFP_KERNEL);
1018 if (!nfc) {
1019 dev_err(&pdev->dev, "failed to allocate driver data\n");
1020 return -ENOMEM;
1021 }
1022
1023 nfc->base = ioremap(res->start, resource_size(res));
1024 if (nfc->base == NULL) {
1025 dev_err(&pdev->dev, "failed to remap I/O memory\n");
1026 ret = -ENXIO;
1027 goto err_free_nand;
1028 }
1029
1030 nfc->irq = platform_get_irq(pdev, 0);
1031 if (nfc->irq < 0) {
1032 dev_err(&pdev->dev, "no IRQ resource specified\n");
1033 ret = -EINVAL;
1034 goto err_unmap;
1035 }
1036
1037 init_waitqueue_head(&nfc->irq_waitq);
1038 ret = request_irq(nfc->irq, ar934x_nfc_irq_handler, IRQF_DISABLED,
1039 dev_name(&pdev->dev), nfc);
1040 if (ret) {
1041 dev_err(&pdev->dev, "requast_irq failed, err:%d\n", ret);
1042 goto err_unmap;
1043 }
1044
1045 nfc->parent = &pdev->dev;
1046 nfc->select_chip = pdata->select_chip;
1047
1048 nand = &nfc->nand_chip;
1049 mtd = &nfc->mtd;
1050
1051 mtd->priv = nand;
1052 mtd->owner = THIS_MODULE;
1053 if (pdata->name)
1054 mtd->name = pdata->name;
1055 else
1056 mtd->name = dev_name(&pdev->dev);
1057
1058 nand->options = NAND_NO_AUTOINCR;
1059 nand->chip_delay = 25;
1060 nand->ecc.mode = NAND_ECC_SOFT;
1061
1062 nand->dev_ready = ar934x_nfc_dev_ready;
1063 nand->cmdfunc = ar934x_nfc_cmdfunc;
1064 nand->read_byte = ar934x_nfc_read_byte;
1065 nand->write_buf = ar934x_nfc_write_buf;
1066 nand->read_buf = ar934x_nfc_read_buf;
1067 nand->verify_buf = ar934x_nfc_verify_buf;
1068 nand->select_chip = ar934x_nfc_select_chip;
1069
1070 ret = ar934x_nfc_alloc_buf(nfc, AR934X_NFC_ID_BUF_SIZE);
1071 if (ret)
1072 goto err_free_irq;
1073
1074 platform_set_drvdata(pdev, nfc);
1075
1076 ar934x_nfc_hw_init(nfc);
1077
1078 ret = nand_scan_ident(mtd, 1, NULL);
1079 if (ret) {
1080 dev_err(&pdev->dev, "nand_scan_ident failed, err:%d\n", ret);
1081 goto err_free_buf;
1082 }
1083
1084 ret = ar934x_nfc_init_tail(mtd);
1085 if (ret) {
1086 dev_err(&pdev->dev, "init tail failed, err:%d\n", ret);
1087 goto err_free_buf;
1088 }
1089
1090 if (pdata->scan_fixup) {
1091 ret = pdata->scan_fixup(mtd);
1092 if (ret)
1093 goto err_free_buf;
1094 }
1095
1096 ret = nand_scan_tail(mtd);
1097 if (ret) {
1098 dev_err(&pdev->dev, "scan tail failed, err:%d\n", ret);
1099 goto err_free_buf;
1100 }
1101
1102 memset(&ppdata, '\0', sizeof(ppdata));
1103 ret = mtd_device_parse_register(mtd, part_probes, &ppdata,
1104 pdata->parts, pdata->nr_parts);
1105 if (ret) {
1106 dev_err(&pdev->dev, "unable to register mtd, err:%d\n", ret);
1107 goto err_free_buf;
1108 }
1109
1110 return 0;
1111
1112 err_free_buf:
1113 ar934x_nfc_free_buf(nfc);
1114 err_free_irq:
1115 free_irq(nfc->irq, nfc);
1116 err_unmap:
1117 iounmap(nfc->base);
1118 err_free_nand:
1119 kfree(nfc);
1120 platform_set_drvdata(pdev, NULL);
1121 return ret;
1122 }
1123
1124 static int __devexit
1125 ar934x_nfc_remove(struct platform_device *pdev)
1126 {
1127 struct ar934x_nfc *nfc;
1128
1129 nfc = platform_get_drvdata(pdev);
1130 if (nfc) {
1131 nand_release(&nfc->mtd);
1132 ar934x_nfc_free_buf(nfc);
1133 free_irq(nfc->irq, nfc);
1134 iounmap(nfc->base);
1135 kfree(nfc);
1136 }
1137
1138 return 0;
1139 }
1140
1141 static struct platform_driver ar934x_nfc_driver = {
1142 .probe = ar934x_nfc_probe,
1143 .remove = __devexit_p(ar934x_nfc_remove),
1144 .driver = {
1145 .name = AR934X_NFC_DRIVER_NAME,
1146 .owner = THIS_MODULE,
1147 },
1148 };
1149
1150 module_platform_driver(ar934x_nfc_driver);
1151
1152 MODULE_LICENSE("GPL v2");
1153 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1154 MODULE_DESCRIPTION("Atheros AR934x NAND Flash Controller driver");
1155 MODULE_ALIAS("platform:" AR934X_NFC_DRIVER_NAME);
Staging tree of Mathias Kresin