target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c

   1 /*
   2  *  MikroTik RouterBOARD 2011 support
   3  *
   4  *  Copyright (C) 2012 Stijn Tintel <stijn@linux-ipv6.be>
   5  *  Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms of the GNU General Public License version 2 as published
   9  *  by the Free Software Foundation.
  10  */
  11
  12 #define pr_fmt(fmt) "rb2011: " fmt
  13
  14 #include <linux/phy.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/ath9k_platform.h>
  17 #include <linux/ar8216_platform.h>
  18 #include <linux/mtd/mtd.h>
  19 #include <linux/mtd/partitions.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/spi/flash.h>
  22 #include <linux/rle.h>
  23 #include <linux/routerboot.h>
  24
  25 #include <asm/mach-ath79/ath79.h>
  26 #include <asm/mach-ath79/ar71xx_regs.h>
  27
  28 #include "common.h"
  29 #include "dev-eth.h"
  30 #include "dev-m25p80.h"
  31 #include "dev-wmac.h"
  32 #include "machtypes.h"
  33 #include "routerboot.h"
  34
  35 #define RB_ROUTERBOOT_OFFSET    0x0000
  36 #define RB_ROUTERBOOT_SIZE      0xb000
  37 #define RB_HARD_CFG_OFFSET      0xb000
  38 #define RB_HARD_CFG_SIZE        0x1000
  39 #define RB_BIOS_OFFSET          0xd000
  40 #define RB_BIOS_SIZE            0x2000
  41 #define RB_SOFT_CFG_OFFSET      0xf000
  42 #define RB_SOFT_CFG_SIZE        0x1000
  43
  44 #define RB_ART_SIZE             0x10000
  45
  46 static struct mtd_partition rb2011_spi_partitions[] = {
  47         {
  48                 .name           = "routerboot",
  49                 .offset         = RB_ROUTERBOOT_OFFSET,
  50                 .size           = RB_ROUTERBOOT_SIZE,
  51                 .mask_flags     = MTD_WRITEABLE,
  52         }, {
  53                 .name           = "hard_config",
  54                 .offset         = RB_HARD_CFG_OFFSET,
  55                 .size           = RB_HARD_CFG_SIZE,
  56                 .mask_flags     = MTD_WRITEABLE,
  57         }, {
  58                 .name           = "bios",
  59                 .offset         = RB_BIOS_OFFSET,
  60                 .size           = RB_BIOS_SIZE,
  61                 .mask_flags     = MTD_WRITEABLE,
  62         }, {
  63                 .name           = "soft_config",
  64                 .offset         = RB_SOFT_CFG_OFFSET,
  65                 .size           = RB_SOFT_CFG_SIZE,
  66         }
  67 };
  68
  69 static struct flash_platform_data rb2011_spi_flash_data = {
  70         .parts          = rb2011_spi_partitions,
  71         .nr_parts       = ARRAY_SIZE(rb2011_spi_partitions),
  72 };
  73
  74 static struct ar8327_pad_cfg rb2011_ar8327_pad0_cfg = {
  75         .mode = AR8327_PAD_MAC_RGMII,
  76         .txclk_delay_en = true,
  77         .rxclk_delay_en = true,
  78         .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  79         .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  80 };
  81
  82 static struct ar8327_platform_data rb2011_ar8327_data = {
  83         .pad0_cfg = &rb2011_ar8327_pad0_cfg,
  84         .cpuport_cfg = {
  85                 .force_link = 1,
  86                 .speed = AR8327_PORT_SPEED_1000,
  87                 .duplex = 1,
  88                 .txpause = 1,
  89                 .rxpause = 1,
  90         }
  91 };
  92
  93 static struct mdio_board_info rb2011_mdio0_info[] = {
  94         {
  95                 .bus_id = "ag71xx-mdio.0",
  96                 .phy_addr = 0,
  97                 .platform_data = &rb2011_ar8327_data,
  98         },
  99 };
 100
 101 static void __init rb2011_gmac_setup(void)
 102 {
 103         void __iomem *base;
 104         u32 t;
 105
 106         base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
 107
 108         t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
 109         t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
 110                 AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
 111         t |= AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE;
 112
 113         __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
 114
 115         iounmap(base);
 116 }
 117
 118 static void __init rb2011_wlan_init(void)
 119 {
 120         u8 *hard_cfg = (u8 *) KSEG1ADDR(0x1f000000 + RB_HARD_CFG_OFFSET);
 121         u16 tag_len;
 122         u8 *tag;
 123         char *art_buf;
 124         u8 wlan_mac[ETH_ALEN];
 125         int err;
 126
 127         err = routerboot_find_tag(hard_cfg, RB_HARD_CFG_SIZE, RB_ID_WLAN_DATA,
 128                                   &tag, &tag_len);
 129         if (err) {
 130                 pr_err("no calibration data found\n");
 131                 return;
 132         }
 133
 134         art_buf = kmalloc(RB_ART_SIZE, GFP_KERNEL);
 135         if (art_buf == NULL) {
 136                 pr_err("no memory for calibration data\n");
 137                 return;
 138         }
 139
 140         err = rle_decode((char *) tag, tag_len, art_buf, RB_ART_SIZE,
 141                          NULL, NULL);
 142         if (err) {
 143                 pr_err("unable to decode calibration data\n");
 144                 goto free;
 145         }
 146
 147         ath79_init_mac(wlan_mac, ath79_mac_base, 11);
 148         ath79_register_wmac(art_buf + 0x1000, wlan_mac);
 149
 150 free:
 151         kfree(art_buf);
 152 }
 153
 154 static void __init rb2011_setup(void)
 155 {
 156         ath79_register_m25p80(&rb2011_spi_flash_data);
 157
 158         rb2011_gmac_setup();
 159
 160         ath79_register_mdio(1, 0x0);
 161         ath79_register_mdio(0, 0x0);
 162
 163         mdiobus_register_board_info(rb2011_mdio0_info,
 164                                     ARRAY_SIZE(rb2011_mdio0_info));
 165
 166         /* GMAC0 is connected to an ar8327 switch */
 167         ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
 168         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 169         ath79_eth0_data.phy_mask = BIT(0);
 170         ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 171         ath79_eth0_pll_data.pll_1000 = 0x06000000;
 172
 173         ath79_register_eth(0);
 174
 175         /* GMAC1 is connected to the internal switch */
 176         ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 5);
 177         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
 178         ath79_eth1_data.speed = SPEED_1000;
 179         ath79_eth1_data.duplex = DUPLEX_FULL;
 180
 181         ath79_register_eth(1);
 182 }
 183
 184 MIPS_MACHINE(ATH79_MACH_RB_2011L, "2011L", "MikroTik RouterBOARD 2011L",
 185              rb2011_setup);
 186
 187 static void __init rb2011g_setup(void)
 188 {
 189         rb2011_setup();
 190         rb2011_wlan_init();
 191 }
 192
 193 MIPS_MACHINE(ATH79_MACH_RB_2011G, "2011G", "MikroTik RouterBOARD 2011UAS-2HnD",
 194              rb2011g_setup);