projects / openwrt / staging / mkresin.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ltq-atm/ltq-ptm: add kernel 5.10 compatiblity
[openwrt/staging/mkresin.git] / package / kernel / lantiq / ltq-ptm / src / ifxmips_ptm_vdsl.c
1 /******************************************************************************
2 **
3 ** FILE NAME : ifxmips_ptm_vdsl.c
4 ** PROJECT : UEIP
5 ** MODULES : PTM
6 **
7 ** DATE : 7 Jul 2009
8 ** AUTHOR : Xu Liang
9 ** DESCRIPTION : PTM driver common source file (core functions for VR9)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
13 **
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
18 **
19 ** HISTORY
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 *******************************************************************************/
23
24 #include <linux/version.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/ctype.h>
29 #include <linux/errno.h>
30 #include <linux/proc_fs.h>
31 #include <linux/init.h>
32 #include <linux/ioctl.h>
33 #include <linux/etherdevice.h>
34 #include <linux/interrupt.h>
35 #include <linux/netdevice.h>
36 #include <linux/platform_device.h>
37 #include <linux/of_device.h>
38
39 #include "ifxmips_ptm_vdsl.h"
40 #include <lantiq_soc.h>
41
42 #define MODULE_PARM_ARRAY(a, b) module_param_array(a, int, NULL, 0)
43 #define MODULE_PARM(a, b) module_param(a, int, 0)
44
45 static int wanqos_en = 0;
46 static int queue_gamma_map[4] = {0xFE, 0x01, 0x00, 0x00};
47
48 MODULE_PARM(wanqos_en, "i");
49 MODULE_PARM_DESC(wanqos_en, "WAN QoS support, 1 - enabled, 0 - disabled.");
50
51 MODULE_PARM_ARRAY(queue_gamma_map, "4-4i");
52 MODULE_PARM_DESC(queue_gamma_map, "TX QoS queues mapping to 4 TX Gamma interfaces.");
53
54 extern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *);
55 extern int (*ifx_mei_atm_showtime_exit)(void);
56 extern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr);
57
58 static int g_showtime = 0;
59 static void *g_xdata_addr = NULL;
60
61
62 #define ENABLE_TMP_DBG 0
63
64 unsigned long cgu_get_pp32_clock(void)
65 {
66 struct clk *c = clk_get_ppe();
67 unsigned long rate = clk_get_rate(c);
68 clk_put(c);
69 return rate;
70 }
71
72 static void ptm_setup(struct net_device *, int);
73 static struct net_device_stats *ptm_get_stats(struct net_device *);
74 static int ptm_open(struct net_device *);
75 static int ptm_stop(struct net_device *);
76 static unsigned int ptm_poll(int, unsigned int);
77 static int ptm_napi_poll(struct napi_struct *, int);
78 static int ptm_hard_start_xmit(struct sk_buff *, struct net_device *);
79 static int ptm_ioctl(struct net_device *, struct ifreq *, int);
80 #if LINUX_VERSION_CODE < KERNEL_VERSION(5,6,0)
81 static void ptm_tx_timeout(struct net_device *);
82 #else
83 static void ptm_tx_timeout(struct net_device *, unsigned int txqueue);
84 #endif
85
86 static inline struct sk_buff* alloc_skb_rx(void);
87 static inline struct sk_buff* alloc_skb_tx(unsigned int);
88 static inline struct sk_buff *get_skb_pointer(unsigned int);
89 static inline int get_tx_desc(unsigned int, unsigned int *);
90
91 /*
92 * Mailbox handler and signal function
93 */
94 static irqreturn_t mailbox_irq_handler(int, void *);
95
96 /*
97 * Tasklet to Handle Swap Descriptors
98 */
99 static void do_swap_desc_tasklet(unsigned long);
100
101
102 /*
103 * Init & clean-up functions
104 */
105 static inline int init_priv_data(void);
106 static inline void clear_priv_data(void);
107 static inline int init_tables(void);
108 static inline void clear_tables(void);
109
110 static int g_wanqos_en = 0;
111
112 static int g_queue_gamma_map[4];
113
114 static struct ptm_priv_data g_ptm_priv_data;
115
116 static struct net_device_ops g_ptm_netdev_ops = {
117 .ndo_get_stats = ptm_get_stats,
118 .ndo_open = ptm_open,
119 .ndo_stop = ptm_stop,
120 .ndo_start_xmit = ptm_hard_start_xmit,
121 .ndo_validate_addr = eth_validate_addr,
122 .ndo_set_mac_address = eth_mac_addr,
123 .ndo_do_ioctl = ptm_ioctl,
124 .ndo_tx_timeout = ptm_tx_timeout,
125 };
126
127 static struct net_device *g_net_dev[1] = {0};
128 static char *g_net_dev_name[1] = {"dsl0"};
129
130 static int g_ptm_prio_queue_map[8];
131
132 #if LINUX_VERSION_CODE < KERNEL_VERSION(5,9,0)
133 static DECLARE_TASKLET(g_swap_desc_tasklet, do_swap_desc_tasklet, 0);
134 #else
135 static DECLARE_TASKLET_OLD(g_swap_desc_tasklet, do_swap_desc_tasklet);
136 #endif
137
138
139 unsigned int ifx_ptm_dbg_enable = DBG_ENABLE_MASK_ERR;
140
141 /*
142 * ####################################
143 * Local Function
144 * ####################################
145 */
146
147 static void ptm_setup(struct net_device *dev, int ndev)
148 {
149 netif_carrier_off(dev);
150
151 dev->netdev_ops = &g_ptm_netdev_ops;
152 /* Allow up to 1508 bytes, for RFC4638 */
153 dev->max_mtu = ETH_DATA_LEN + 8;
154 netif_napi_add(dev, &g_ptm_priv_data.itf[ndev].napi, ptm_napi_poll, 16);
155 dev->watchdog_timeo = ETH_WATCHDOG_TIMEOUT;
156
157 dev->dev_addr[0] = 0x00;
158 dev->dev_addr[1] = 0x20;
159 dev->dev_addr[2] = 0xda;
160 dev->dev_addr[3] = 0x86;
161 dev->dev_addr[4] = 0x23;
162 dev->dev_addr[5] = 0x75 + ndev;
163 }
164
165 static struct net_device_stats *ptm_get_stats(struct net_device *dev)
166 {
167 struct net_device_stats *s;
168
169 if ( dev != g_net_dev[0] )
170 return NULL;
171 s = &g_ptm_priv_data.itf[0].stats;
172
173 return s;
174 }
175
176 static int ptm_open(struct net_device *dev)
177 {
178 ASSERT(dev == g_net_dev[0], "incorrect device");
179
180 napi_enable(&g_ptm_priv_data.itf[0].napi);
181
182 IFX_REG_W32_MASK(0, 1, MBOX_IGU1_IER);
183
184 netif_start_queue(dev);
185
186 return 0;
187 }
188
189 static int ptm_stop(struct net_device *dev)
190 {
191 ASSERT(dev == g_net_dev[0], "incorrect device");
192
193 IFX_REG_W32_MASK(1 | (1 << 17), 0, MBOX_IGU1_IER);
194
195 napi_disable(&g_ptm_priv_data.itf[0].napi);
196
197 netif_stop_queue(dev);
198
199 return 0;
200 }
201
202 static unsigned int ptm_poll(int ndev, unsigned int work_to_do)
203 {
204 unsigned int work_done = 0;
205 volatile struct rx_descriptor *desc;
206 struct rx_descriptor reg_desc;
207 struct sk_buff *skb, *new_skb;
208
209 ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), "ndev = %d (wrong value)", ndev);
210
211 while ( work_done < work_to_do ) {
212 desc = &WAN_RX_DESC_BASE[g_ptm_priv_data.itf[0].rx_desc_pos];
213 if ( desc->own /* || !desc->c */ ) // if PP32 hold descriptor or descriptor not completed
214 break;
215 if ( ++g_ptm_priv_data.itf[0].rx_desc_pos == WAN_RX_DESC_NUM )
216 g_ptm_priv_data.itf[0].rx_desc_pos = 0;
217
218 reg_desc = *desc;
219 skb = get_skb_pointer(reg_desc.dataptr);
220 ASSERT(skb != NULL, "invalid pointer skb == NULL");
221
222 new_skb = alloc_skb_rx();
223 if ( new_skb != NULL ) {
224 skb_reserve(skb, reg_desc.byteoff);
225 skb_put(skb, reg_desc.datalen);
226
227 // parse protocol header
228 skb->dev = g_net_dev[0];
229 skb->protocol = eth_type_trans(skb, skb->dev);
230
231 netif_receive_skb(skb);
232
233 g_ptm_priv_data.itf[0].stats.rx_packets++;
234 g_ptm_priv_data.itf[0].stats.rx_bytes += reg_desc.datalen;
235
236 reg_desc.dataptr = (unsigned int)new_skb->data & 0x0FFFFFFF;
237 reg_desc.byteoff = RX_HEAD_MAC_ADDR_ALIGNMENT;
238 }
239
240 reg_desc.datalen = RX_MAX_BUFFER_SIZE - RX_HEAD_MAC_ADDR_ALIGNMENT;
241 reg_desc.own = 1;
242 reg_desc.c = 0;
243
244 /* write discriptor to memory */
245 *((volatile unsigned int *)desc + 1) = *((unsigned int *)&reg_desc + 1);
246 wmb();
247 *(volatile unsigned int *)desc = *(unsigned int *)&reg_desc;
248
249 work_done++;
250 }
251
252 return work_done;
253 }
254
255 static int ptm_napi_poll(struct napi_struct *napi, int budget)
256 {
257 int ndev = 0;
258 unsigned int work_done;
259
260 work_done = ptm_poll(ndev, budget);
261
262 // interface down
263 if ( !netif_running(napi->dev) ) {
264 napi_complete(napi);
265 return work_done;
266 }
267
268 // clear interrupt
269 IFX_REG_W32_MASK(0, 1, MBOX_IGU1_ISRC);
270 // no more traffic
271 if (work_done < budget) {
272 napi_complete(napi);
273 IFX_REG_W32_MASK(0, 1, MBOX_IGU1_IER);
274 return work_done;
275 }
276
277 // next round
278 return work_done;
279 }
280
281 static int ptm_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
282 {
283 unsigned int f_full;
284 int desc_base;
285 volatile struct tx_descriptor *desc;
286 struct tx_descriptor reg_desc = {0};
287 struct sk_buff *skb_to_free;
288 unsigned int byteoff;
289
290 ASSERT(dev == g_net_dev[0], "incorrect device");
291
292 if ( !g_showtime ) {
293 err("not in showtime");
294 goto PTM_HARD_START_XMIT_FAIL;
295 }
296
297 /* allocate descriptor */
298 desc_base = get_tx_desc(0, &f_full);
299 if ( f_full ) {
300 netif_trans_update(dev);
301 netif_stop_queue(dev);
302
303 IFX_REG_W32_MASK(0, 1 << 17, MBOX_IGU1_ISRC);
304 IFX_REG_W32_MASK(0, 1 << 17, MBOX_IGU1_IER);
305 }
306 if ( desc_base < 0 )
307 goto PTM_HARD_START_XMIT_FAIL;
308 desc = &CPU_TO_WAN_TX_DESC_BASE[desc_base];
309
310 byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
311 if ( skb_headroom(skb) < sizeof(struct sk_buff *) + byteoff || skb_cloned(skb) ) {
312 struct sk_buff *new_skb;
313
314 ASSERT(skb_headroom(skb) >= sizeof(struct sk_buff *) + byteoff, "skb_headroom(skb) < sizeof(struct sk_buff *) + byteoff");
315 ASSERT(!skb_cloned(skb), "skb is cloned");
316
317 new_skb = alloc_skb_tx(skb->len);
318 if ( new_skb == NULL ) {
319 dbg("no memory");
320 goto ALLOC_SKB_TX_FAIL;
321 }
322 skb_put(new_skb, skb->len);
323 memcpy(new_skb->data, skb->data, skb->len);
324 dev_kfree_skb_any(skb);
325 skb = new_skb;
326 byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
327 /* write back to physical memory */
328 dma_cache_wback((unsigned long)skb->data, skb->len);
329 }
330
331 /* make the skb unowned */
332 skb_orphan(skb);
333
334 *(struct sk_buff **)((unsigned int)skb->data - byteoff - sizeof(struct sk_buff *)) = skb;
335 /* write back to physical memory */
336 dma_cache_wback((unsigned long)skb->data - byteoff - sizeof(struct sk_buff *), skb->len + byteoff + sizeof(struct sk_buff *));
337
338 /* free previous skb */
339 skb_to_free = get_skb_pointer(desc->dataptr);
340 if ( skb_to_free != NULL )
341 dev_kfree_skb_any(skb_to_free);
342
343 /* update descriptor */
344 reg_desc.small = 0;
345 reg_desc.dataptr = (unsigned int)skb->data & (0x0FFFFFFF ^ (DATA_BUFFER_ALIGNMENT - 1));
346 reg_desc.datalen = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
347 reg_desc.qid = g_ptm_prio_queue_map[skb->priority > 7 ? 7 : skb->priority];
348 reg_desc.byteoff = byteoff;
349 reg_desc.own = 1;
350 reg_desc.c = 1;
351 reg_desc.sop = reg_desc.eop = 1;
352
353 /* update MIB */
354 g_ptm_priv_data.itf[0].stats.tx_packets++;
355 g_ptm_priv_data.itf[0].stats.tx_bytes += reg_desc.datalen;
356
357 /* write discriptor to memory */
358 *((volatile unsigned int *)desc + 1) = *((unsigned int *)&reg_desc + 1);
359 wmb();
360 *(volatile unsigned int *)desc = *(unsigned int *)&reg_desc;
361
362 netif_trans_update(dev);
363
364 return 0;
365
366 ALLOC_SKB_TX_FAIL:
367 PTM_HARD_START_XMIT_FAIL:
368 dev_kfree_skb_any(skb);
369 g_ptm_priv_data.itf[0].stats.tx_dropped++;
370 return 0;
371 }
372
373 static int ptm_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
374 {
375 ASSERT(dev == g_net_dev[0], "incorrect device");
376
377 switch ( cmd )
378 {
379 case IFX_PTM_MIB_CW_GET:
380 ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifRxNoIdleCodewords = IFX_REG_R32(DREG_AR_CELL0) + IFX_REG_R32(DREG_AR_CELL1);
381 ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifRxIdleCodewords = IFX_REG_R32(DREG_AR_IDLE_CNT0) + IFX_REG_R32(DREG_AR_IDLE_CNT1);
382 ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifRxCodingViolation = IFX_REG_R32(DREG_AR_CVN_CNT0) + IFX_REG_R32(DREG_AR_CVN_CNT1) + IFX_REG_R32(DREG_AR_CVNP_CNT0) + IFX_REG_R32(DREG_AR_CVNP_CNT1);
383 ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifTxNoIdleCodewords = IFX_REG_R32(DREG_AT_CELL0) + IFX_REG_R32(DREG_AT_CELL1);
384 ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifTxIdleCodewords = IFX_REG_R32(DREG_AT_IDLE_CNT0) + IFX_REG_R32(DREG_AT_IDLE_CNT1);
385 break;
386 case IFX_PTM_MIB_FRAME_GET:
387 {
388 PTM_FRAME_MIB_T data = {0};
389 int i;
390
391 data.RxCorrect = IFX_REG_R32(DREG_AR_HEC_CNT0) + IFX_REG_R32(DREG_AR_HEC_CNT1) + IFX_REG_R32(DREG_AR_AIIDLE_CNT0) + IFX_REG_R32(DREG_AR_AIIDLE_CNT1);
392 for ( i = 0; i < 4; i++ )
393 data.RxDropped += WAN_RX_MIB_TABLE(i)->wrx_dropdes_pdu;
394 for ( i = 0; i < 8; i++ )
395 data.TxSend += WAN_TX_MIB_TABLE(i)->wtx_total_pdu;
396
397 *((PTM_FRAME_MIB_T *)ifr->ifr_data) = data;
398 }
399 break;
400 case IFX_PTM_CFG_GET:
401 // use bear channel 0 preemption gamma interface settings
402 ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcPresent = 1;
403 ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcCheck = RX_GAMMA_ITF_CFG(0)->rx_eth_fcs_ver_dis == 0 ? 1 : 0;
404 ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcCheck = RX_GAMMA_ITF_CFG(0)->rx_tc_crc_ver_dis == 0 ? 1 : 0;;
405 ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcLen = RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size == 0 ? 0 : (RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size * 16);
406 ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxEthCrcGen = TX_GAMMA_ITF_CFG(0)->tx_eth_fcs_gen_dis == 0 ? 1 : 0;
407 ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcGen = TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size == 0 ? 0 : 1;
408 ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcLen = TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size == 0 ? 0 : (TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size * 16);
409 break;
410 case IFX_PTM_CFG_SET:
411 {
412 int i;
413
414 for ( i = 0; i < 4; i++ ) {
415 RX_GAMMA_ITF_CFG(i)->rx_eth_fcs_ver_dis = ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcCheck ? 0 : 1;
416
417 RX_GAMMA_ITF_CFG(0)->rx_tc_crc_ver_dis = ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcCheck ? 0 : 1;
418
419 switch ( ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcLen ) {
420 case 16: RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size = 1; break;
421 case 32: RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size = 2; break;
422 default: RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size = 0;
423 }
424
425 TX_GAMMA_ITF_CFG(0)->tx_eth_fcs_gen_dis = ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxEthCrcGen ? 0 : 1;
426
427 if ( ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcGen ) {
428 switch ( ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcLen ) {
429 case 16: TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size = 1; break;
430 case 32: TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size = 2; break;
431 default: TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size = 0;
432 }
433 }
434 else
435 TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size = 0;
436 }
437 }
438 break;
439 case IFX_PTM_MAP_PKT_PRIO_TO_Q:
440 {
441 struct ppe_prio_q_map cmd;
442
443 if ( copy_from_user(&cmd, ifr->ifr_data, sizeof(cmd)) )
444 return -EFAULT;
445
446 if ( cmd.pkt_prio < 0 || cmd.pkt_prio >= ARRAY_SIZE(g_ptm_prio_queue_map) )
447 return -EINVAL;
448
449 if ( cmd.qid < 0 || cmd.qid >= g_wanqos_en )
450 return -EINVAL;
451
452 g_ptm_prio_queue_map[cmd.pkt_prio] = cmd.qid;
453 }
454 break;
455 default:
456 return -EOPNOTSUPP;
457 }
458
459 return 0;
460 }
461
462 #if LINUX_VERSION_CODE < KERNEL_VERSION(5,6,0)
463 static void ptm_tx_timeout(struct net_device *dev)
464 #else
465 static void ptm_tx_timeout(struct net_device *dev, unsigned int txqueue)
466 #endif
467 {
468 ASSERT(dev == g_net_dev[0], "incorrect device");
469
470 /* disable TX irq, release skb when sending new packet */
471 IFX_REG_W32_MASK(1 << 17, 0, MBOX_IGU1_IER);
472
473 /* wake up TX queue */
474 netif_wake_queue(dev);
475
476 return;
477 }
478
479 static inline struct sk_buff* alloc_skb_rx(void)
480 {
481 struct sk_buff *skb;
482
483 /* allocate memroy including trailer and padding */
484 skb = dev_alloc_skb(RX_MAX_BUFFER_SIZE + DATA_BUFFER_ALIGNMENT);
485 if ( skb != NULL ) {
486 /* must be burst length alignment and reserve two more bytes for MAC address alignment */
487 if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 )
488 skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));
489 /* pub skb in reserved area "skb->data - 4" */
490 *((struct sk_buff **)skb->data - 1) = skb;
491 wmb();
492 /* write back and invalidate cache */
493 dma_cache_wback_inv((unsigned long)skb->data - sizeof(skb), sizeof(skb));
494 /* invalidate cache */
495 dma_cache_inv((unsigned long)skb->data, (unsigned int)skb->end - (unsigned int)skb->data);
496 }
497
498 return skb;
499 }
500
501 static inline struct sk_buff* alloc_skb_tx(unsigned int size)
502 {
503 struct sk_buff *skb;
504
505 /* allocate memory including padding */
506 size = RX_MAX_BUFFER_SIZE;
507 size = (size + DATA_BUFFER_ALIGNMENT - 1) & ~(DATA_BUFFER_ALIGNMENT - 1);
508 skb = dev_alloc_skb(size + DATA_BUFFER_ALIGNMENT);
509 /* must be burst length alignment */
510 if ( skb != NULL )
511 skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));
512 return skb;
513 }
514
515 static inline struct sk_buff *get_skb_pointer(unsigned int dataptr)
516 {
517 unsigned int skb_dataptr;
518 struct sk_buff *skb;
519
520 // usually, CPE memory is less than 256M bytes
521 // so NULL means invalid pointer
522 if ( dataptr == 0 ) {
523 dbg("dataptr is 0, it's supposed to be invalid pointer");
524 return NULL;
525 }
526
527 skb_dataptr = (dataptr - 4) | KSEG1;
528 skb = *(struct sk_buff **)skb_dataptr;
529
530 ASSERT((unsigned int)skb >= KSEG0, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb, dataptr);
531 ASSERT((((unsigned int)skb->data & (0x0FFFFFFF ^ (DATA_BUFFER_ALIGNMENT - 1))) | KSEG1) == (dataptr | KSEG1), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb, (unsigned int)skb->data, dataptr);
532
533 return skb;
534 }
535
536 static inline int get_tx_desc(unsigned int itf, unsigned int *f_full)
537 {
538 int desc_base = -1;
539 struct ptm_itf *p_itf = &g_ptm_priv_data.itf[0];
540
541 // assume TX is serial operation
542 // no protection provided
543
544 *f_full = 1;
545
546 if ( CPU_TO_WAN_TX_DESC_BASE[p_itf->tx_desc_pos].own == 0 ) {
547 desc_base = p_itf->tx_desc_pos;
548 if ( ++(p_itf->tx_desc_pos) == CPU_TO_WAN_TX_DESC_NUM )
549 p_itf->tx_desc_pos = 0;
550 if ( CPU_TO_WAN_TX_DESC_BASE[p_itf->tx_desc_pos].own == 0 )
551 *f_full = 0;
552 }
553
554 return desc_base;
555 }
556
557 static irqreturn_t mailbox_irq_handler(int irq, void *dev_id)
558 {
559 unsigned int isr;
560 int i;
561
562 isr = IFX_REG_R32(MBOX_IGU1_ISR);
563 IFX_REG_W32(isr, MBOX_IGU1_ISRC);
564 isr &= IFX_REG_R32(MBOX_IGU1_IER);
565
566 if (isr & BIT(0)) {
567 IFX_REG_W32_MASK(1, 0, MBOX_IGU1_IER);
568 napi_schedule(&g_ptm_priv_data.itf[0].napi);
569 #if defined(ENABLE_TMP_DBG) && ENABLE_TMP_DBG
570 {
571 volatile struct rx_descriptor *desc = &WAN_RX_DESC_BASE[g_ptm_priv_data.itf[0].rx_desc_pos];
572
573 if ( desc->own ) { // PP32 hold
574 err("invalid interrupt");
575 }
576 }
577 #endif
578 }
579 if (isr & BIT(16)) {
580 IFX_REG_W32_MASK(1 << 16, 0, MBOX_IGU1_IER);
581 tasklet_hi_schedule(&g_swap_desc_tasklet);
582 }
583 if (isr & BIT(17)) {
584 IFX_REG_W32_MASK(1 << 17, 0, MBOX_IGU1_IER);
585 netif_wake_queue(g_net_dev[0]);
586 }
587
588 return IRQ_HANDLED;
589 }
590
591 static void do_swap_desc_tasklet(unsigned long arg)
592 {
593 int budget = 32;
594 volatile struct tx_descriptor *desc;
595 struct sk_buff *skb;
596 unsigned int byteoff;
597
598 while ( budget-- > 0 ) {
599 if ( WAN_SWAP_DESC_BASE[g_ptm_priv_data.itf[0].tx_swap_desc_pos].own ) // if PP32 hold descriptor
600 break;
601
602 desc = &WAN_SWAP_DESC_BASE[g_ptm_priv_data.itf[0].tx_swap_desc_pos];
603 if ( ++g_ptm_priv_data.itf[0].tx_swap_desc_pos == WAN_SWAP_DESC_NUM )
604 g_ptm_priv_data.itf[0].tx_swap_desc_pos = 0;
605
606 skb = get_skb_pointer(desc->dataptr);
607 if ( skb != NULL )
608 dev_kfree_skb_any(skb);
609
610 skb = alloc_skb_tx(RX_MAX_BUFFER_SIZE);
611 if ( skb == NULL )
612 panic("can't allocate swap buffer for PPE firmware use\n");
613 byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
614 *(struct sk_buff **)((unsigned int)skb->data - byteoff - sizeof(struct sk_buff *)) = skb;
615
616 desc->dataptr = (unsigned int)skb->data & 0x0FFFFFFF;
617 desc->own = 1;
618 }
619
620 // clear interrupt
621 IFX_REG_W32_MASK(0, 16, MBOX_IGU1_ISRC);
622 // no more skb to be replaced
623 if ( WAN_SWAP_DESC_BASE[g_ptm_priv_data.itf[0].tx_swap_desc_pos].own ) { // if PP32 hold descriptor
624 IFX_REG_W32_MASK(0, 1 << 16, MBOX_IGU1_IER);
625 return;
626 }
627
628 tasklet_hi_schedule(&g_swap_desc_tasklet);
629 return;
630 }
631
632
633 static inline int ifx_ptm_version(char *buf)
634 {
635 int len = 0;
636 unsigned int major, mid, minor;
637
638 ifx_ptm_get_fw_ver(&major, &mid, &minor);
639
640 len += ifx_drv_ver(buf + len, "PTM", IFX_PTM_VER_MAJOR, IFX_PTM_VER_MID, IFX_PTM_VER_MINOR);
641 if ( mid == ~0 )
642 len += sprintf(buf + len, " PTM (E1) firmware version %u.%u\n", major, minor);
643 else
644 len += sprintf(buf + len, " PTM (E1) firmware version %u.%u.%u\n", major, mid, minor);
645
646 return len;
647 }
648
649 static inline int init_priv_data(void)
650 {
651 int i, j;
652
653 g_wanqos_en = wanqos_en ? wanqos_en : 8;
654 if ( g_wanqos_en > 8 )
655 g_wanqos_en = 8;
656
657 for ( i = 0; i < ARRAY_SIZE(g_queue_gamma_map); i++ )
658 {
659 g_queue_gamma_map[i] = queue_gamma_map[i] & ((1 << g_wanqos_en) - 1);
660 for ( j = 0; j < i; j++ )
661 g_queue_gamma_map[i] &= ~g_queue_gamma_map[j];
662 }
663
664 memset(&g_ptm_priv_data, 0, sizeof(g_ptm_priv_data));
665
666 {
667 int max_packet_priority = ARRAY_SIZE(g_ptm_prio_queue_map);
668 int tx_num_q;
669 int q_step, q_accum, p_step;
670
671 tx_num_q = __ETH_WAN_TX_QUEUE_NUM;
672 q_step = tx_num_q - 1;
673 p_step = max_packet_priority - 1;
674 for ( j = 0, q_accum = 0; j < max_packet_priority; j++, q_accum += q_step )
675 g_ptm_prio_queue_map[j] = q_step - (q_accum + (p_step >> 1)) / p_step;
676 }
677
678 return 0;
679 }
680
681 static inline void clear_priv_data(void)
682 {
683 }
684
685 static inline int init_tables(void)
686 {
687 struct sk_buff *skb_pool[WAN_RX_DESC_NUM] = {0};
688 struct cfg_std_data_len cfg_std_data_len = {0};
689 struct tx_qos_cfg tx_qos_cfg = {0};
690 struct psave_cfg psave_cfg = {0};
691 struct eg_bwctrl_cfg eg_bwctrl_cfg = {0};
692 struct test_mode test_mode = {0};
693 struct rx_bc_cfg rx_bc_cfg = {0};
694 struct tx_bc_cfg tx_bc_cfg = {0};
695 struct gpio_mode gpio_mode = {0};
696 struct gpio_wm_cfg gpio_wm_cfg = {0};
697 struct rx_gamma_itf_cfg rx_gamma_itf_cfg = {0};
698 struct tx_gamma_itf_cfg tx_gamma_itf_cfg = {0};
699 struct wtx_qos_q_desc_cfg wtx_qos_q_desc_cfg = {0};
700 struct rx_descriptor rx_desc = {0};
701 struct tx_descriptor tx_desc = {0};
702 int i;
703
704 for ( i = 0; i < WAN_RX_DESC_NUM; i++ ) {
705 skb_pool[i] = alloc_skb_rx();
706 if ( skb_pool[i] == NULL )
707 goto ALLOC_SKB_RX_FAIL;
708 }
709
710 cfg_std_data_len.byte_off = RX_HEAD_MAC_ADDR_ALIGNMENT; // this field replaces byte_off in rx descriptor of VDSL ingress
711 cfg_std_data_len.data_len = 1600;
712 *CFG_STD_DATA_LEN = cfg_std_data_len;
713
714 tx_qos_cfg.time_tick = cgu_get_pp32_clock() / 62500; // 16 * (cgu_get_pp32_clock() / 1000000)
715 tx_qos_cfg.overhd_bytes = 0;
716 tx_qos_cfg.eth1_eg_qnum = __ETH_WAN_TX_QUEUE_NUM;
717 tx_qos_cfg.eth1_burst_chk = 1;
718 tx_qos_cfg.eth1_qss = 0;
719 tx_qos_cfg.shape_en = 0; // disable
720 tx_qos_cfg.wfq_en = 0; // strict priority
721 *TX_QOS_CFG = tx_qos_cfg;
722
723 psave_cfg.start_state = 0;
724 psave_cfg.sleep_en = 1; // enable sleep mode
725 *PSAVE_CFG = psave_cfg;
726
727 eg_bwctrl_cfg.fdesc_wm = 16;
728 eg_bwctrl_cfg.class_len = 128;
729 *EG_BWCTRL_CFG = eg_bwctrl_cfg;
730
731 //*GPIO_ADDR = (unsigned int)IFX_GPIO_P0_OUT;
732 *GPIO_ADDR = (unsigned int)0x00000000; // disabled by default
733
734 gpio_mode.gpio_bit_bc1 = 2;
735 gpio_mode.gpio_bit_bc0 = 1;
736 gpio_mode.gpio_bc1_en = 0;
737 gpio_mode.gpio_bc0_en = 0;
738 *GPIO_MODE = gpio_mode;
739
740 gpio_wm_cfg.stop_wm_bc1 = 2;
741 gpio_wm_cfg.start_wm_bc1 = 4;
742 gpio_wm_cfg.stop_wm_bc0 = 2;
743 gpio_wm_cfg.start_wm_bc0 = 4;
744 *GPIO_WM_CFG = gpio_wm_cfg;
745
746 test_mode.mib_clear_mode = 0;
747 test_mode.test_mode = 0;
748 *TEST_MODE = test_mode;
749
750 rx_bc_cfg.local_state = 0;
751 rx_bc_cfg.remote_state = 0;
752 rx_bc_cfg.to_false_th = 7;
753 rx_bc_cfg.to_looking_th = 3;
754 *RX_BC_CFG(0) = rx_bc_cfg;
755 *RX_BC_CFG(1) = rx_bc_cfg;
756
757 tx_bc_cfg.fill_wm = 2;
758 tx_bc_cfg.uflw_wm = 2;
759 *TX_BC_CFG(0) = tx_bc_cfg;
760 *TX_BC_CFG(1) = tx_bc_cfg;
761
762 rx_gamma_itf_cfg.receive_state = 0;
763 rx_gamma_itf_cfg.rx_min_len = 60;
764 rx_gamma_itf_cfg.rx_pad_en = 1;
765 rx_gamma_itf_cfg.rx_eth_fcs_ver_dis = 0;
766 rx_gamma_itf_cfg.rx_rm_eth_fcs = 1;
767 rx_gamma_itf_cfg.rx_tc_crc_ver_dis = 0;
768 rx_gamma_itf_cfg.rx_tc_crc_size = 1;
769 rx_gamma_itf_cfg.rx_eth_fcs_result = 0xC704DD7B;
770 rx_gamma_itf_cfg.rx_tc_crc_result = 0x1D0F1D0F;
771 rx_gamma_itf_cfg.rx_crc_cfg = 0x2500;
772 rx_gamma_itf_cfg.rx_eth_fcs_init_value = 0xFFFFFFFF;
773 rx_gamma_itf_cfg.rx_tc_crc_init_value = 0x0000FFFF;
774 rx_gamma_itf_cfg.rx_max_len_sel = 0;
775 rx_gamma_itf_cfg.rx_edit_num2 = 0;
776 rx_gamma_itf_cfg.rx_edit_pos2 = 0;
777 rx_gamma_itf_cfg.rx_edit_type2 = 0;
778 rx_gamma_itf_cfg.rx_edit_en2 = 0;
779 rx_gamma_itf_cfg.rx_edit_num1 = 0;
780 rx_gamma_itf_cfg.rx_edit_pos1 = 0;
781 rx_gamma_itf_cfg.rx_edit_type1 = 0;
782 rx_gamma_itf_cfg.rx_edit_en1 = 0;
783 rx_gamma_itf_cfg.rx_inserted_bytes_1l = 0;
784 rx_gamma_itf_cfg.rx_inserted_bytes_1h = 0;
785 rx_gamma_itf_cfg.rx_inserted_bytes_2l = 0;
786 rx_gamma_itf_cfg.rx_inserted_bytes_2h = 0;
787 rx_gamma_itf_cfg.rx_len_adj = -6;
788 for ( i = 0; i < 4; i++ )
789 *RX_GAMMA_ITF_CFG(i) = rx_gamma_itf_cfg;
790
791 tx_gamma_itf_cfg.tx_len_adj = 6;
792 tx_gamma_itf_cfg.tx_crc_off_adj = 6;
793 tx_gamma_itf_cfg.tx_min_len = 0;
794 tx_gamma_itf_cfg.tx_eth_fcs_gen_dis = 0;
795 tx_gamma_itf_cfg.tx_tc_crc_size = 1;
796 tx_gamma_itf_cfg.tx_crc_cfg = 0x2F00;
797 tx_gamma_itf_cfg.tx_eth_fcs_init_value = 0xFFFFFFFF;
798 tx_gamma_itf_cfg.tx_tc_crc_init_value = 0x0000FFFF;
799 for ( i = 0; i < ARRAY_SIZE(g_queue_gamma_map); i++ ) {
800 tx_gamma_itf_cfg.queue_mapping = g_queue_gamma_map[i];
801 *TX_GAMMA_ITF_CFG(i) = tx_gamma_itf_cfg;
802 }
803
804 for ( i = 0; i < __ETH_WAN_TX_QUEUE_NUM; i++ ) {
805 wtx_qos_q_desc_cfg.length = WAN_TX_DESC_NUM;
806 wtx_qos_q_desc_cfg.addr = __ETH_WAN_TX_DESC_BASE(i);
807 *WTX_QOS_Q_DESC_CFG(i) = wtx_qos_q_desc_cfg;
808 }
809
810 // default TX queue QoS config is all ZERO
811
812 // TX Ctrl K Table
813 IFX_REG_W32(0x90111293, TX_CTRL_K_TABLE(0));
814 IFX_REG_W32(0x14959617, TX_CTRL_K_TABLE(1));
815 IFX_REG_W32(0x18999A1B, TX_CTRL_K_TABLE(2));
816 IFX_REG_W32(0x9C1D1E9F, TX_CTRL_K_TABLE(3));
817 IFX_REG_W32(0xA02122A3, TX_CTRL_K_TABLE(4));
818 IFX_REG_W32(0x24A5A627, TX_CTRL_K_TABLE(5));
819 IFX_REG_W32(0x28A9AA2B, TX_CTRL_K_TABLE(6));
820 IFX_REG_W32(0xAC2D2EAF, TX_CTRL_K_TABLE(7));
821 IFX_REG_W32(0x30B1B233, TX_CTRL_K_TABLE(8));
822 IFX_REG_W32(0xB43536B7, TX_CTRL_K_TABLE(9));
823 IFX_REG_W32(0xB8393ABB, TX_CTRL_K_TABLE(10));
824 IFX_REG_W32(0x3CBDBE3F, TX_CTRL_K_TABLE(11));
825 IFX_REG_W32(0xC04142C3, TX_CTRL_K_TABLE(12));
826 IFX_REG_W32(0x44C5C647, TX_CTRL_K_TABLE(13));
827 IFX_REG_W32(0x48C9CA4B, TX_CTRL_K_TABLE(14));
828 IFX_REG_W32(0xCC4D4ECF, TX_CTRL_K_TABLE(15));
829
830 // init RX descriptor
831 rx_desc.own = 1;
832 rx_desc.c = 0;
833 rx_desc.sop = 1;
834 rx_desc.eop = 1;
835 rx_desc.byteoff = RX_HEAD_MAC_ADDR_ALIGNMENT;
836 rx_desc.datalen = RX_MAX_BUFFER_SIZE - RX_HEAD_MAC_ADDR_ALIGNMENT;
837 for ( i = 0; i < WAN_RX_DESC_NUM; i++ ) {
838 rx_desc.dataptr = (unsigned int)skb_pool[i]->data & 0x0FFFFFFF;
839 WAN_RX_DESC_BASE[i] = rx_desc;
840 }
841
842 // init TX descriptor
843 tx_desc.own = 0;
844 tx_desc.c = 0;
845 tx_desc.sop = 1;
846 tx_desc.eop = 1;
847 tx_desc.byteoff = 0;
848 tx_desc.qid = 0;
849 tx_desc.datalen = 0;
850 tx_desc.small = 0;
851 tx_desc.dataptr = 0;
852 for ( i = 0; i < CPU_TO_WAN_TX_DESC_NUM; i++ )
853 CPU_TO_WAN_TX_DESC_BASE[i] = tx_desc;
854 for ( i = 0; i < WAN_TX_DESC_NUM_TOTAL; i++ )
855 WAN_TX_DESC_BASE(0)[i] = tx_desc;
856
857 // init Swap descriptor
858 for ( i = 0; i < WAN_SWAP_DESC_NUM; i++ )
859 WAN_SWAP_DESC_BASE[i] = tx_desc;
860
861 // init fastpath TX descriptor
862 tx_desc.own = 1;
863 for ( i = 0; i < FASTPATH_TO_WAN_TX_DESC_NUM; i++ )
864 FASTPATH_TO_WAN_TX_DESC_BASE[i] = tx_desc;
865
866 return 0;
867
868 ALLOC_SKB_RX_FAIL:
869 while ( i-- > 0 )
870 dev_kfree_skb_any(skb_pool[i]);
871 return -1;
872 }
873
874 static inline void clear_tables(void)
875 {
876 struct sk_buff *skb;
877 int i, j;
878
879 for ( i = 0; i < WAN_RX_DESC_NUM; i++ ) {
880 skb = get_skb_pointer(WAN_RX_DESC_BASE[i].dataptr);
881 if ( skb != NULL )
882 dev_kfree_skb_any(skb);
883 }
884
885 for ( i = 0; i < CPU_TO_WAN_TX_DESC_NUM; i++ ) {
886 skb = get_skb_pointer(CPU_TO_WAN_TX_DESC_BASE[i].dataptr);
887 if ( skb != NULL )
888 dev_kfree_skb_any(skb);
889 }
890
891 for ( j = 0; j < 8; j++ )
892 for ( i = 0; i < WAN_TX_DESC_NUM; i++ ) {
893 skb = get_skb_pointer(WAN_TX_DESC_BASE(j)[i].dataptr);
894 if ( skb != NULL )
895 dev_kfree_skb_any(skb);
896 }
897
898 for ( i = 0; i < WAN_SWAP_DESC_NUM; i++ ) {
899 skb = get_skb_pointer(WAN_SWAP_DESC_BASE[i].dataptr);
900 if ( skb != NULL )
901 dev_kfree_skb_any(skb);
902 }
903
904 for ( i = 0; i < FASTPATH_TO_WAN_TX_DESC_NUM; i++ ) {
905 skb = get_skb_pointer(FASTPATH_TO_WAN_TX_DESC_BASE[i].dataptr);
906 if ( skb != NULL )
907 dev_kfree_skb_any(skb);
908 }
909 }
910
911 static int ptm_showtime_enter(struct port_cell_info *port_cell, void *xdata_addr)
912 {
913 int i;
914
915 ASSERT(port_cell != NULL, "port_cell is NULL");
916 ASSERT(xdata_addr != NULL, "xdata_addr is NULL");
917
918 // TODO: ReTX set xdata_addr
919 g_xdata_addr = xdata_addr;
920
921 g_showtime = 1;
922
923 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )
924 netif_carrier_on(g_net_dev[i]);
925
926 IFX_REG_W32(0x0F, UTP_CFG);
927
928 //#ifdef CONFIG_VR9
929 // IFX_REG_W32_MASK(1 << 17, 0, FFSM_CFG0);
930 //#endif
931
932 printk("enter showtime\n");
933
934 return 0;
935 }
936
937 static int ptm_showtime_exit(void)
938 {
939 int i;
940
941 if ( !g_showtime )
942 return -1;
943
944 //#ifdef CONFIG_VR9
945 // IFX_REG_W32_MASK(0, 1 << 17, FFSM_CFG0);
946 //#endif
947
948 IFX_REG_W32(0x00, UTP_CFG);
949
950 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )
951 netif_carrier_off(g_net_dev[i]);
952
953 g_showtime = 0;
954
955 // TODO: ReTX clean state
956 g_xdata_addr = NULL;
957
958 printk("leave showtime\n");
959
960 return 0;
961 }
962
963 static const struct of_device_id ltq_ptm_match[] = {
964 #ifdef CONFIG_DANUBE
965 { .compatible = "lantiq,ppe-danube", .data = NULL },
966 #elif defined CONFIG_AMAZON_SE
967 { .compatible = "lantiq,ppe-ase", .data = NULL },
968 #elif defined CONFIG_AR9
969 { .compatible = "lantiq,ppe-arx100", .data = NULL },
970 #elif defined CONFIG_VR9
971 { .compatible = "lantiq,ppe-xrx200", .data = NULL },
972 #endif
973 {},
974 };
975 MODULE_DEVICE_TABLE(of, ltq_ptm_match);
976
977 static int ltq_ptm_probe(struct platform_device *pdev)
978 {
979 int ret;
980 int i;
981 char ver_str[256];
982 struct port_cell_info port_cell = {0};
983
984 ret = init_priv_data();
985 if ( ret != 0 ) {
986 err("INIT_PRIV_DATA_FAIL");
987 goto INIT_PRIV_DATA_FAIL;
988 }
989
990 ifx_ptm_init_chip(pdev);
991 ret = init_tables();
992 if ( ret != 0 ) {
993 err("INIT_TABLES_FAIL");
994 goto INIT_TABLES_FAIL;
995 }
996
997 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ ) {
998 g_net_dev[i] = alloc_netdev(0, g_net_dev_name[i], NET_NAME_UNKNOWN, ether_setup);
999 if ( g_net_dev[i] == NULL )
1000 goto ALLOC_NETDEV_FAIL;
1001 ptm_setup(g_net_dev[i], i);
1002 }
1003
1004 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ ) {
1005 ret = register_netdev(g_net_dev[i]);
1006 if ( ret != 0 )
1007 goto REGISTER_NETDEV_FAIL;
1008 }
1009
1010 /* register interrupt handler */
1011 ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "ptm_mailbox_isr", &g_ptm_priv_data);
1012 if ( ret ) {
1013 if ( ret == -EBUSY ) {
1014 err("IRQ may be occupied by other driver, please reconfig to disable it.");
1015 }
1016 else {
1017 err("request_irq fail");
1018 }
1019 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
1020 }
1021 disable_irq(PPE_MAILBOX_IGU1_INT);
1022
1023 ret = ifx_pp32_start(0);
1024 if ( ret ) {
1025 err("ifx_pp32_start fail!");
1026 goto PP32_START_FAIL;
1027 }
1028 IFX_REG_W32(1 << 16, MBOX_IGU1_IER); // enable SWAP interrupt
1029 IFX_REG_W32(~0, MBOX_IGU1_ISRC);
1030
1031 enable_irq(PPE_MAILBOX_IGU1_INT);
1032
1033 ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr);
1034 if ( g_showtime ) {
1035 ptm_showtime_enter(&port_cell, &g_xdata_addr);
1036 }
1037
1038 ifx_mei_atm_showtime_enter = ptm_showtime_enter;
1039 ifx_mei_atm_showtime_exit = ptm_showtime_exit;
1040
1041 ifx_ptm_version(ver_str);
1042 printk(KERN_INFO "%s", ver_str);
1043
1044 printk("ifxmips_ptm: PTM init succeed\n");
1045
1046 return 0;
1047
1048 PP32_START_FAIL:
1049 free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);
1050 REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
1051 i = ARRAY_SIZE(g_net_dev);
1052 REGISTER_NETDEV_FAIL:
1053 while ( i-- )
1054 unregister_netdev(g_net_dev[i]);
1055 i = ARRAY_SIZE(g_net_dev);
1056 ALLOC_NETDEV_FAIL:
1057 while ( i-- ) {
1058 free_netdev(g_net_dev[i]);
1059 g_net_dev[i] = NULL;
1060 }
1061 INIT_TABLES_FAIL:
1062 INIT_PRIV_DATA_FAIL:
1063 clear_priv_data();
1064 printk("ifxmips_ptm: PTM init failed\n");
1065 return ret;
1066 }
1067
1068 static int ltq_ptm_remove(struct platform_device *pdev)
1069 {
1070 int i;
1071 ifx_mei_atm_showtime_enter = NULL;
1072 ifx_mei_atm_showtime_exit = NULL;
1073
1074
1075 ifx_pp32_stop(0);
1076
1077 free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);
1078
1079 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )
1080 unregister_netdev(g_net_dev[i]);
1081
1082 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ ) {
1083 free_netdev(g_net_dev[i]);
1084 g_net_dev[i] = NULL;
1085 }
1086
1087 clear_tables();
1088
1089 ifx_ptm_uninit_chip();
1090
1091 clear_priv_data();
1092
1093 return 0;
1094 }
1095
1096 #ifndef MODULE
1097 static int __init wanqos_en_setup(char *line)
1098 {
1099 wanqos_en = simple_strtoul(line, NULL, 0);
1100
1101 if ( wanqos_en < 1 || wanqos_en > 8 )
1102 wanqos_en = 0;
1103
1104 return 0;
1105 }
1106
1107 static int __init queue_gamma_map_setup(char *line)
1108 {
1109 char *p;
1110 int i;
1111
1112 for ( i = 0, p = line; i < ARRAY_SIZE(queue_gamma_map) && isxdigit(*p); i++ )
1113 {
1114 queue_gamma_map[i] = simple_strtoul(p, &p, 0);
1115 if ( *p == ',' || *p == ';' || *p == ':' )
1116 p++;
1117 }
1118
1119 return 0;
1120 }
1121 #endif
1122 static struct platform_driver ltq_ptm_driver = {
1123 .probe = ltq_ptm_probe,
1124 .remove = ltq_ptm_remove,
1125 .driver = {
1126 .name = "ptm",
1127 .owner = THIS_MODULE,
1128 .of_match_table = ltq_ptm_match,
1129 },
1130 };
1131
1132 module_platform_driver(ltq_ptm_driver);
1133 #ifndef MODULE
1134 __setup("wanqos_en=", wanqos_en_setup);
1135 __setup("queue_gamma_map=", queue_gamma_map_setup);
1136 #endif
1137
1138 MODULE_LICENSE("GPL");
Staging tree of Mathias Kresin